CN110071803A - A kind of totally digital circuit real random number generator - Google Patents
A kind of totally digital circuit real random number generator Download PDFInfo
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- CN110071803A CN110071803A CN201910368663.1A CN201910368663A CN110071803A CN 110071803 A CN110071803 A CN 110071803A CN 201910368663 A CN201910368663 A CN 201910368663A CN 110071803 A CN110071803 A CN 110071803A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
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Abstract
The invention discloses a kind of totally digital circuit real random number generator, the generator includes entropy source circuit, sample circuit and output register circuit, and the sample circuit is connected with the entropy source circuit；The generator further includes post processing circuitry, the post processing circuitry is arranged between the sample circuit and the output register circuit and is respectively connected with the two, the post processing circuitry includes the linear feedback shift register being connected with the sample circuit, the detection circuit being connected with the linear feedback shift register and is connected with the detection circuit and randomly selects circuit, the output register circuit is connected with the circuit of randomly selecting, to randomly select the output of circuit described in latch.Advantage is: the present invention has the characteristics that circuit structure is simple, is easily achieved, quality of random numbers is higher, is evenly distributed, is unpredictable, low-power consumption, attack resistance, has the reference of very strong engineering and applying value.
Description
Technical field
The present invention relates to crypto chip security fields more particularly to a kind of totally digital circuit real random number generators.
Background technique
Smart card is one of the encryption device that crypto chip is most widely used, and in order to ensure the safety of smart card, is needed
Random number is relied on to generate uncertain key.For random number there are two types of generating mode, one kind is pseudo random number generating mode,
One kind is true random number generating mode.Pseudorandom number generator, by one be known as " seed " original state, pass through one
Determining algorithm generates random number, and output sequence has periodically, so being easy to be attacked, safety is not high.True random number
Generator is obtained from random physical process, such as thermal noise, cosmic noise, the radioactive decay of circuit.
Typical real random number generator includes Resistance Thermal Noise, oscillator sample, scattered date etc., it is contemplated that resistance heat
The smaller needs of the amplitude of noise are amplified by the operational amplifier of high-gain, but the limited bandwidth of amplifier and imbalance can make
The stochastic behaviour of random number is deteriorated, and scattered date switching network circuit is excessively complicated, and power consumption is higher, is unable to satisfy the low function of smart card
The design requirement of consumption.Moreover, more stringent requirements are proposed for quality of the smart card standard to random source category and random number, it is desirable that more
A stochastic source, and random number will be evenly distributed, sequence is unrelated, can resist the extraneous physics including side-channel attack and attack
It hits.
Summary of the invention
The purpose of the present invention is to provide a kind of totally digital circuit real random number generators, to solve to deposit in the prior art
Foregoing problems.
To achieve the goals above, The technical solution adopted by the invention is as follows:
A kind of totally digital circuit real random number generator, the generator include that entropy source circuit, sample circuit and output are posted
Latch circuit, the sample circuit are connected with the entropy source circuit；The generator further includes post processing circuitry, the post-processing
Circuit is arranged between the sample circuit and the output register circuit and is respectively connected with the two, the post-processing electricity
The inspection that road includes the linear feedback shift register being connected with the sample circuit, is connected with the linear feedback shift register
Slowdown monitoring circuit and it is connected with the detection circuit and randomly selects circuit, the output register circuit and described randomly selects circuit
It is connected, to randomly select the output of circuit described in latch.
Preferably, the control circuit and the sample circuit, the linear feedback shift register, detection electricity
Circuit described is randomly selected and the output register circuit is respectively connected in road.
Preferably, the entropy source circuit is connected with the sample circuit, the sample circuit use low-frequency sampling clock as
The clock signal at the rising edge triggering end sample circuit D；The output signal of the entropy source circuit is inputted as sample circuit D end data
Signal, and it is sampled in the rising edge of sample clock pulse, a true random number ratio is obtained with the end Q in sample circuit
Spy's stream.
Preferably, the entropy source circuit includes multiple random source circuits, respectively based on metastable first stochastic source electricity
It road, the based on even loop collapse time second random source circuit and is fluttered the random source circuit of dynamic third based on ring, each stochastic source
Circuit can provide data input signal to the end D of sample circuit.
Preferably, the described first random source circuit includes M S/R latch unit, and parallel connection is set between each S/R latch unit
Set and carry out XOR operation, output of the operation result as entropy source circuit；M >=128.
Preferably, the described second random source circuit includes N number of successively end to end phase inverter and two XOR gates, and two is different
Or at a distance of N/2 phase inverter between door；The N is even number.
Preferably, two XOR gates are respectively the first XOR gate and the second XOR gate, and the second random source circuit has two
A signal transmission path is respectively the first signal transmission path and second signal transmission path；First XOR gate only allows
First signal transmission path passes through, and second XOR gate only allows the second transmission path to pass through.
Preferably, the random source circuit of institute's third includes several ring oscillators, each ring oscillator by odd number reverse phase
Device is constituted, and is provided with one and door in each ring oscillator；In the same ring oscillator with door and each phase inverter successively
Join end to end, and on the direction that signal transmits in ring oscillator, the output end in most downstream phase inverter and described and door
Input terminal be connected, it is described to be connected with the input terminal for being in most upstream phase inverter with the output end of door；Different length annular is shaken
The output end for swinging device connects the same third XOR gate two-by-two, carries out exclusive or processing, later connects each third exclusive or gate output terminal
It is connected to the 4th XOR gate.
Preferably, the linear feedback shift register is output it random number sequence is sent into detection circuit, it is described with
For machine Number Sequence with (8m) bit for a unit, m is the bit wide of random number sequence.
Preferably, the generator further includes randomly selecting device circuit, described to randomly select device circuit and detection electricity
Road is connected, for extracting the random number sequence for being sent into detection circuit, to obtain the random number of mbit.
The beneficial effects of the present invention are: the 1, present invention has, circuit structure is simple, be easily achieved, quality of random numbers is higher,
Be evenly distributed, be unpredictable, low-power consumption, attack resistance the characteristics of, have very strong engineering reference and applying value.2, the present invention is set
The soft IP that meter acts not only as intelligent card chip is called for system, to meet the need in system operation to random number
It asks, and can be in other chip developments or FPGA exploitation as the scheme reference of true random number design.
Detailed description of the invention
Fig. 1 is real random number generator overall circuit configuration figure in the embodiment of the present invention；
Fig. 2 is in the embodiment of the present invention based on metastable entropy source circuit diagram；
Fig. 3 is the two-stage S/R latch constituted in the embodiment of the present invention with 4 XOR gates；
Fig. 4 is the entropy source circuit diagram in the embodiment of the present invention based on even loop collapse time；
Fig. 5 is even number collapsed ring schematic diagram in the embodiment of the present invention；
Fig. 6 is the entropy source circuit diagram based on circular type shaker shake in the embodiment of the present invention；
Fig. 7 is 6 tap, 16 linear feedback shift registers in the embodiment of the present invention；
Fig. 8 is the flow chart that device circuit algorithm is randomly selected in the embodiment of the present invention；
Fig. 9 be in the embodiment of the present invention real random number generator far from schematic diagram；
Figure 10 is the work flow diagram of real random number generator in the embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing, to the present invention into
Row is further described.It should be appreciated that the specific embodiments described herein are only used to explain the present invention, it is not used to
Limit the present invention.
As shown in Figure 1, the present invention provides a kind of totally digital circuit real random number generator, the generator includes entropy source
Circuit, sample circuit and output register circuit, the sample circuit are connected with the entropy source circuit；The generator further includes
Post processing circuitry, the post processing circuitry be arranged between the sample circuit and the output register circuit and with the two
Be respectively connected with, the post processing circuitry include the linear feedback shift register being connected with the sample circuit, with it is described linear
The connected detection circuit of feedback shift register and it is connected with the detection circuit and randomly selects circuit, the output register
Circuit is connected with the circuit of randomly selecting, to randomly select the output of circuit described in latch.
In the present embodiment, the control circuit and the sample circuit, the linear feedback shift register, the detection
Circuit described randomly selects circuit and the output register circuit is respectively connected with.
In the present embodiment, the entropy source circuit is connected with the sample circuit, sample circuit low-frequency sampling clock
Clock signal as the rising edge triggering end sample circuit D；The output signal of the entropy source circuit is as sample circuit (triggering
Device) D end data input signal, the sample circuit is exactly trigger, and is adopted in the rising edge of sample clock pulse to it
Sample obtains a true random number bit stream with the end Q in sample circuit.
In the present embodiment, it is most important component in randomizer that entropy source circuit, which is responsible for generating random number,；Sampling electricity
It is responsible for for the randomness in entropy source circuit being quantified as random binary sequence in road；Post processing circuitry target is defeated to sample circuit
Binary sequence out is handled, and is hidden or is eliminated the biasing introduced in entropy source circuit or sample circuit, improve
The statistical property of random number, while achieving the purpose that attack resistance；Output register circuit is responsible for exporting post processing circuitry true
Random number latch exporting and be used to other of chip exterior or chip module；Control circuit is responsible for generating random number
Device runs relevant control signal, the control including low-power consumption, Row control etc..
In the present embodiment, the entropy source circuit includes multiple random source circuits, respectively random based on metastable first
Source circuit, the based on even loop collapse time second random source circuit and fluttered the random source circuit of dynamic third based on ring, respectively with
Machine source circuit can provide data input signal to the end D of sample circuit.
Embodiment one
As shown in Figures 2 to 6, various entropy source circuits are explained in detail in the present embodiment: as shown in Fig. 2, described first
Random source circuit includes M S/R latch unit, is arranged in parallel and carries out XOR operation, operation between each S/R latch unit
As a result the output as entropy source circuit；M >=128.That is it is based on metastable random source circuit structure, using m
The output of S/R latch unit carries out output of the exclusive or result as entropy source, and Fig. 3 is the structure chart of each S/R latch unit, including
4 XOR gates, as S=R=1, latch is in neither 1, and non-zero nondeterministic statement；Specifically exporting which logical value is
It is determined by the instantaneous level of NAND gate and the absolute and relative value of internal noise, is found after tested, when sampling clock is with vibrating
Clock ratio is bigger, and randomness is stronger, and the number of S/R latch unit is not easy to select very few, otherwise can not be surveyed by randomness
Examination, the number for increasing S/R latch unit can effectively improve the randomness for generating random number, general m >=128 it can satisfy and want
It asks.
In the present embodiment, as shown in Fig. 4 to Fig. 5, the second random source circuit includes N number of successively end to end reverse phase
Device and two XOR gates, at a distance of N/2 phase inverter between two XOR gates；The N is even number.Two XOR gates are respectively first different
Or door and the second XOR gate, the second random source circuit there are two signal transmission path, be respectively the first signal transmission path
With second signal transmission path；First XOR gate only allows first signal transmission path to pass through, second exclusive or
Door only allows the second transmission path to pass through.
In the present embodiment, as shown in figure 5, the second random source circuit is made of even number of inverters and two XOR gates
Loop, referred to as " even number collapsed ring ".In the loop, there are two bars transmission paths, including the first transmission path and
Two transmission paths." ... " and " --- " is used to be indicated respectively in Fig. 5.The rising edge of the same inverter input and
The path that failing edge passes through in the loop is different.Starting point (port A and the port B) in the different paths of loop is defeated simultaneously
Enter an identical rising edge, after a period of time, the two are along that can meet, and loop is in stable state at this time.Transmit edge
It is known as collapse time from the time for being input to stable.The transmission delay of each path is the tired of each transistor parameter and noise
Add.The randomness of collapse time is determined by each phase inverter noise randomness.So collapse time can be used as true random number hair
The stochastic source of raw device.
In the present embodiment, as shown in figure 4, even number collapse loop has 2n grades of phase inverters, with the frequency dividing of sampling clock sclk
Clock sckxdiv (x=4,8 ...) input pulse is done, take the output of phase inverter Bn to do counting pulse, counter cnt1 exists
Sclkxdiv is started counting between high period, and counter cnt2 is started counting between low period in sclkxdiv.It will count
The 0th of value and the 1st is random in order to improve the purpose of doing output of the XOR operation output as the entropy source, carry out XOR operation
Several randomness.In order to accurately count collapse time as far as possible, if sckxdiv is four frequency dividings, sample circuit should be every one
Clock cycle collects 1 random number.If the pulse of even number collapsed ring input is 8 frequency dividings of sampling clock, adopt
Sample circuit should collect 1 random number every 3 clock cycle, and so on.
In the present embodiment, as shown in fig. 6, the random source circuit of institute's third includes several ring oscillators, each ring oscillator
It is made of the phase inverter of odd number, is provided with one and door in each ring oscillator；In the same ring oscillator with door
It successively joins end to end with each phase inverter, and in ring oscillator on the direction of signal transmission, in the defeated of most downstream phase inverter
Outlet is connected with described with the input terminal of door, described to be connected with the output end of door with the input terminal in most upstream phase inverter；It will
The output end of different length ring oscillator connects the same third XOR gate two-by-two, carries out exclusive or processing, later by each third
Exclusive or gate output terminal is connected to the 4th XOR gate.
In the present embodiment, each ring oscillator of entropy source circuit diagram based on circular type shaker shake is by several odd levels
Phase inverter constitute, the output of the last one phase inverter feeds back to the input of first phase inverter, vibrates in link due to presence
The influence of thermal noise, shot noise and low-frequency noise etc. causes the delay time of phase inverter to change, so that oscillation frequency
Rate changes, and can be used as the source of random number using the uncertainty of chattering frequency.
In the present embodiment, the timing jitter of an oscillation rings can not be needed as the entropy source of a high quality using multiple
Ring oscillator carries out exclusive or to improve randomness, and in addition the length of ring oscillator determines frequency of oscillation, eventually affects
The quality of random number after exclusive or.Simultaneously the length of different rings vibrations each other prime number when, the randomness of entropy source is better.That is because when two
The length of a ring oscillator chain is identical, and frequency of oscillation is just close, and jump area, which exists, largely to be overlapped, when two oscillators are sent out simultaneously
When raw jump, the entropy in timing jitter is just wasted, such overlapping in order to reduce as far as possible, it should to select two differences
The oscillator of length carries out exclusive or, it is contemplated that when the length prime number each other of two oscillators, then their frequency of oscillation is also
Prime number, within the two maximum common multiple one number time, there is no overlapping phenomenons in jump area, thus less to the greatest extent " entropy "
Waste.It joined in ring oscillator simultaneously and door close the clock when the circuit does not need work, meet low function
Consume the demand of design.Fig. 6 middle ring vibration length uses: 3,5,7,11,13,17,19,23,29,31,37,41,43,47,53,59.
Embodiment two
As shown in Figure 7 to 10, the random number sequence that the linear feedback shift register is output it is sent into detection electricity
Road, for the random number sequence with (8m) bit for a unit, m is the bit wide of random number sequence；The detection circuit is to random number
Sequence is detected.
In the present embodiment, the generator further includes randomly selecting device circuit, described to randomly select device circuit and the inspection
Slowdown monitoring circuit is connected, for extracting the random number sequence for being sent into detection circuit, to obtain the random number of mbit.
In the present embodiment, as shown in fig. 7, being constituted for 6 tap, 16 linear feedback shift registers (LFSR) and XOR gate
Circuit, feedback relationship is, the 1st-> Reg [0] of Reg [15] ^ input；Reg[5]^Reg[15]—>Reg[5]；Reg
[12]^Reg[15]—>Reg[12].Extract 1,4,5,7,8,9 totally 6 bit value carry out logical operation as map after
The value of the random number of 1bit.First using true random number as the seed filling of LSFR into 16 LSFR, at this point, LSFR is exported
Random number sequence be it is invalid, after being stuffed entirely with when 16 of LSFR, the random number sequence of LFSR output is considered as effectively.
In the present embodiment, as shown in figure 8, to randomly select the algorithm flow chart of device circuit；It is not random by detection circuit
Number, is given up to fall automatically；It is then admitted to by the random number of (8m) bit of detection circuit and randomly selects the progress of device circuit further
Processing.Randomly selecting device circuit is designed for attack protection, is randomly selected, is obtained to the random number of (8m) bit
The random number of mbit.Present invention Toeplitz matrix construction one kind randomly selects device circuit, can demonstrate,prove by mathematical relationship
It is bright, variation physical environment and its deposit in the case of an attack, still be able to extract well to a certain extent entropy source with
Machine and the unpredictability that can guarantee output.A in Fig. 8 is the 256bit data of input, and B is the 32bit number of output
According to PI is the constant value of 288bit.
In the present embodiment, randomly selecting device circuit and being not one for the design of real random number generator must cannot be lacked
The module of mistake, although the addition of the circuit reaches some intrusions and the non-intruding resisted including the channel of side to a certain extent
The purpose of formula attack, but extracted from the random number of (8m) bitt and obtain mbit as last random number sequence output significantly
The efficiency for generating random number is reduced, the area and power consumption of entire circuit increase with it, so practice occasion should be combined
Selection is using the circuit or gives up the circuit.
Embodiment three
As shown in Figure 9 and Figure 10, the schematic diagram and control flow chart of real random number generator in the present invention are given；This hair
The soft IP that bright middle real random number generator acts not only as intelligent card chip is called for system, is run with meeting system
To the demand of random number in journey, and can be in other chip developments or FPGA exploitation as true random number design
Scheme reference, Figure 10 are the workflow that system calls real random number generator.
In the present embodiment, after control circuit opens clock gating signal and selection stochastic source, start true random number module,
After the module generates the reset of several clock cycle, random source circuit is started to work, and exports random number；The design of the module
Compare flexibly, needs the scene flexible design according to application.
By using above-mentioned technical proposal disclosed by the invention, following beneficial effect has been obtained:
The present invention provides a kind of totally digital circuit real random number generator, the real random number generator has circuit knot
The characteristics of structure is simple, be easily achieved, quality of random numbers is higher, be evenly distributed, be unpredictable, low-power consumption, attack resistance, has very strong
Engineering reference and applying value；Real random number generator acts not only as a soft IP of intelligent card chip for system tune
With, to meet in system operation the needs of to random number, and can be in other chip developments or FPGA exploitation
The middle scheme reference as true random number design.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
Depending on protection scope of the present invention.
Claims (10)
1. a kind of totally digital circuit real random number generator, the generator includes entropy source circuit, sample circuit and output deposit
Device circuit, the sample circuit are connected with the entropy source circuit；It is characterized by: the generator further includes post processing circuitry,
The post processing circuitry is arranged between the sample circuit and the output register circuit and is respectively connected with the two, institute
Stating post processing circuitry includes the linear feedback shift register being connected with the sample circuit and the linear feedback shift register
The connected detection circuit of device and be connected with the detection circuit and randomly select circuit, the output register circuit with it is described with
Machine extraction circuit is connected, to randomly select the output of circuit described in latch.
2. totally digital circuit real random number generator according to claim 1, it is characterised in that: the control circuit and institute
State sample circuit, the linear feedback shift register, the detection circuit, it is described randomly select circuit and it is described output post
Latch circuit is respectively connected with.
3. totally digital circuit real random number generator according to claim 2, it is characterised in that: the entropy source circuit and institute
It states sample circuit to be connected, the sample circuit uses low-frequency sampling clock as the clock signal at the rising edge triggering end sample circuit D；
The output signal of the entropy source circuit is as sample circuit D end data input signal, and in the rising edge pair of sample clock pulse
It is sampled, and obtains a true random number bit stream with the end Q in sample circuit.
4. totally digital circuit real random number generator according to claim 1, it is characterised in that: the entropy source circuit includes
Multiple random source circuits, respectively at random based on the metastable first random source circuit, second based on even loop collapse time
It source circuit and is fluttered the random source circuit of dynamic third based on ring, each random source circuit can provide data to the end D of sample circuit
Input signal.
5. totally digital circuit real random number generator according to claim 4, it is characterised in that: the first stochastic source electricity
Road includes M S/R latch unit, is arranged in parallel and carries out XOR operation, operation result conduct between each S/R latch unit
The output of entropy source circuit；M >=128.
6. totally digital circuit real random number generator according to claim 4, it is characterised in that: the second stochastic source electricity
Road includes N number of successively end to end phase inverter and two XOR gates, at a distance of N/2 phase inverter between two XOR gates；The N is
Even number.
7. totally digital circuit real random number generator according to claim 6, it is characterised in that: two XOR gates are respectively
First XOR gate and the second XOR gate, there are two signal transmission paths, respectively the first signal to pass for the second random source circuit
Defeated path and second signal transmission path；First XOR gate only allows first signal transmission path to pass through, and described
Two XOR gates only allow the second transmission path to pass through.
8. totally digital circuit real random number generator according to claim 4, it is characterised in that: the random source circuit of institute's third
Including several ring oscillators, each ring oscillator is made of the phase inverter of odd number, be provided in each ring oscillator one with
Door；Successively joining end to end in the same ring oscillator with door and each phase inverter, and signal passes in ring oscillator
Output end on defeated direction, in most downstream phase inverter is connected with described with the input terminal of door, the output end with door with
Input terminal in most upstream phase inverter is connected；It is different that the output end of different length ring oscillator is connected into the same third two-by-two
Or door, progress exclusive or processing, each third exclusive or gate output terminal is connected to the 4th XOR gate later.
9. totally digital circuit real random number generator according to claim 1, it is characterised in that: the linear feedback shift
The random number sequence that register is output it is sent into detection circuit, and with (8m) bit for a unit, m is the random number sequence
The bit wide of random number sequence.
10. totally digital circuit real random number generator according to claim 9, it is characterised in that: the generator also wraps
It includes and randomly selects device circuit, the device circuit of randomly selecting is connected with the detection circuit, is sent into detection circuit for extracting
Random number sequence, to obtain the random number of mbit.
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| CN112130810A (en) * | 2020-09-27 | 2020-12-25 | 山西大学 | Safe high-speed random number generator and structure optimization method thereof |
| CN113377337A (en) * | 2021-07-07 | 2021-09-10 | 山东方寸微电子科技有限公司 | True random number generator and chip |
| CN114584305A (en) * | 2022-04-28 | 2022-06-03 | 苏州云途半导体有限公司 | Random number generator, electronic circuit and system-on-chip |
| TWI811642B (en) * | 2021-03-08 | 2023-08-11 | 新唐科技股份有限公司 | Random-number generator circuit and random-number generation method |
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| CN112130810A (en) * | 2020-09-27 | 2020-12-25 | 山西大学 | Safe high-speed random number generator and structure optimization method thereof |
| TWI811642B (en) * | 2021-03-08 | 2023-08-11 | 新唐科技股份有限公司 | Random-number generator circuit and random-number generation method |
| CN113377337A (en) * | 2021-07-07 | 2021-09-10 | 山东方寸微电子科技有限公司 | True random number generator and chip |
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| CN114584305B (en) * | 2022-04-28 | 2022-07-26 | 苏州云途半导体有限公司 | Random number generator, electronic circuit and system-on-chip |
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| CN110071803B (en) | 2022-04-01 |
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