CN208723865U

CN208723865U - A kind of duty-ratio calibrating circuit

Info

Publication number: CN208723865U
Application number: CN201821502409.3U
Authority: CN
Inventors: 何杰; 杨诗洋; 王颀; 宋大植; 詹姆士·金
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-09-13
Filing date: 2018-09-13
Publication date: 2019-04-09
Anticipated expiration: 2028-09-13

Abstract

The utility model embodiment discloses a kind of duty-ratio calibrating circuit, comprising: delay line, failing edge detection module and phase-interpolation module；Delay line is in series with multiple sub- delay lines, and every sub- delay line includes one or more delay units connected and delay time is equal, and the delay time of delay unit is less than the delay time of delay unit in latter sub- delay line in previous sub- delay line；Failing edge detection module for obtaining multiple time delayed signals of signal to be calibrated from delay line according to the frequency of signal to be calibrated, and detects according to signal to be calibrated and each time delayed signal the failing edge of signal to be calibrated, obtains failing edge state detection signal；Phase-interpolation module, for the signal according to signal to be calibrated and the failing edge state detection signal, after being calibrated.The utility model can satisfy the power consumption and area occupied for reducing circuit in the case where meeting the duty ratio calibration accuracy of different frequency signals.

Description

A kind of duty-ratio calibrating circuit

Technical field

This application involves signal processing technology field more particularly to a kind of duty-ratio calibrating circuits.

Background technique

In high-speed digital system, the duty cycle dither of high-speed clock signal will lead to system job insecurity, need to add Enter duty-ratio calibrating circuit (duty cycle correction, DCC) to solve the problems, such as the duty cycle dither of high-frequency clock, incites somebody to action The duty ratio correction of input clock guarantees the normal work of system to 50%.

A kind of currently used duty-ratio calibrating circuit is the duty-ratio calibrating circuit of digital open loop structure, including delay Line, Logic control module and phase-interpolation module (phase interpolation, PI).Wherein delay line is single by multiple delays First (delay cell) is composed in series, for by the phase delay unit time of input signal.Logic control module, using to school Calibration signal and the signal after the delay of each delay unit, determine the failing edge of signal to be calibrated, obtain failing edge state-detection Signal.Phase-interpolation module further according to failing edge state detection signal and signal to be calibrated realize the duty ratio of signal to be calibrated into Row calibration.

Since the calibration accuracy of duty ratio is related to the delay time of each delay unit, for high-frequency signal, calibration High-precision need the delay time of delay unit short；And for low frequency signal, if the delay time of delay unit is short, again A fairly large number of delay unit is needed to realize the high-precision of duty ratio calibration, and the area that duty-ratio calibrating circuit occupies is big.

Utility model content

In order to solve prior art problem, the embodiment of the present application provides a kind of duty-ratio calibrating circuit, can satisfy In the case where the duty ratio calibration accuracy for meeting different frequency signals, reduce the power consumption and area occupied of circuit.

A kind of duty-ratio calibrating circuit provided by the embodiments of the present application, comprising: delay line, failing edge detection module and phase Interpolating module；

The delay line is in series with multiple sub- delay lines, and each sub- delay line includes one or more series connection and postpones Time equal delay unit, the delay time of delay unit, which is less than in latter sub- delay line, in previous sub- delay line is delayed The total delay time of the delay time of unit, every sub- delay line are determined according to the working frequency of signal to be calibrated；The delay Line is for being delayed to the signal to be calibrated；

The failing edge detection module, it is described for being obtained from the delay line according to the frequency of the signal to be calibrated Multiple time delayed signals of signal to be calibrated, and it is described to be calibrated according to the signal to be calibrated and each time delayed signal detection The failing edge of signal obtains failing edge state detection signal；

The phase-interpolation module, for obtaining according to the signal to be calibrated and the failing edge state detection signal Signal after calibration.

Optionally, the failing edge detection module includes multiple and the one-to-one logic control submodule of the delay unit Block；

The logic control submodule switches to idle state or working condition for controlling signal based on the received, The time delayed signal and the signal to be calibrated of corresponding delay unit output are received when in running order, and are prolonged according to what is received When the signal and signal to be calibrated, be made whether the detection for failing edge state occur；

Wherein, the control signal is determined according to the frequency of the signal to be calibrated；The failing edge state is specially to work as When the time delayed signal received is in low level, the signal to be calibrated switches to low level from high level；

First logic control submodule is also used to connect when detecting that the failing edge state occurs by described The time delayed signal received is exported as the failing edge state detection signal to the phase-interpolation module；

K-th of logic control submodule is also used to detect that the failing edge state occurs and front is in work When the logic control submodule for making state is not detected the failing edge state and occurs, the time delayed signal received is made It exports for the failing edge state detection signal to the phase-interpolation module；K is the integer greater than 1.

Optionally,

The logic control submodule, specifically for being in idle condition or being not detected the failing edge state appearance When output first state Seize ACK message to the latter described in logic control submodule；Detecting the failing edge state appearance When, export logic control submodule described in the Seize ACK message to the latter of the second state；It is also used in running order and connect When receiving the Seize ACK message of first state, according to the time delayed signal and the signal to be calibrated received, it is made whether institute occur State the detection of failing edge state；It is also used to when receiving the Seize ACK message of the second state, continues to the latter logic control Module sends the Seize ACK message of the second state.

Optionally, the logic control submodule, comprising: d type flip flop, logic processing circuit, transmission circuit and control electricity Road；

The end D of the d type flip flop connects the signal to be calibrated, and the input end of clock connection correspondence of the d type flip flop is prolonged The time delayed signal of Shi Danyuan output, the end Q of the d type flip flop connects the first input end of the logic processing circuit；

Second input terminal of the logic processing circuit connects the end Q of d type flip flop in previous logic control submodule, institute The third input terminal for stating logic processing circuit connects the first output end of logic processing circuit in previous logic control submodule, First output end of the logic processing circuit connects the third input of logic processing circuit in the latter logic control submodule End, the second output terminal of the logic processing circuit connect the control terminal of the transmission circuit；

The logic processing circuit, for being enabled when the end the Q output first of d type flip flop in previous logic control submodule The first output end of logic processing circuit exports the occupancy in the first state of signal, the previous logic control submodule The end Q when exporting the second state of the first enable signal of the first state of signal, the d type flip flop, the of the second state of output Two enable signals and export the Seize ACK message of the second state to the latter logic control to the control terminal of the transmission circuit The third input terminal of logic processing circuit in submodule；It is also used to when logical process electricity in the previous logic control submodule When the second state of the first output end output Seize ACK message on road, alternatively, when the enabled letter of the end Q of d type flip flop output first Number first state when, export the second enable signal of first state to the control terminal of the transmission circuit, and export the first shape The third input terminal of the Seize ACK message of state logic processing circuit into the latter logic control submodule；

The transmission circuit, for when receiving the second enable signal of the second state, corresponding delay unit to be exported Time delayed signal export to the phase-interpolation module；

The control circuit is used for according to the control signal, and the first state or the second state for exporting Seize ACK message are to control Make the logic processing circuit is in running order or idle state.

Optionally, the logic processing circuit, specifically includes: the first phase inverter, the second phase inverter, third phase inverter, One NAND gate, the second NAND gate, third NAND gate and the 4th NAND gate；

The input terminal of first phase inverter connects the end Q of d type flip flop in the previous logic control submodule, institute The output end for stating the first phase inverter connects the first input end of first NAND gate；

Second input terminal of first NAND gate connects the output end of second phase inverter, first NAND gate Output end connects the first input end of second NAND gate；

The input terminal of second phase inverter connects of logic processing circuit in the previous logic control submodule One output end；

Second input terminal of second NAND gate connects the output end of the third phase inverter, second NAND gate Output end connects the control terminal of the transmission circuit；

The input terminal of the third phase inverter connects the end Q of the d type flip flop；

The first input end of the third NAND gate connects the input terminal of the third phase inverter, the third NAND gate Second input terminal connects the end Q of d type flip flop in the previous logic control submodule, and the output end of the third NAND gate connects Connect the first input end of the 4th NAND gate；

Second input terminal of the 4th NAND gate connects the output end of second phase inverter, the 4th NAND gate Output end connects the third input terminal of logic processing circuit in the latter logic control submodule.

Optionally, further includes: frequency detection module；

The frequency detection module, for detecting the frequency of the signal to be calibrated；It is also used to and according to being previously obtained Allocation list determines frequency range belonging to the frequency of the signal to be calibrated, and exports corresponding to the frequency range determined Control signal is to each logic control submodule, the shape so that the logic control submodule is in idle condition or works State；

Wherein, the allocation list includes the one-to-one relationship of frequency range and control signal.

Optionally, the phase-interpolation module, comprising: the 4th phase inverter and phase interpolator；

The failing edge state detection signal inputs the phase interpolator through the 4th phase inverter；

The phase interpolator is obtained for the output signal according to the signal to be calibrated and the 4th phase inverter Signal after the calibration；

The frequency detection module is also used to the frequency according to the signal to be calibrated, sends configuration signal to the phase Position interpolation device, the interpolation range of the phase interpolator is arranged.

Optionally, the phase interpolator, including multiple groups phase inverter set, phase inverter set described in every group and the configuration Table includes that frequency range corresponds；Phase inverter set described in every group includes two parallel-connected inverters in parallel and with described two The series connection phase inverter of the inverter series of a parallel connection；

The input terminal of two parallel-connected inverters is separately connected the signal to be calibrated and institute in phase inverter set described in every group The output end of the 4th phase inverter is stated, the output end of described two parallel-connected inverters connects the input terminal of the series connection phase inverter, institute Signal after stating the output end output calibration of series connection phase inverter；

The frequency detection module, specifically for the frequency according to the signal to be calibrated, control any one group described in it is anti- Phase device set is in running order.

Optionally,

Each sub- delay line corresponds to a frequency range in the allocation list, and the previous sub- delay line pair The frequency range answered is greater than the corresponding frequency range of sub- delay line described in the latter.

Optionally,

The total delay time of first sub- delay line to m-th of sub- delay line is greater than or equal to m-th of son and prolongs The maximum time of low-limit frequency signal positive half period within the scope of slow line respective frequencies, m are the positive integer greater than 1.

Compared with prior art, the application has at least the following advantages:

In the embodiment of the present application, duty-ratio calibrating circuit includes delay line, failing edge detection module and phase-interpolation mould Block, wherein delay line is delayed for treating calibration signal, is in series with multiple sub- delay lines, every sub- delay line packet thereon One or more concatenated delay units are included, the delay time of delay unit postpones less than latter height in previous sub- delay line The delay time of delay unit in line.The total delay time of every sub- delay line is determining according to the working frequency of signal to be calibrated, When the frequency of signal to be calibrated is higher, delay time lesser delay unit on previous or multiple sub- delay lines can use The obtained time delayed signal that is delayed detects the failing edge of signal to be calibrated, guarantees the calibration accuracy of high-frequency signal；And work as letter to be calibrated Number frequency it is lower when, multiple prolonged using what unit in the latter or multiple sub- delay lines was delayed that larger delay unit is delayed The failing edge of slow signal detection signal to be calibrated, it is also ensured that the calibration accuracy of low frequency signal.Also, subsequent sub- delay The delay time of delay unit is long on line, reduces on delay line the quantity of required delay cell while also consequently reducing pair The control logic circuit area answered.Duty-ratio calibrating circuit provided by the embodiments of the present application can not reduced by phase-interpolation Under the premise of calibration accuracy of the module according to signal after the calibration of signal to be calibrated and the acquisition of failing edge state detection signal, pass through The division in region and the configuration of logic control circuit are carried out to delay line, when increasing the delay of delay unit used in low frequency signal Between, it can be substantially reduced the power consumption and area of circuit, improve the area efficiency and energy efficiency of circuit.

Detailed description of the invention

In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this The some embodiments recorded in application, for those of ordinary skill in the art, without creative efforts, It can also be obtained according to these attached drawings other attached drawings.

Fig. 1 is a kind of existing circuit topology of duty-ratio calibrating circuit；

Fig. 2 is the signal timing diagram after delay line shown in FIG. 1 delay；

Fig. 3 is a kind of structural schematic diagram of duty-ratio calibrating circuit provided by the embodiments of the present application；

Fig. 4 is a kind of schematic diagram for delay line that the application specific embodiment provides；

Fig. 5 a- Fig. 5 c is the schematic diagram in the application specific embodiment for the time delayed signal of failing edge detection；

Fig. 6 is the working principle timing diagram of phase interpolator in the application specific embodiment；

Fig. 7 is the structural schematic diagram of another duty-ratio calibrating circuit provided by the embodiments of the present application；

Fig. 8 is the structural schematic diagram for the logic control submodule that the application specific embodiment provides；

Fig. 9 is the structural schematic diagram for the logic processing circuit that the application specific embodiment provides；

Figure 10 is the structural schematic diagram for the phase-interpolation module that the application specific embodiment provides；

Figure 11 is the structural schematic diagram for the phase interpolator that the application specific embodiment provides.

Specific embodiment

In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only this Apply for a part of the embodiment, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art exist Every other embodiment obtained under the premise of creative work is not made, shall fall in the protection scope of this application.

It should be appreciated that in this application, " at least one (item) " refers to one or more, and " multiple " refer to two or two More than a."and/or" indicates may exist three kinds of relationships, for example, " A and/or B " for describing the incidence relation of affiliated partner It can indicate: only exist A, only exist B and exist simultaneously tri- kinds of situations of A and B, wherein A, B can be odd number or plural number. Character "/" typicallys represent the relationship that forward-backward correlation object is a kind of "or".At least one of " following (a) " or its similar expression is Refer to any combination in these, any combination including individual event (a) or complex item (a).For example, at least one in a, b or c Item (a), can indicate: a, b, c, " a and b ", " a and c ", " b and c ", or " a and b and c ", and wherein a, b, c can be individually, It is also possible to multiple.

In order to make it easy to understand, introducing the duty-ratio calibrating circuit and its work of a kind of existing digital open loop structure first below Make principle.

Referring to Fig. 1, which is a kind of circuit topology of existing duty-ratio calibrating circuit.

The duty-ratio calibrating circuit of digital open loop structure is mainly made of delay line, logic control circuit and interpolation circuit. Wherein, delay line is in series by multiple delay units, and each delay unit is prolonged the signal timer time τ of input When after signal.The output of each delay unit is also connected with corresponding logic control circuit, for detecting under signal to be calibrated Edge drops.

As an example, after by signal CLK_IN to be calibrated for first delay unit of input delay line, Ge Geyan Slow unit is exported to the signal timing diagram of logic control circuit as shown in Fig. 2, wherein the signal of a-th of delay unit output is CLK[a].Logic control circuit especially by the signal CLK [a] judged after the delay as low level when, whether signal to be calibrated Low level is switched to by high level, the appearance of detection failing edge state is determined whether, to treat the failing edge of calibration signal It is detected.

With continued reference to Fig. 2, it is assumed that the detection of logic control circuit corresponding to (n+1)th delay cell failing edge state goes out It is existing, then CLK [n+1] is exported as failing edge state detection signal to interpolation circuit.Failing edge state detection signal illustrates At the time of there is failing edge in signal to be calibrated.Interpolation circuit is to failing edge state detection signal/CLK [n+1] of reverse phase and to school Calibration signal CLK_IN carries out phase-interpolation calculating, the signal after being calibrated.Assuming that the negative half-cycle of signal CLK_IN to be calibrated Length is A, clock cycle T, between the failing edge state detection signal CLK [n+1] and signal CLK_IN to be calibrated detected Phase difference be B=N* τ, i.e., difference between the failing edge and CLK_IN failing edge of negated/CLK [n+1] is (A+B- T).The negative half-cycle length of/CLK [n+1] is (T-A), between the next rising edge and/CLK [n+1] rising edge of CLK_IN For (A-B), the duty ratio of the signal after being calibrated after interpolation is 0.5* (A+B-T)+(T-A)+0.5 (A-B)=0.5T, real The calibration to CLK_IN duty ratio is showed.

In order to meet different frequency signal failing edge state-detection to be calibrated demand, generally require the total of delay line Delay time is set greater than the maximum time of signal positive half period to be calibrated.Due to the precision and failing edge shape of duty ratio calibration The precision of state detection is related, i.e., related to the unit time τ that delay unit on delay line postpones.If unit time τ is arranged The smaller calibration accuracy to guarantee high-frequency signal then needs then in order to meet the lower signal failing edge state-detection demand of frequency A fairly large number of delay unit and corresponding logic control circuit are set, power consumption height and the occupancy face of duty-ratio calibrating circuit are caused Product is big.

To solve the above-mentioned problems, under the premise of not sacrificing duty ratio calibration accuracy, reduce the power consumption and area of circuit, The embodiment of the present application provides a kind of duty-ratio calibrating circuit, by the division for carrying out sub- delay line to delay unit on delay line With the configuration of logic control circuit, as the extension of delay line increases the delay time of delay cell in every sub- delay line, from And it can be substantially reduced circuit power consumption and area, improve the area efficiency and energy efficiency of circuit.

It should be noted that duty-ratio calibrating circuit provided by the embodiments of the present application, can be applied not only to clock signal The calibration of duty ratio can be applicable to the duty ratio calibration to other signals, and the embodiment of the present application is without limiting.At one In specific example, duty-ratio calibrating circuit provided by the embodiments of the present application is suitable for the data-path circuit NV- of nand flash memory The calibration of RE differential signal under DDR2 and NVDDR3 mode.When data are read, RE differential signal is equivalent to differential clock signal, Externally input RE signal will affect effective window of data reading since the influence duty ratio inside nand flash memory can shake The mouth time, with the increase of working frequency, influencing can be increasingly severe, needs clock duty cycle calibration circuit to calibrate RE letter Number.

Based on above-mentioned thought, in order to make the above objects, features, and advantages of the present application more apparent, below with reference to Attached drawing is described in detail the specific embodiment of the application.

Referring to Fig. 3, which is a kind of structural schematic diagram of duty-ratio calibrating circuit provided by the embodiments of the present application.

Duty-ratio calibrating circuit provided by the embodiments of the present application, comprising: delay line 10, failing edge detection module 20 and phase Interpolating module 30；

Delay line 10 is delayed for treating calibration signal CLK_IN, wherein being in series with multiple sub- delay lines；Every height Delay line includes one or more delay units connected and delay time is equal, delay unit in previous sub- delay line Delay time is less than the delay time of delay unit in latter sub- delay line, the total delay time of every sub- delay line according to The working frequency of calibration signal determines.

What needs to be explained here is that between the time delayed signal and signal CLK_IN to be calibrated of previous sub- delay line output Time delay is less than the time delay between latter sub- delay line and signal CLK_IN to be calibrated.That is, previous sub- delay line and delay line It is spaced between less than latter 10 input terminal of sub- delay line and delay line of the quantity for the delay unit being spaced between 10 input terminals The quantity of delay unit.

As an example, as shown in figure 4, delay line 10 includes concatenated three sub- delay lines one by one: the first son delay Line 11, the second sub- delay line 12 and the sub- delay line 13 of third.Previous sub- delay line can be the first sub- delay line 11, the latter Sub- delay line can be the second sub- delay line 12；Alternatively, previous sub- delay line can be the second sub- delay line 12, latter height Delay line can be the sub- delay line 13 of third.

In the embodiment of the present application, signal CLK_IN to be calibrated is passed through to the output end input delay line 10 of delay line 10 Afterwards, due to the extension with delay line 10, the delay time of delay unit is gradually increased in every sub- delay line on delay line 10, And the frequency dependence of the total delay time of sub- delay line and signal CLK_IN to be calibrated, then it is calibrated in the duty ratio to high-frequency signal When, the detection that multiple time delayed signals carry out failing edge can be obtained by delay unit in the sub- delay line of one or more of front, The unit delay of delay cell is small, it is ensured that the high-precision of high-frequency signal duty ratio calibration.And the failing edge inspection of low frequency signal Of less demanding to the delay time of delay unit when survey, delay time biggish delay unit also can guarantee the essence of duty ratio calibration Degree when calibrating to the duty ratio of low frequency signal, expands in the subsequent sub- delay line of one or more in the embodiment of the present application The big delay cell of unit delay is delayed, and can not only guarantee the precision calibrated to low frequency signal duty ratio, also reduce The quantity of required delay unit reduces the area occupied of duty-ratio calibrating circuit.

With continued reference to Fig. 4, delay line 10 includes concatenated three sub- delay lines one by one: first sub- the 11, second son of delay line Delay line 12 and the sub- delay line 13 of third.First sub- delay line 11 includes 4 series connection and delay time is the delay cell of τ DC1, the second sub- delay line 12 includes 2 series connection and delay time is the delay cell DC2 of 2 τ, and the sub- delay line 13 of third includes The delay cell DC3 that one delay time is 3 τ.When due to the detection of high-frequency signal failing edge, prolong needed for the precision to guarantee detection The unit delay of slow signal is short, total delay time is short, delay time small delay unit DC in former sub- delay lines, and such as first Four delay times are that the delay cell DC1 of τ can meet the need of high-frequency signal failing edge state-detection in sub- delay line 11 It asks；And when the detection of low frequency signal failing edge, the unit delay of postpones signal needed for the precision to guarantee detection can longer, always prolong The slow time is long, and the delay time of delay unit DC is big (in the such as second sub- delay line 12 when two delays in rear several sub- delay lines Between for delay time in the delay cell DC2 of 2 τ, the sub- delay line 13 of third be 4 τ delay cell DC3), that is, increase with to school The delay time of each delay cell of maximum time of the delay beyond high-frequency signal positive half period between calibration signal CLK_IN, Reduce the quantity of delay cell DC needed for low frequency signal, and 10 length of delay line and counterlogic circuit number can reduced On the basis of amount, meets the needs of low frequency signal failing edge state-detection, to realize on the basis of guaranteeing calibration accuracy Reduction to the area occupied of duty cycle circuit power consumption.

In practical application, each delay unit DC in the quantity for the sub- delay line that delay line 10 includes and sub- delay line Delay time, can the frequency of calibration signal according to actual needs specifically set, the embodiment of the present application without limiting, Here it also will not enumerate.

Failing edge detection module 20, it is to be calibrated for being obtained from delay line 10 according to the frequency of signal CLK_IN to be calibrated Multiple time delayed signal CLK [M] of signal CLK_IN, and examined according to signal CLK_IN to be calibrated and each time delayed signal CLK [M] The failing edge for surveying signal CLK_IN to be calibrated obtains failing edge state detection signal CLK_DOWN.

In the embodiment of the present application, signal CLK_IN to be calibrated is input to delay line 10 and is delayed, and failing edge detects mould Block 20 can using the frequency of signal CLK_IN to be calibrated as foundation, selectively on delay line 10 multiple delay units output The time delayed signal CLK [M] that end obtains after delay unit delay is compared to realize and treat with signal CLK_IN to be calibrated The detection of the failing edge of calibration signal CLK_IN.

For example, when the frequency of signal CLK_IN to be calibrated is higher, can according to the frequency of signal CLK_IN to be calibrated from The output end of delay time lesser delay unit obtains multiple delay letters on the previous or multiple sub- delay line of delay line 10 Number CLK [M] carries out the detection of failing edge, guarantees the precision to the detection of high-frequency signal failing edge and duty ratio calibration；And when to school When the frequency of calibration signal CLK_IN is lower, the delay time lesser delay unit on obtaining previous or multiple sub- delay lines Output end obtains the possible insufficient detection for completing failing edge of multiple time delayed signal CLK [M], so as to according to signal to be calibrated The frequency of CLK_IN continue from the latter of delay line 10 or multiple sub- delay lines delay time biggish delay unit it is defeated Outlet obtains the detection that one or more postpones signal CLK [M] carries out failing edge, guarantees that low frequency signal failing edge is detected and accounted for Precision of the sky than calibration.In general, between the multiple time delayed signal CLK [M] got and signal CLK_IN to be calibrated most Big delay should be greater than or equal to signal CLK_IN positive half period to be calibrated maximum time.

Continue by taking the delay line shown in Fig. 4 as an example, when signal CLK_IN to be calibrated is low frequency signal, failing edge detects mould It is respectively τ, 2 τ, 3 τ and 4 τ that block 20 can obtain delay between 4 and signal CLK_IN to be calibrated from the first sub- delay line 11 Time delayed signal realize the detection for treating calibration signal CLK_IN failing edge, as shown in Figure 5 a；As signal CLK_IN to be calibrated When for intermediate-freuqncy signal, failing edge detection module 20 obtained from the first sub- delay line 11 and the second sub- delay line 12 4 with to school Delay is respectively that the time delayed signal of 2 τ, 4 τ, 6 τ and 8 τ are treated under calibration signal CLK_IN to realize between calibration signal CLK_IN The detection on edge is dropped, as shown in Figure 5 b；When signal CLK_IN to be calibrated is low frequency signal, failing edge detection module 20 is sub from first 3 delays point between signal CLK_IN to be calibrated are obtained in delay line 11, the second sub- delay line 12 and the sub- delay line 13 of third Not Wei the time delayed signal of 4 τ, 8 τ and 11 τ realize the detection for treating calibration signal CLK_IN failing edge, as shown in Figure 5 c.Below It will be explained in how failing edge detection module 20 specifically obtains from delay line 10 according to the frequency of signal CLK_IN to be calibrated Multiple time delayed signal CLK [M] do not repeat first here.

Phase-interpolation module 30 is used for according to signal CLK_IN to be calibrated and failing edge state detection signal CLK_DOWN, Signal CLK_OUT after being calibrated.

As an example, phase-interpolation module can specifically include: phase inverter and phase interpolator PI；

The inverted device of failing edge state detection signal CLK_DOWN inputs phase after obtaining signal/CLK_DOWN after reverse phase Position interpolation device；Phase interpolator PI is according to signal/CLK_DOWN after signal CLK_IN to be calibrated and reverse phase, after being calibrated Signal CLK_OUT.

In practical application, the signal CLK_OUT after any one phase interpolator PI is calibrated, this Shen can use Please embodiment without limit.

In one example, referring to Fig. 6, which is the working principle timing diagram of phase interpolator in the embodiment of the present application. Phase interpolator PI obtains interpolation according to failing edge state detection signal/CLK_DOWN after signal CLK_IN to be calibrated and reverse phase Signal Spi, then using interpolated signal Spi rising edge midpoint as the starting point of the signal CLK_OUT failing edge after calibration, realization is treated The calibration of calibration signal CLK_IN duty ratio, the signal CLK_OUT after obtaining the calibration that duty ratio is 50%.In practical application, The difference that phase interpolator PI can use two switching tube driving capabilities of phase inverter or more obtains interpolated signal Spi.

Above content carries out whole explanation to the structure and principle of duty-ratio calibrating circuit provided by the embodiments of the present application, It is described in detail one by one below with reference to specific example.

Referring to Fig. 7, which is the structural schematic diagram of another duty-ratio calibrating circuit provided by the embodiments of the present application.

In some possible implementations of the embodiment of the present application, failing edge detection module 20 includes multiple and delay unit The one-to-one logic control submodule 21 of DC；

Logic control submodule 21 switches to idle state or working condition for control signal Ctrl based on the received, The time delayed signal and signal CLK_IN to be calibrated of corresponding delay unit output are received when in running order, and according to reception The time delayed signal and signal CLK_IN to be calibrated arrived, is made whether the detection for failing edge state occur；

First logic control submodule 21 [1] is also used to prolong when detecting that failing edge state occurs by what is received When signal export as failing edge state detection signal to phase-interpolation module 30；

K-th of logic control submodule 21 [k] is also used to detect that failing edge state occurs and front is in work shape When the logic control submodule of state is not detected failing edge state and occurs, using the time delayed signal received as failing edge state Detection signal is exported to phase-interpolation module 30；K is the integer greater than 1.

Wherein, control signal Ctrl is determined according to the frequency of signal CLK_IN to be calibrated；Failing edge state is specially to work as to connect When the time delayed signal received is in low level, signal CLK_IN to be calibrated switches to low level from high level.Such as it is shown in Fig. 2 Example in, when CLK [n+1] is in low level state, signal CLK_IN to be calibrated switches to low level from high level, that is, examines The appearance of failing edge state is arrived out.

It should be noted that first logic control submodule 21 [1] refers to and the company of series connection after 10 input terminal of delay line Logic control submodule corresponding to first delay unit connect, receive the output of first delay unit time delayed signal and to Calibration signal CLK_IN, to be made whether the detection of failing edge state occur.Similarly, k-th of logic control submodule 21 [k] refers to The kth delay unit for being with being connected in series after 10 input terminal of delay line corresponding to logic control submodule, receive this The time delayed signal and signal CLK_IN to be calibrated of k delay unit output, to be made whether the detection of failing edge state occur.The In running order logic control submodule refers in running order the before k logic control submodule 21 [k] K-p logic control submodule, p are the integer greater than 0 and less than k.

In the embodiment of the present application, it is defeated according to corresponding delay unit to refer specifically to logic control submodule 21 for working condition Time delayed signal and signal CLK_IN to be calibrated out is made whether the detection for failing edge state occur；Idle state then refers to patrolling Control submodule 21 is collected without whether the detection of failing edge turntable occur or not exporting the detection for failing edge state whether occur As a result to phase-interpolation module 30.By control signal control is determined according to the frequency of signal CLK_IN to be calibrated, without progress The logic control submodule 21 of failing edge detection switches to idle state, it is possible to reduce the whole function of failing edge detection module 20 Consumption.In a specific example, logic control submodule 21 switches to idle state specifically and can be closing, such as by logic control The power supply of system module 21 is turned or switched off；Be also possible to short circuit, no matter correspond to delay unit output time delayed signal and Which kind of state signal CLK_IN to be calibrated is in, which obtains the knot that the appearance of failing edge state is not detected Fruit.

In some possible implementations of the embodiment of the present application, logic control submodule 21 is specifically used in sky Not busy state is not detected when failing edge state occurs and exports the Seize ACK message of first state to the latter logic control submodule； When detecting that failing edge state occurs, the Seize ACK message of the second state is exported to the latter logic control submodule；It is also used to In in running order appearance and when receiving the Seize ACK message of first state, according to the time delayed signal and letter to be calibrated received Number, it is made whether the detection for failing edge state occur；It is also used to continue when receiving the Seize ACK message of the second state to latter A logic control submodule sends the Seize ACK message of the second state.It should be noted that the logic control submodule 21 is corresponding The delay unit of delay unit output end connection, as delay unit corresponding to the latter logic control submodule.

In the embodiment of the present application, first state represents " non-", the second status representative "Yes", can respectively by high level and Low level indicates.In practical application, the performance of the first state and the second state of Seize ACK message can be set as the case may be Form, for example, the first state (i.e. " non-") of Seize ACK message can be high level, the second state (i.e. "Yes") of Seize ACK message can To be low level, the application is to this without limiting.

Illustrate by taking Fig. 7 as an example, it is assumed that logic control submodule 21 [1] is in idle condition, and output first state accounts for With signal to logic control submodule 21 [2]；Logic control submodule 21 [2] is in running order, is made whether to decline Along state detection but failing edge state be not detected occur, continue to output the Seize ACK message of first state to logic control submodule 21[3]；Logic control submodule 21 [3] is in idle condition, and exports the Seize ACK message of first state to logic control submodule Block 21 [4], and so on, there is output first state until failing edge state is still not detected in logic control submodule 21 [k-2] Seize ACK message to logic control submodule 21 [k-1].Logic control submodule 21 [k-1] is in running order, is made whether There is the detection of failing edge state and detect that failing edge state occurs, the Seize ACK message for exporting the second state is sub to logic control Module 21 [k] is indicated to detect the appearance of failing edge state；Logic control submodule 21 [k] continues logic control rearwards Module exports the Seize ACK message of the second state, and avoiding the repetition of failing edge state from detecting causes duty-ratio calibrating circuit to malfunction.

In some possible implementations of the embodiment of the present application, with continued reference to Fig. 7, which can be with It include: frequency detection module 40；

Frequency detection module 40, for detecting the frequency of signal CLK_IN to be calibrated；It is also used to and according to being previously obtained Allocation list determines frequency range belonging to the frequency CLK_IN of signal to be calibrated, and exports corresponding to the frequency range determined Control signal Ctrl to each logic control submodule 21 shape so that logic control submodule 21 is in idle condition or works State；

Wherein, allocation list includes the one-to-one relationship of frequency range and control signal Ctrl.

In some possible designs, every sub- delay line corresponds to a frequency range in allocation list on delay line 10, And the corresponding frequency range of previous sub- delay line is greater than the corresponding frequency range of latter sub- delay line.In practical applications, It can be according to signal CLK_IN frequency to be calibrated, before its affiliated corresponding sub- delay line of frequency range and the sub- delay line The sub- delay lines of one or more obtain multiple time delayed signals of failing edge detection.Specifically obtain the defeated of which delay unit It can use control signal Crtl as the multiple time delayed signals for obtaining failing edge detection to select out.Optionally, in order to protect The accurate of failing edge detection is demonstrate,proved, in some possible implementations, first sub- delay line to m-th sub- delay line always prolongs The slow time is greater than or equal to the maximum time of low-limit frequency signal positive half period within the scope of m-th of sub- delay line respective frequencies, and m is Positive integer.

It in practical applications, can be each by what need to be calibrated previously according to the concrete application scene of duty-ratio calibrating circuit Signal is divided into multiple frequency ranges, and different control signals is arranged for each frequency range, to switch each logic control Submodule 21 is in idle condition or working condition, and the detection of failing edge is realized in the case where guaranteeing precision.For example, can be (100MHz, 200MHz), (200MHz, 300MHz) and (300MHz, 400MHz) three frequency ranges are set in allocation list, and Different control signal Ctrl is arranged for each frequency range to be in idle condition or work to switch each logical subunit 21 State.

It is understood that the quantity of control signal Ctrl can be set according to the number for the frequency range for including in allocation list It is fixed, such as when setting (100MHz, 200MHz), (200MHz, 300MHz) and (300MHz, 400MHz) three frequencies in allocation list When rate range, control signal may include the first signal Ctrl1 and second signal Ctrl2, so as to according to utilization control signal Different conditions indicate different frequency ranges, control each logic control submodule and are in idle condition or working condition.For example, When the first signal Ctrl1 and second signal Ctrl2 are low level (0), each logic control submodule is turned off；When When one signal Ctrl1 is low level, second signal Ctrl2 is high level, signal CLK_IN to be calibrated is low frequency, belongs to frequency model Enclose (100MHz, 200MHz)；When the first signal Ctrl1 is high level, second signal Ctrl2 is low level, signal to be calibrated CLK_IN is intermediate frequency, belongs to frequency range (200MHz, 300MHz)；When the first signal Ctrl1 and second signal Ctrl2 are When high level, signal CLK_IN to be calibrated is high frequency, belongs to frequency range (300MHz, 400MHz).The above is only exemplary theorys It is bright, it is not construed as the limitation to the application protection scope, can be set as the case may be in practical application, here no longer one by one It enumerates.

In the embodiment of the present application, subsequent to be in work when some logic control submodule detects failing edge state The logic control submodule of state no longer carries out the detection of failing edge state, and avoiding the repetition of failing edge state from detecting leads to duty Than calibration circuit error.It is multiple part logic control submodule to be switched to by idle shape according to the frequency of signal to be calibrated State, to save the power consumption of logical process.

The specific structure of logic control submodule in duty-ratio calibrating circuit is exemplified below.

Referring to Fig. 8, which is the structural schematic diagram for the logic control submodule that the application specific embodiment provides.

In the embodiment of the present application, logic control submodule 21 [i] may include: d type flip flop 801 [i], logical process Circuit 802 [i], transmission circuit 803 [i] and control circuit 804 [i]；I is the integer greater than 1.

The end D of d type flip flop 801 [i] connects CLK_IN to be calibrated, and the input end of clock of d type flip flop 801 [i], which connects, to be corresponded to The time delayed signal CLK [i] of delay unit DC [i] output, the first of the end Q connection logic processing circuit 802 [i] of d type flip flop 801 Input terminal in1；

D in the second previous logic control submodule 21 [i-1] of input terminal in2 connection of logic processing circuit 802 [i] The end Q of trigger 801 [i-1], the previous logic control submodule of third input terminal in3 connection of logic processing circuit 802 [i] First output end out1 of logic processing circuit 802 [i-1], the first output end of logic processing circuit 802 [i] in 21 [i-1] In1 connects the third input terminal in3 of logic processing circuit 802 [i+1] in the latter logic control submodule 21 [i+1], logic The control terminal of the second output terminal out2 connection transmission circuit 803 [i] of processing circuit 802 [i]；

Logic processing circuit 802 [i], for as 801 [i- of d type flip flop in previous logic control submodule 21 [i-1] 1] the end Q exports the first state of the first enable signal Q [i-1], 21 [i-1] logical process in previous logic control submodule The first state of the first output end out1 output Seize ACK message C [i-1] of circuit 802 [i-1], the end Q of d type flip flop 801 [i] are defeated Out when the second state of the first enable signal Q [i], the second enable signal S [i] to transmission circuit 803 [i] of the second state is exported Control terminal, and export the second state Seize ACK message C [i] into the latter logic control submodule 21 [i+1] logical process The third input terminal in3 of circuit 802 [i+1]；It is also used to when logic processing circuit in previous logic control submodule 21 [i-1] When the second state of the first output end out1 output Seize ACK message C [i-1] of 802 [i-1], alternatively, as d type flip flop 801 [i] When the end Q exports the first state of the first enable signal Q [i], the second enable signal S [i] of first state is exported to transmission circuit 803 control terminal, and the Seize ACK message C [i] of first state is exported into the latter logic control submodule 21 [i+1] at logic Manage the third input terminal in3 of circuit 802 [i+1]；

Transmission circuit 803 [i], for delay list will to be corresponded to as the second enable signal S [i] of second state that receives The time delayed signal CLK [i] of member output is exported to phase-interpolation module 30；For example, transmission circuit 803 [i] specifically can be transmission Door.

It is understood that for first logic control submodule, the second input terminal in2 of logic processing circuit The Seize ACK message of the first enable signal and third the input terminal input of input can be directly given by system.

Similar with Seize ACK message described above, first state represents " non-", and the second status representative "Yes" can be distinguished It is indicated by high level and low level.In practical application, the first state and second of Seize ACK message can be set as the case may be The form of expression of state, for example, the first state (i.e. " non-") of signal can be high level, the second state (i.e. "Yes") of signal It can be low level；Alternatively, the first state (i.e. " non-") of signal can be low level, the second state (i.e. "Yes") of signal It can be high level, level state corresponding to the first state and the second state of every class signal can be different, and the application is to this Without limiting.

The concrete operating principle of logic control submodule is described in detail in conjunction with a specific example:

Failing edge state is not detected in first logic control submodule, according to the working principle of d type flip flop, the end Q output 1 The first input end input of (i.e. high level, " non-"), first logic processing circuit is 1, second the first enable signal of input terminal It is also 1 (i.e. high level, " non-"), the third input of first logic processing circuit for the first enabled initial signal that system provides It is 1 (i.e. high level, " non-") that end input, which is also the initial Seize ACK message that system provides,.The first of first logic processing circuit is defeated Outlet output is 0 (i.e. low level, " non-"), and first transmission circuit is not turned on, the second output of first logic processing circuit 1 (i.e. high level, " non-") of end output.

Then, second logic control submodule detects failing edge state, the end the Q output 0 of d type flip flop (i.e. low level, "Yes"), the first input end input of second logic processing circuit is 0；Failing edge is not detected in first logic control submodule State, then the second input terminal of second logic processing circuit is 1 (i.e. high level, " non-")；Logic processing circuit before is not Failing edge state is detected, then the third input terminal of second logic processing circuit inputs 1 (i.e. high level, " non-").Second is patrolled The the first output end output for collecting processing circuit is 1 (i.e. high level, "Yes"), and second is delayed by second transmission circuit conducting The time delayed signal of unit output is exported to phase-interpolation module, and the second output terminal output 0 of second logic processing circuit is (i.e. low Level, "Yes").

Later, no matter third logic control submodule detects or failing edge state is not detected, at logic before It manages circuit (i.e. second logic processing circuit) and detects failing edge state, then the third input terminal of third logic processing circuit is defeated Enter 0 (i.e. low level, "Yes").The first output end output of third logic processing circuit is 0 (i.e. low level, " non-"), third A transmission circuit is not turned on, and the second output terminal of second logic processing circuit continues to output 0 (i.e. low level, "Yes").

The specific structure of logic processing circuit in duty-ratio calibrating circuit is exemplified below.

Referring to Fig. 9, which is the structural schematic diagram for the logic processing circuit that the application specific embodiment provides.

In the embodiment of the present application, logic processing circuit can specifically include: the first phase inverter inv1, the second phase inverter Inv2, third phase inverter inv3, the first NAND gate nand1, the second NAND gate nand2, third NAND gate nand3 and the 4th with it is non- Door nand4；

The input terminal of first phase inverter inv1 connects the end the Q (Q [i- of d type flip flop in previous logic control submodule 1]), the output end of the first phase inverter inv1 connects the first input end of the first NAND gate nand1；

The second input terminal of first NAND gate nand1 connects the output end of the second phase inverter inv2, the first NAND gate nand1 Output end connect the second NAND gate nand2 first input end；

It is first defeated to connect logic processing circuit in previous logic control submodule for the input terminal of second phase inverter inv2 Outlet (C [i-1])；

The output end of the second input terminal connection third phase inverter inv3 of second NAND gate nand2, the second NAND gate nand2 Output end connection transmission circuit control terminal (S [i])；

The end Q (Q [i]) of the input terminal connection d type flip flop of third phase inverter inv3；

The input terminal of the first input end connection third phase inverter inv3 of third NAND gate nand3, third NAND gate nand3 The second input terminal connect the end Q (Q [i-1]) of d type flip flop in previous logic control submodule, third NAND gate nand3's Output end connects the first input end of the 4th NAND gate nand4；

The second input terminal of 4th NAND gate nand4 connects the output end of the second phase inverter inv2, the 4th NAND gate nand4 Output end connect the third input terminal (C [i]) of logic processing circuit in the latter logic control submodule.

Specific output logic is as follows:

Control circuit 804 [i] is used to export the first state or the second shape of Seize ACK message C [i] according to control signal Ctrl State is with control logic processing circuit 802 [i] is in running order or idle state.

Reference is with example shown in Fig. 5 a-5c, since when signal CLK_IN to be calibrated is high-frequency signal, failing edge is detected It is respectively τ, 2 τ, 3 τ and 4 τ that module 20 obtains delay between 4 and signal CLK_IN to be calibrated from the first sub- delay line 11 Time delayed signal treats the detection of calibration signal CLK_IN failing edge to realize, then corresponding logic control of first four delay unit When signal CLK_IN to be calibrated is high frequency, the first state of output Seize ACK message C [i] controls to be corresponded to control circuit in module Logic processing circuit it is in running order, remaining logic processing circuit is in idle condition or closes.

When signal CLK_IN to be calibrated is intermediate-freuqncy signal, failing edge detection module is from the first sub- delay line 11 and second The time delayed signal that 4 delay respectively 2 τ, 4 τ, 6 τ and 8 τ between signal CLK_IN to be calibrated are obtained in sub- delay line 12 comes Realize the detection for treating calibration signal CLK_IN failing edge, then first and the corresponding logic control submodule of second delay unit Control circuit when signal CLK_IN to be calibrated is intermediate frequency, answer by the second state control pair of output Seize ACK message C [i] in block Logic processing circuit is in idle condition, and second, control in the 4th-the six corresponding logic control submodule of delay unit The corresponding logic processing circuit of first state control of circuit output Seize ACK message C [i] is in running order, remaining logical process Circuit is in idle condition or closes.

When signal CLK_IN to be calibrated is low frequency signal, failing edge detection module is sub from the first sub- delay line 11, second 3 delay respectively 4 τ, 8 τ and 11 τ between signal CLK_IN to be calibrated are obtained in delay line 12 and the sub- delay line 13 of third Time delayed signal treats the detection of calibration signal CLK_IN failing edge to realize, then the first-third and the 5th delay unit pair Control circuit is when signal CLK_IN to be calibrated is intermediate frequency in the logic control submodule answered, the second of output Seize ACK message C [i] The logic processing circuit that state control pair is answered is in idle condition, and the 4th, the 6th and the 7th delay unit is corresponding patrols The first state for collecting control circuit output Seize ACK message C [i] in control submodule controls corresponding logic processing circuit and is in work Make state, remaining logic processing circuit is in idle condition or closes.

In practical application, the control logic of control circuit can be specific according to control signal in each logic control submodule Control logic realizes which is not described herein again using one or more nor gates.

The specific structure and working principle of failing edge detection module is illustrated in above content, will insert below to phase Value module is specifically described.

Referring to Figure 10, which is the structural schematic diagram for the phase-interpolation module that the application specific embodiment provides.

In the embodiment of the present application, phase-interpolation module 30, can specifically include: the 4th phase inverter inv4 and phase are inserted It is worth device PI；

Failing edge state detection signal CLK_DOWN is through the 4th phase inverter inv4 input phase interpolation device PI；

Phase interpolator PI is obtained for the output signal according to signal CLK_IN and the 4th phase inverter inv4 to be calibrated Signal CLK_OUT after calibration.

The concrete operating principle of phase interpolator PI is mutually spoken on somebody's behalf as described in the corresponding embodiment of Fig. 6 referring specifically to above Bright, which is not described herein again.

In order to improve the accuracy and precision of duty ratio calibration, in some possible implementations of the embodiment of the present application, Frequency detection module 40 can be also used for the frequency according to signal CLK_IN to be calibrated, send configuration signal to phase interpolator PI, the interpolation range of phase interpolator PI is arranged.

Specifically, as shown in figure 11, phase interpolator may include that (Figure 11 is with 3 groups for illustration for multiple groups phase inverter set Out), every group of phase inverter set and allocation list include that frequency range corresponds；Every group of phase inverter set include two it is in parallel and Join phase inverter pINV and with the concatenated phase inverter sINV that connects of two phase inverter pINV in parallel；

The input terminal of two parallel-connected inverter pINV is separately connected signal to be calibrated and the 4th instead in every group of phase inverter set The output end of phase device inv4, the input terminal of the output end connection series connection phase inverter sINV of two parallel-connected inverter pINV, series connection are anti- Signal CLK_OUT after the output end output calibration of phase device sINV；

Frequency detection module 40 controls any one group of phase inverter specifically for the frequency according to signal CLK_IN to be calibrated Gather in running order, is obtained to carry out phase-interpolation to the signal of different frequency using different configuration of phase inverter set Signal CLK_OUT after calibration.

In some possible implementations of the embodiment of the present application, phase can also be inserted according to the frequency of signal to be calibrated The interpolation range of value device is set, and phase-interpolation is made to be more suitable for the frequency of signal to be calibrated, improves the accurate of phase-interpolation Degree and precision, and then improve the precision of duty ratio calibration.

It should be noted that each embodiment in this specification is described in a progressive manner, each embodiment emphasis is said Bright is the difference from other embodiments, and the same or similar parts in each embodiment may refer to each other.

It should also be noted that, herein, relational terms such as first and second and the like are used merely to one Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain Lid non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including the element.

The above is only the preferred embodiment of the application, not makes any form of restriction to the application.Though Right the application has been disclosed in a preferred embodiment above, however is not limited to the application.It is any to be familiar with those skilled in the art Member, in the case where not departing from technical scheme ambit, all using the methods and technical content of the disclosure above to the application Technical solution makes many possible changes and modifications or equivalent example modified to equivalent change.Therefore, it is all without departing from The content of technical scheme, any simple modification made to the above embodiment of the technical spirit of foundation the application are equal Variation and modification, still fall within technical scheme protection in the range of.

Claims

1. a kind of duty-ratio calibrating circuit characterized by comprising delay line, failing edge detection module and phase-interpolation module；

The delay line is in series with multiple sub- delay lines, and each sub- delay line includes one or more series connection and delay time Equal delay unit, the delay time of delay unit is less than delay unit in latter sub- delay line in previous sub- delay line Delay time, the total delay time of every sub- delay line determines according to the working frequency of signal to be calibrated；The delay line is used It is delayed in the signal to be calibrated；

The failing edge detection module, it is described to school for being obtained from the delay line according to the frequency of the signal to be calibrated Multiple time delayed signals of calibration signal, and the signal to be calibrated is detected according to the signal to be calibrated and each time delayed signal Failing edge, obtain failing edge state detection signal；

The phase-interpolation module, for being calibrated according to the signal to be calibrated and the failing edge state detection signal Signal afterwards.

2. duty-ratio calibrating circuit according to claim 1, which is characterized in that the failing edge detection module includes multiple With the one-to-one logic control submodule of the delay unit；

The logic control submodule switches to idle state or working condition, is being in for controlling signal based on the received The time delayed signal and the signal to be calibrated of corresponding delay unit output are received when working condition, and are believed according to the delay received Number and the signal to be calibrated, be made whether the detection for failing edge state occur；

Wherein, the control signal is determined according to the frequency of the signal to be calibrated；The failing edge state is specially when described When the time delayed signal received is in low level, the signal to be calibrated switches to low level from high level；

First logic control submodule is also used to receive when detecting that the failing edge state occurs by described Time delayed signal export as the failing edge state detection signal to the phase-interpolation module；

K-th of logic control submodule is also used to detect that the failing edge state occurs and front is in work shape When the logic control submodule of state is not detected the failing edge state and occurs, using the time delayed signal received as institute Failing edge state detection signal is stated to export to the phase-interpolation module；K is the integer greater than 1.

3. duty-ratio calibrating circuit according to claim 2, which is characterized in that

The logic control submodule, specifically for defeated when being in idle condition or being not detected the failing edge state and occur Logic control submodule described in the Seize ACK message to the latter of first state out；When detecting that the failing edge state occurs, Export logic control submodule described in the Seize ACK message to the latter of the second state；It is also used in running order and receive When the Seize ACK message of first state, according to the time delayed signal and the signal to be calibrated received, be made whether to occur it is described under Detection along state is dropped；It is also used to when receiving the Seize ACK message of the second state, continues to the latter logic control submodule Send the Seize ACK message of the second state.

4. duty-ratio calibrating circuit according to claim 3, which is characterized in that the logic control submodule, comprising: D Trigger, logic processing circuit, transmission circuit and control circuit；

The end D of the d type flip flop connects the signal to be calibrated, and the corresponding delay of input end of clock connection of the d type flip flop is single The time delayed signal of member output, the end Q of the d type flip flop connects the first input end of the logic processing circuit；

Second input terminal of the logic processing circuit connects the end Q of d type flip flop in previous logic control submodule, described to patrol The third input terminal for collecting processing circuit connects the first output end of logic processing circuit in previous logic control submodule, described First output end of logic processing circuit connects the third input terminal of logic processing circuit in the latter logic control submodule, institute The second output terminal for stating logic processing circuit connects the control terminal of the transmission circuit；

The logic processing circuit, for exporting the first enable signal when the end Q of d type flip flop in previous logic control submodule First state, the first output end of logic processing circuit exports the Seize ACK message in the previous logic control submodule First state, the d type flip flop the end Q when exporting the second state of the first enable signal, the second state of output second makes Can signal to the control terminal of the transmission circuit, and export the Seize ACK message of the second state to the latter logic control submodule The third input terminal of logic processing circuit in block；It is also used to when logic processing circuit in the previous logic control submodule When first output end exports the second state of Seize ACK message, alternatively, when the end Q of the d type flip flop exports the first enable signal When first state, the second enable signal of first state is exported to the control terminal of the transmission circuit, and export first state The third input terminal of Seize ACK message logic processing circuit into the latter logic control submodule；

The transmission circuit, for prolonging what corresponding delay unit exported when receiving the second enable signal of the second state When signal export to the phase-interpolation module；

The control circuit is used for according to the control signal, and the first state or the second state for exporting Seize ACK message are to control State that logic processing circuit is in running order or idle state.

5. duty-ratio calibrating circuit according to claim 4, which is characterized in that the logic processing circuit specifically includes: First phase inverter, the second phase inverter, third phase inverter, the first NAND gate, the second NAND gate, third NAND gate and the 4th with it is non- Door；

The input terminal of first phase inverter connects the end Q of d type flip flop in the previous logic control submodule, and described first The output end of phase inverter connects the first input end of first NAND gate；

Second input terminal of first NAND gate connects the output end of second phase inverter, the output of first NAND gate End connects the first input end of second NAND gate；

It is first defeated to connect logic processing circuit in the previous logic control submodule for the input terminal of second phase inverter Outlet；

Second input terminal of second NAND gate connects the output end of the third phase inverter, the output of second NAND gate End connects the control terminal of the transmission circuit；

The first input end of the third NAND gate connects the input terminal of the third phase inverter, and the second of the third NAND gate Input terminal connects the end Q of d type flip flop in the previous logic control submodule, and the output end of the third NAND gate connects institute State the first input end of the 4th NAND gate；

Second input terminal of the 4th NAND gate connects the output end of second phase inverter, the output of the 4th NAND gate End connects the third input terminal of logic processing circuit in the latter logic control submodule.

6. according to duty-ratio calibrating circuit described in claim 2-5 any one, which is characterized in that further include: frequency detecting Module；

The frequency detection module, for detecting the frequency of the signal to be calibrated；It is also used to and according to the configuration being previously obtained Table determines frequency range belonging to the frequency of the signal to be calibrated, and exports control corresponding to the frequency range determined Signal is to each logic control submodule, so that the logic control submodule is in idle condition or working condition；

7. duty-ratio calibrating circuit according to claim 6, which is characterized in that the phase-interpolation module, comprising: the 4th Phase inverter and phase interpolator；

The phase interpolator, for the output signal according to the signal to be calibrated and the 4th phase inverter, described in acquisition Signal after calibration；

The frequency detection module is also used to the frequency according to the signal to be calibrated, sends configuration signal to the phase and inserts It is worth device, the interpolation range of the phase interpolator is arranged.

8. duty-ratio calibrating circuit according to claim 7, which is characterized in that the phase interpolator, including multiple groups are anti- Phase device set, phase inverter set described in every group and the allocation list include that frequency range corresponds；Phase inverter collection described in every group Close include two parallel-connected inverters in parallel and with the phase inverter of connecting of the inverter series of described two parallel connections；

The input terminal of two parallel-connected inverters is separately connected the signal to be calibrated and described in phase inverter set described in every group The output end of four phase inverters, the output end of described two parallel-connected inverters connect the input terminal of the series connection phase inverter, the string Signal after joining the output end output calibration of phase inverter；

The frequency detection module, specifically for the frequency according to the signal to be calibrated, control any one group described in phase inverter Gather in running order.

9. duty-ratio calibrating circuit according to claim 6, which is characterized in that

Each sub- delay line corresponds to a frequency range in the allocation list, and the previous sub- delay line is corresponding Frequency range is greater than the corresponding frequency range of sub- delay line described in the latter.

10. duty-ratio calibrating circuit according to claim 9, which is characterized in that

The total delay time of first sub- delay line to m-th of sub- delay line is greater than or equal to described m-th sub- delay line The maximum time of low-limit frequency signal positive half period within the scope of respective frequencies, m are the positive integer greater than 1.