CN116339446A - Clock burr signal generation method based on selection signal and offset signal - Google Patents
Clock burr signal generation method based on selection signal and offset signal Download PDFInfo
- Publication number
- CN116339446A CN116339446A CN202310257334.6A CN202310257334A CN116339446A CN 116339446 A CN116339446 A CN 116339446A CN 202310257334 A CN202310257334 A CN 202310257334A CN 116339446 A CN116339446 A CN 116339446A
- Authority
- CN
- China
- Prior art keywords
- clock
- signal
- clock signal
- clk
- fault
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 title abstract description 7
- 230000003111 delayed effect Effects 0.000 claims abstract description 5
- 230000000630 rising effect Effects 0.000 claims abstract description 4
- 102000003800 Selectins Human genes 0.000 claims description 6
- 108090000184 Selectins Proteins 0.000 claims description 6
- AAEVYOVXGOFMJO-UHFFFAOYSA-N prometryn Chemical compound CSC1=NC(NC(C)C)=NC(NC(C)C)=N1 AAEVYOVXGOFMJO-UHFFFAOYSA-N 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 11
- 230000006698 induction Effects 0.000 description 11
- 238000013461 design Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000011160 research Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 230000002427 irreversible effect Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002688 persistence Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/0435—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Pulse Circuits (AREA)
Abstract
The invention discloses a clock burr signal generation method based on a selection signal and an offset signal, which comprises the following steps: obtaining a second clock signal based on the initial clock signal delayed by Δt on the clock; obtaining a third clock signal based on the second clock signal delayed by Δt on the clock; the level of the clock edge signal trigger is set to be high, and the rising edge part of the third clock signal and the falling edge part of the second clock signal are overlapped to obtain a clock signal clk_error; the clock signal clk_error is injected into a designated clock period for executing the AES advanced encryption standard algorithm flow, and the trigger signal is modified to be high level in a clock running interval where the fault clock signal is required to be generated, so that a first fault clock signal is generated. The invention has low cost for generating the clock burr signal, can not damage the internal structure of the encryption algorithm execution equipment, and has high applicability.
Description
Technical Field
The invention belongs to the technical field of electronic signal communication, and particularly relates to a clock burr signal generation method based on a selection signal and an offset signal.
Background
The encryption algorithm is actually a mapping relation formula meeting a certain mathematical rule, and the encryption operation is that the user inputs the concealed message and the parameter key of the mapping relation and outputs the result as another ciphertext. The core part of the cryptographic mechanism is unknown in design, and the encryption algorithm and the internal implementation principle thereof should be published externally and not used as secret content. Researchers gradually separate two directions of encryption algorithm design research and encryption algorithm attack analysis research in the research process of the encryption algorithm. In the attack analysis aiming at the encryption algorithm, the attack analysis is mainly divided into a non-invasive attack mode and an invasive attack mode. Non-invasive attacks mainly include side channel attack analysis, energy consumption attack analysis, etc., and invasive attack modes are generally implemented by performing an encryption algorithm operation on an encryption device, and a researcher performs error injection by adopting a fault induction technology, that is, inducing errors in some units for performing internal data storage and reading by a certain means so as to generate faults.
The fault induction technology is mainly based on optical fault injection attack, temperature fault attack change, cache attack means such as cache control and the like. However, in many fault injection attack implementation schemes, the cost of building a platform, attempting to attack a device and the like is too high, and most fault induction technologies can generate irreversible effects on implementation equipment of an encryption algorithm, so that multiple balance tests are difficult to perform, and therefore, the applicability of many fault induction technologies is not wide.
Disclosure of Invention
In order to solve the problems, the invention provides the following scheme: a clock glitch generation method based on a select signal and an offset signal, comprising:
based on the initial clock signal clk, delaying the clock by deltat to obtain a second clock signal clk_delay1;
obtaining a third clock signal clk_delay2 based on the second clock signal clk_delay1 by delay Δt on the clock;
the level of the clock edge signal trigger is set to be high, and the rising edge part of the third clock signal clk_delay2 and the falling clock edge part of the second clock signal clk_delay1 are overlapped to obtain a clock signal clk_error;
and injecting the clock signal clk_error into a designated clock period for executing an AES advanced encryption standard algorithm flow, and generating a first fault clock signal by modifying a trigger signal into a high level in a clock running interval in which the fault clock signal is required to be generated.
Preferably, the first fault clock signal is generated in a second stage of the clock signal clk_error.
Preferably, let T denote the period under normal execution, the clock glitch period data being T-2 Δt;
the precision of the clock burr signal is expressed as theta, and the delay precision theta allowed by the internal element of the FPGA when the encryption algorithm is executed t θ=2θ t 。
Preferably, the process of obtaining the second clock signal clk_delay1 further comprises,
the internal structure circuit of the chip is subjected to phase offset operation based on the initial clock signal clk, and the offset theta w The clock signal clk_delay is then generated.
Preferably, the internal structure circuit of the chip performs phase offset operation based on the initial clock signal clk, and is offset by θ w The post-generation clock signal clk _ delay is also followed by,
when the fault clock signal is obtained by acting on the clk signal at a determined position and time, the selection signal selectin is set to a high level, and the phase of the selection signal selectin is shifted by an amount theta from the initial clock signal clk p 。
Preferably, when the clk signal is acted upon at the determined location and time to obtain the fault clock signal, the selection signal selectin is set high and then further comprises,
and based on selection by the selector, combining the initial clock signal clk, the clock signal clk_delay and the selection signal select to obtain a second fault clock signal.
Preferably, the second fault clock signal is generated in a second stage of the clock signal clk_error.
Preferably, the width data of the clock burr signal at high level is T w (θ w )；
Generating the second fault clock signal with a clock period T p (θ p )；
The precision delta of the second fault clock signal is enabled to be delta, and precision delay data caused by phase bias of an internal structure circuit is delta t Delta=delta t 。
The invention discloses the following technical effects:
compared with the existing fault induction technical scheme, the method adopts the clock burr signal as the induction technology, and has higher degree of agreement with the internal physical result of the encryption algorithm implementation equipment. Compared with other fault induction technologies, the clock burr signal has extremely low invasiveness to physical equipment, negligible destructiveness to internal structures and low cost compared with other fault induction technologies. Meanwhile, compared with the same type of fault burr signal generation schemes in the transverse direction, the method has the following advantages and effects:
1) The fault induction technology generation scheme provided by the invention is designed based on the offset of a selection signal and a time delay signal, and the frequency of clock burrs generated by the method is continuously adjustable and easy to control due to the existence of the selection signal;
2) The clock burr generation technical design proposal provided by the invention utilizes the offset of the time delay signal, the superposition generation of the selection control signal and the initial input signal. On the basis of the time delay signal, the adjustable offset is adjusted, and the effect brought by the design is that the precision of the fault burr signal is high enough to meet the fault attack test with higher requirement on the signal precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a selection signal and a delay signal according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a selection signal and an offset signal according to an embodiment of the present invention;
FIG. 3 is a diagram of a burr generation framework according to an embodiment of the present invention;
FIG. 4 is a graph of a relationship between a fault clock signal and an input signal according to an embodiment of the present invention;
fig. 5 is a diagram of a clock burr generator policy relationship according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
The invention aims at solving the problems that most fault induction technology generation schemes have poor universality and difficult technology due to the characteristics of higher cost, irreversible destructiveness to encryption equipment, difficult persistence test and the like when the intrusion attack mode analysis of the encryption algorithm is carried out.
In order to solve the technical problems, the invention provides a clock glitch fault induction technology which generates a clock glitch signal based on a clock selection signal and a clock offset signal.
As shown in fig. 1, in the scheme for generating the fault clock glitch signal based on the selection signal and the offset signal, the internal characteristics of the physical hardware are utilized to complete the work. The clock burr generation scheme is obtained by combining the circuit structure inside the chip with the clock signal inside the chip.
Further, an initial clock signal clk is set, a second clock signal clk_delay1 is delayed by Δt in clock compared to the initial signal clk, and a third clock signal clk_delay2 is delayed by Δt on the basis of clk_delay1, so that the delay clock is 2 Δt compared to the initial clock signal clk.
When the fault injection clock signal clk_error needs to be generated, the rising edge part of the third clock signal and the falling clock edge part of the first time delay signal are overlapped by setting the level of the clock edge signal trigger to be high.
If faults are to be injected in a designated clock cycle of executing the AES advanced encryption standard algorithm flow, the corresponding trigger signal is modified to be high level in a clock operation interval in which the fault clock signal is required to be generated, and then the fault clock signal can be generated.
The fault clock signal is generated in the second stage of clk_error, and is in a low level state before the fault clock signal is generated, so that the small section before the generated fault clock glitch signal can be ignored, and the fault attack experiment is not influenced.
Let T denote the period under normal execution for convenience, the clock glitch period data may be obtained as T-2 Δt from the information in fig. 1. If the precision of the clock glitch is expressed as theta, the delay precision theta allowed by the internal elements of the FPGA when executing the encryption algorithm t Then the relationship between them is θ=2θ t 。
The scheme of generating fault burrs by utilizing the selection signal and the time delay signal is designed, and in some fault attack tests with higher requirement precision, the requirements may not be met. Therefore, the invention performs a certain degree of phase shift operation processing on the delay signal clk_delay, so as to obtain the design scheme shown in fig. 2 below, and further improve the precision of the fault signal.
As shown in fig. 2, the clk signal is consistent with the preservation shown in fig. 1, and the function of the clk signal is also consistent with that of the first scheme, and the delay signal clk_delay is different from that of the first scheme, so that the structural circuit in the chip performs phase offset operation based on the clk normal signal, and the offset theta w The signal is then generated. The effect of the selection signal selection is, however, to make it possible to select when the clock glitch signal is to be generated exactly. Clock glitch generation for select signal and scheme oneIn the scheme, trigger edge signals trigger act consistently, when the trigger edge signals trigger to act with the clk signal at determined positions and moments to obtain a fault signal, the selectin signal is set to be high level, and the initial clk clock signal is offset by theta in phase p 。
Further optimizing the scheme, combining the initial signal, the delay signal and the selection signal by using a selector, and obtaining the required fault signal by superposition of the three signals. Consistent with the results of the glitch signal generated by the first scheme described above, in fig. 2, a fault signal will be generated when the clk err signal is executed to the second stage.
Further, the width data of the clock burr under the high level is T w (θ w ) The clock period of the generated fault signal is T p (θ p ). Assuming the precision delta of the fault signal under the scheme, the precision delay data caused by the internal structure circuit after phase deviation reaches delta t The ratio between them is delta=delta t 。
The fault clock signal generation scheme as described in fig. 2 may be divided into a control module, a selector module, and a fault clock signal generation module when described in detail. The association between the modular parts and the effect of each other is shown in figure 3.
The delay phase-locked loop controller is used for providing an initial clock signal clk and offset phase values required by generating clock glitch signals, and then outputting the clock glitch signals generated after operation to other partial modules. The selection signal indicates the selector, which consists of a control module and a counter part, the function of which is to provide the selection signal selection as output to other modules, as described in the first solution above, where the exact position of the generating fault clock signal and its timing need to be located, so that the counter function is presented here. And the most main burr signal generating part combines the output results of the delay locked loop controller and the counter module by a Multiplexer (MUX), and finally combines the output results with a delay locked loop controller control module to generate a clock burr fault signal clk_err, thereby completing the generation of the clock burr signal.
The design scheme for generating clock burrs based on the selection signal and the time delay offset signal has the characteristics of high precision, continuous and adjustable frequency, negligible destructiveness to encryption algorithm execution equipment and the like, and has high applicability. A simple experimental example of the design proposed by the invention herein will be described.
Example 1
As shown in fig. 4, by dividing the original input clock signal by two counters, a fault clock signal as expected can be obtained finally. The first signal is the externally provided clk_in, the second signal is the fault clock signal clk_error, and the glitch signal is generated during the second period of the clk_error signal. From the information shown in fig. 4, the relationship between the normal clock period, the clock period of the glitch, and the period of the clk_in signal provided from the outside can be obtained: the ratio of the period under normal execution to the period of clk_in is 4:1, and the ratio of the period under clock glitch is 2:1.
According to the above information and the mentioned clock burr generation scheme, the clock burr generation module is implemented with Verilog HDL on a ChipWhisperer FPGA development platform. In Modelsim, simulation is performed on the result of the implementation of the above-mentioned scheme, and as shown in FIG. 5, when the clk_error signal is implemented to stage 5, a fault clock signal is generated under the influence of the set signal, and the ratio of the periodic relationship of the normal clock signal to the fault signal is 2:1. There is also a flag signal for the purpose of setting the flag to 0 and terminating the counter2 counter count after the clock glitch signal is generated.
Further, the precision of generating the fault signal by using the scheme of generating the clock glitch signal according to the present embodiment is only affected by the clk_in signal provided from the outside. Therefore, in the case of an attack experiment, the frequency interval of the external source generating the clk_in signal needs to be large enough to ensure that specific accuracy and frequency requirements are met.
The above embodiments are only illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solutions of the present invention should fall within the protection scope defined by the claims of the present invention without departing from the design spirit of the present invention.
Claims (8)
1. A clock glitch generation method based on a selection signal and an offset signal, comprising:
based on the initial clock signal clk, delaying the clock by deltat to obtain a second clock signal clk_delay1;
obtaining a third clock signal clk_delay2 based on the second clock signal clk_delay1 by delay Δt on the clock;
the level of the clock edge signal trigger is set to be high, and the rising edge part of the third clock signal clk_delay2 and the falling clock edge part of the second clock signal clk_delay1 are overlapped to obtain a clock signal clk_error;
and injecting the clock signal clk_error into a designated clock period for executing an AES advanced encryption standard algorithm flow, and generating a first fault clock signal by modifying a trigger signal into a high level in a clock running interval in which the fault clock signal is required to be generated.
2. The clock glitch generation method of claim 1 in which said first fault clock signal is generated in a second stage of said clock signal clk_error.
3. The method for generating a clock glitch signal of claim 1 in which the selection signal and the offset signal are based,
let T denote the period under normal execution, the clock burr period data is T-2 delta T;
the precision of the clock burr signal is expressed as theta, and the delay precision theta allowed by the internal element of the FPGA when the encryption algorithm is executed t θ=2θ t 。
4. The method of generating a clock glitch signal based on a selection signal and an offset signal of claim 1 in which the process of obtaining the second clock signal clk_delay1 based on the initial clock signal clk delayed in clock by Δt further comprises,
the internal structure circuit of the chip is subjected to phase offset operation based on the initial clock signal clk, and the offset theta w The clock signal clk_delay is then generated.
5. The method for generating clock glitch signal of claim 4 in which the internal circuitry of the chip is phase-shifted by θ based on the initial clock signal clk w The post-generation clock signal clk _ delay is also followed by,
when the fault clock signal is obtained by acting on the clk signal at a determined position and time, the selection signal selectin is set to a high level, and the phase of the selection signal selectin is shifted by an amount theta from the initial clock signal clk p 。
6. The method for generating a clock glitch signal of claim 5 in which, when the clk signal is applied at a determined location and time to generate a fault clock signal, setting the select signal select to high further comprises,
and based on selection by the selector, combining the initial clock signal clk, the clock signal clk_delay and the selection signal select to obtain a second fault clock signal.
7. The method of generating a clock glitch signal based on a selection signal and an offset signal of claim 6 in which said second faulty clock signal is generated in a second stage of clock signal clk_error.
8. The method of generating a clock glitch signal of claim 6 in which,
the width data of the clock burr signal under the high level is T w (θ w )；
Generating the second fault clock signal with a clock period T p (θ p )；
The precision delta of the second fault clock signal is enabled to be delta, and precision delay data caused by phase bias of an internal structure circuit is delta t Delta=delta t 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310257334.6A CN116339446A (en) | 2023-03-09 | 2023-03-09 | Clock burr signal generation method based on selection signal and offset signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310257334.6A CN116339446A (en) | 2023-03-09 | 2023-03-09 | Clock burr signal generation method based on selection signal and offset signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116339446A true CN116339446A (en) | 2023-06-27 |
Family
ID=86892396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310257334.6A Pending CN116339446A (en) | 2023-03-09 | 2023-03-09 | Clock burr signal generation method based on selection signal and offset signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116339446A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117033110A (en) * | 2023-10-09 | 2023-11-10 | 深圳市纽创信安科技开发有限公司 | Clock burr string generation method, system and equipment |
-
2023
- 2023-03-09 CN CN202310257334.6A patent/CN116339446A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117033110A (en) * | 2023-10-09 | 2023-11-10 | 深圳市纽创信安科技开发有限公司 | Clock burr string generation method, system and equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2020248318A1 (en) | Bidirectional adaptive clock circuit supporting wide frequency range | |
| Agoyan et al. | When clocks fail: On critical paths and clock faults | |
| Zussa et al. | Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism | |
| Ordas et al. | EM injection: Fault model and locality | |
| US20110302460A1 (en) | Apparatus and method for detecting an approaching error condition | |
| US10033362B1 (en) | PVTM-based wide voltage range clock stretching circuit | |
| KR101046274B1 (en) | Clock signal delay circuit | |
| US11971740B2 (en) | Timing error detection and correction circuit | |
| KR20200038555A (en) | Devices and methods for detecting loop count in delay-fixed loop | |
| CN116339446A (en) | Clock burr signal generation method based on selection signal and offset signal | |
| KR102016532B1 (en) | Semiconductor device and method of driving the same | |
| CN102254110A (en) | Control circuit for randomization of overturning moment of register | |
| CN112364391A (en) | Arbiter PUF reliable response screening system and bias control and response screening method thereof | |
| Kazemi et al. | On a low cost fault injection framework for security assessment of cyber-physical systems: Clock glitch attacks | |
| US8539413B1 (en) | Frequency optimization using useful skew timing | |
| Fojtik et al. | A fine-grained GALS SoC with pausible adaptive clocking in 16 nm FinFET | |
| Igarashi et al. | Concurrent faulty clock detection for crypto circuits against clock glitch based DFA | |
| KR100925393B1 (en) | Domain Crossing Circuit of Semiconductor Memory Apparatus | |
| Zhou et al. | Reliable SoC design and implementation of SHA-3-HMAC algorithm with attack protection | |
| CN102522966A (en) | Programmable nanosecond pulse signal generator | |
| CN110795900B (en) | Intelligent burr design circuit | |
| Zhou et al. | Analysis of Fault Characteristics Based on Clock Glitch Injection | |
| Emmert et al. | An asynchronous MPGA THx2 cell and architecture for mitigating side-channel attacks | |
| JP2000249747A (en) | Timing signal generating circuit for semiconductor test device | |
| Kaur et al. | Injecting power attacks with voltage glitching and generation of clock attacks for testing fault injection attacks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |