CN109831206A - Delay lock loop and delay lock method - Google Patents
Delay lock loop and delay lock method Download PDFInfo
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- CN109831206A CN109831206A CN201910113016.6A CN201910113016A CN109831206A CN 109831206 A CN109831206 A CN 109831206A CN 201910113016 A CN201910113016 A CN 201910113016A CN 109831206 A CN109831206 A CN 109831206A
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Abstract
The present invention provides a kind of delay lock loop and delay lock method, comprising: the simulation main delay line based on master delay control word delay reference clock signal；Identify the digital phase detection module of delayed reference clock signal front and back phase difference；Based on adjusting offset master delay control word, the corresponding master delay control word of a cycle will be postponed and be assigned to the digital main control module that setting postpones control word；The setting delay control word of setting ratio is used as from the digital from control module of delay control word；Based on the simulation postponed from delay control word control input clock signal from delay line.Delayed reference clock signal a cycle is controlled based on phased lock loop；Corresponding master delay control word is assigned to setting delay control word, and multiplied by the delay for adjusting input clock signal after setting ratio.The present invention uses digital phase discriminator and digitial controller, and reliability is higher, and loop is more stable；Using analog delay line, it can be achieved that adjustable, the simplified circuit debugging difficulty of delay.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of delay lock loop and delay lock method.
Background technique
With the development of modern integrated circuits technology, chip-scale constantly increases, and working frequency is continuously improved, piece internal clock
Distribution quality and clock delay become more and more important.Delay lock loop (Delay Locked Loop, DLL), can satisfy
The precise synchronization demand of high-frequency clock in piece, realize eliminate clock delay, realize zero transmission delay, make clock input signal with it is whole
Deviation is minimum between a chip interior clock pins.As a part very important in IC design, delay lock
Ring has been increasingly becoming focus concerned by people, is more widely used in various SoC (System on Chip, system on chip) chip
In.
Delay lock loop is assisted in SDIO (Secure Digital Input and Output, secure digital input and output)
It assesses a bid for tender in quasi- application, the clock alignment between host and SD card may be implemented, guarantee that the timing between clock and data can
It meets the requirements, so that it is guaranteed that the correctness of data transmission.Delay lock loop is adapted to different working frequencies simultaneously, is suitable for
The different new and old editions of SDIO standard.
But traditional digital delay lock loop has complicated cumbersome sequence problem, once timing malfunctions, entire ring
Road all will be unable to work normally；And the accuracy of traditional analog delay locked loop is significantly insufficient.Therefore, when how to propose a kind of
The delay lock loop that sequence is simple, accuracy is high has become one of those skilled in the art's urgent problem to be solved.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of delay lock loop and delay locks
Determine method, is used for the problems such as solving delay lock loop complex time, poor accuracy in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of delay lock loop, the delay lock loop
It includes at least:
Main delay line, digital phase detection module, digital main control module, number are simulated from control module and is simulated from delay
Line；
The simulation main delay line is connected to the output end of the digital main control module, and receives reference clock signal,
Master delay control word based on the digital main control module output controls the delayed reference clock signal；
The digital phase detection module is connected to the output end of the simulation main delay line, and receives the reference clock letter
Number, for identifying the phase difference before and after the delayed reference clock signal；
The number main control module is connected to the output end of the digital phase detection module, is based on the reference clock signal
Postpone master delay control word described in the adjusting offset of front and back, and will be corresponding to the delayed reference clock signal a cycle
Master delay control word is assigned to setting delay control word；
The number is connected to the output end of the digital main control module from control module, and receives control signal, base
It is exported after the setting is postponed control word multiplied by setting ratio by the control signal as from delay control word；
The simulation is connected to output end of the number from control module from delay line, and receives and the reference clock
Signal controls the input clock signal delay from delay control word based on described with the input clock signal of frequency.
Optionally, the simulation main delay line includes multiple analogue delay units, the first input of each analogue delay unit
First output end of end connection prime, the second input terminal connect the second output terminal of rear class, and prime mould is worked as in the output of the first output end
The postpones signal of the first input end signal of quasi- delay cell, second output terminal select prime by the master delay control word
First output end signal or the output of the second output terminal signal of rear class, control terminal connect the master delay control word；Wherein, first
Input terminal of the first input end of grade analogue delay unit as the simulation main delay line, second output terminal is as the simulation
The output end of main delay line；Second input terminal of afterbody analogue delay unit connects low level.
More optionally, the analogue delay unit includes delayer and data selector；The input terminal of the delayer is made
For the first input end of the analogue delay unit, first output end of the output end as the analogue delay unit；The number
Connect the output end of the delayer according to the first input end of selector, the second input terminal as the analogue delay unit
Two input terminals, the control terminal connection master delay control word, second output terminal of the output end as the analogue delay unit,
In, when control terminal high level of the data selector, exports the output signal of the delayer.
More optionally, the simulation is identical as the simulation structure of main delay line from delay line.
Optionally, the digital phase detection module includes single analog delay line, the first d type flip flop, the second d type flip flop,
3d flip-flop and four d flip-flop；The input terminal of the single analog delay line connects the delay letter of the reference clock signal
Number, the adjacent delay signal of the single analog delay line input signal is exported after a delay cell；The first D touching
The data terminal of hair device connects the postpones signal of the reference clock signal, and clock end connects the reference clock signal；Described
The data terminal of 2-D trigger connects the positive output end of first d type flip flop, and clock end connects the reference clock signal,
Positive output end exports first phase comparison result；The data terminal of the third d type flip flop connects the single analog delay line
Output signal, clock end connects the reference clock signal；The data terminal of the four d flip-flop connects the 3rd D touching
The positive output end of device is sent out, clock end connects the reference clock signal, and positive output end exports second phase comparison result.
Optionally, the digital main control module includes and logic unit and counting unit；It is described to be received with logic unit
The inverted signal of adjacent two signals of the digital phase detection module output, and progress and operation；The counting unit is connected to institute
The output end with logic unit is stated, and receives one in adjacent two signals that the digital phase detection module exports, works as phase
Difference reduces the master delay control word when being greater than a cycle, does not change the master delay control when phase difference is equal to a cycle
Word processed increases the master delay control word when phase difference is less than a cycle.
Optionally, the setting ratio is fixed value or adjustable value.
More optionally, the number includes multiplication unit from control module, and the multiplication unit receives the setting delay
Control word and the control signal, to realize multiplying.
Optionally, the delay lock loop is suitable for secure digital input-output card.
In order to achieve the above objects and other related objects, the present invention provides a kind of delay lock method, the delay lock
Method includes at least:
Reference clock signal is postponed, the phase difference of the detection delay front and back reference clock signal, based on detection
Obtained phase comparison result generates the delay time that master delay control word adjusts the reference clock signal, until the reference
Clock signal delay a cycle；
The corresponding master delay control word of the delayed reference clock signal a cycle is assigned to setting delay control word,
And multiplied by setting ratio, obtain from delay control word；
It is real based on the delay from delay control word adjustment and input clock signal of the reference clock signal with frequency
The delay lock of the existing input clock signal.
Optionally, when the master delay control word adjusts delay by the number of the selected analogue delay unit of control
Between.
Optionally, it is sampled using postpones signal of the reference clock signal to the reference clock signal；When adopting
Sample signal is high level, then is delayed over half period and is less than a cycle；When sampled signal is low level, then delay is less than
Half period.
More optionally, the delay time of the reference clock signal is judged based on the adjacent two phase comparison results；
When the value of adjacent two phase comparison results is 10, then the delayed reference clock signal a cycle is determined, loop-locking, when
Preceding master delay control word is assigned to setting delay control word；When the value of adjacent two phase comparison results is 00, then described in judgement
Delayed reference clock signal is greater than a cycle, reduces the value of the master delay control word, loop is unlocked；When adjacent two phases
The value of bit comparison result is 11, then determines that the delayed reference clock signal is less than a cycle, increases the master delay control
The value of word, loop are unlocked；When adjacent two phase comparison results value be 01, then determine that the delayed reference clock signal is
Half period, increases the value of the master delay control word, and loop is unlocked.
Optionally, the setting ratio is fixed value or adjustable value.
As described above, delay lock loop and delay lock method of the invention, have the advantages that
Delay lock loop and delay lock method of the invention use digital phase discriminator and digitial controller, reliability compared with
Height, loop are more stable.
Delay lock loop and delay lock method of the invention uses analog delay line, and the adjustable of delay may be implemented, and
And the problems such as without the concern for settling time (setup time) common in digital circuit, retention time (hold time), letter
Circuit debugging difficulty is changed.
Detailed description of the invention
Fig. 1 is shown as the structural schematic diagram of delay lock loop of the invention.
Fig. 2 is shown as the structural schematic diagram of simulation main delay line of the invention.
Fig. 3 is shown as the structural schematic diagram of analogue delay unit of the invention.
Fig. 4 is shown as the structural schematic diagram of digital phase detection module of the invention.
Fig. 5 is shown as the structural schematic diagram of digital main control module of the invention.
Fig. 6 is shown as the digital structural schematic diagram from control module of the invention.
Component label instructions
1 delay lock loop
11 simulation main delay lines
111 analogue delay units
111a~111c first~third level analogue delay unit
12 digital phase detection modules
121~124 the first~the four d flip-flops
125 single analog delay lines
13 digital main control modules
131 counting units
14 is digital from control module
141 multiplication units
15 simulate from delay line
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to FIG. 1 to FIG. 6.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
As shown in Figure 1, the present embodiment provides a kind of delay lock loop 1, the delay lock loop 1 includes:
Main delay line 11, digital phase detection module 12, digital main control module 13, number are simulated from control module 14 and is simulated
From delay line 15.
As shown in Figure 1, the simulation main delay line 11 is connected to the output end of the digital main control module 13, and receive
Reference clock signal Refclk, the master delay control word MCODE exported based on the digital main control module 13 control the ginseng
Examine clock signal Refclk delay.
Specifically, the simulation main delay line 11 includes multiple analogue delay units 111, each analogue delay unit 111
First output end PASS, the second output terminal OUT of the second input terminal RET connection rear class, the of first input end IN connection prime
Postpones signal of the one output end PASS output when the first input end signal of prime analogue delay unit 111, second output terminal OUT
The first output end signal of prime or the second output terminal signal output of rear class are selected by the master delay control word MCODE；
The control terminal S connection master delay control word MCODE, wherein described in the first input end of first order analogue delay unit is used as
Simulate the input terminal of main delay line 11, output end of the second output terminal as the simulation main delay line 11；Afterbody simulation
Second input terminal of delay cell is useless, can be directly connected to low level.As shown in Fig. 2, only showing in the present embodiment wherein
Three analogue delay units 111, respectively first order analogue delay unit 111a, second level analogue delay unit 111b and
Three-level analogue delay unit 111c.The first input end IN of the first order analogue delay unit 111a receives the reference clock
Signal Refclk, the second input terminal RET connect the second output terminal OUT of the second level analogue delay unit 111b, and first is defeated
Outlet PASS connects the first input end IN of the second level analogue delay unit 111b, and second output terminal OUT is as the mould
The output end of quasi- main delay line 11, to export the postpones signal Rfeclk_delay of the reference clock signal；The second level
The first input end IN of analogue delay unit 111b connects the first output end PASS of the first order analogue delay unit 111a,
Second input terminal RET connects the second output terminal OUT of the third level analogue delay unit 111c, the first output end PASS connection
The first input end IN of the third level analogue delay unit 111c, the second output terminal OUT connection first order analogue delay
The second input terminal RET of unit 111a；The first input end IN connection prime of the third level analogue delay unit 111c is simulated
First output end PASS of delay cell, the second input terminal RET connection low level, the first output end PASS is hanging, the second output
Hold the second input terminal RET of OUT connection prime analogue delay unit.
More specifically, as shown in figure 3, the analogue delay unit 111 includes delayer Delay and data selector MUX；
First input end IN of the input terminal of the delayer Delay as the analogue delay unit 111, output end is as the mould
First output end PASS of quasi- delay cell 111.The first input end of the data selector MUX connects the delayer
The output end of Delay, second input terminal RET of second input terminal as the analogue delay unit 111, control terminal S connection institute
State master delay control word MCODE, second output terminal OUT of the output end as the analogue delay unit 111, wherein work as S=1
When, OUT=PASS；As S=0, OUT=RET.
It should be noted that the simulation main delay line 11 can be using arbitrarily via the master delay control word MCODE
The analog delay circuit of control adjustment delay time, is not limited to the present embodiment.Analogue delay list in the simulation main delay line 11
The quantity of member 111 can be set as needed, and be not limited to this embodiment.
As shown in Figure 1, the digital phase detection module 12 is connected to the output end of the simulation main delay line 11, and receive institute
Reference clock signal Refclk is stated, for identifying the phase difference of reference clock signal Refclk delay front and back.
Specifically, as shown in figure 3, in the present embodiment, the digital phase detection module 12 includes single analog delay line
125, the first d type flip flop 121, the second d type flip flop 122, third d type flip flop 123 and four d flip-flop 124.The single simulation
The input terminal of delay line 125 connects the postpones signal Refclk_delay of the reference clock signal Refclk, output end output
The adjacent delay signal Refclk_delay2 of the postpones signal Refclk_delay, the selection of control terminal (not shown) are single
A delay cell work, i.e., the described postpones signal Refclk_delay are differed with the adjacent delay signal Refclk_delay2
One setting timer, in the present embodiment, the structure of the single analog delay line 125 and the simulation main delay line 11
It is identical；The data terminal D of first d type flip flop 121 connects the postpones signal Refclk_delay of the reference clock signal, when
The clock end clk connection reference clock signal Refclk；The data terminal D connection of second d type flip flop 122 the first D touching
Send out the positive output end Q of device 121, clock end clk connection the reference clock signal Refclk, positive output end Q output first
Phase comparison result PDQ1；The data terminal D connection adjacent delay signal Refclk_ of the third d type flip flop 123
Delay2, the clock end clk connection reference clock signal Refclk；The data terminal D connection institute of the four d flip-flop 124
State the positive output end Q of third d type flip flop 123, clock end clk connection the reference clock signal Refclk, positive output end Q
Export second phase comparison result PDQ2.When first d type flip flop 121 positive output signal Q1 (or the 3rd D triggering
The positive output signal Q2 of device 123) it is 1, then it is current to be delayed over half period and be less than a cycle；When described
The positive output signal Q1 (or positive output signal Q2 of the third d type flip flop 123) of one d type flip flop 121 is 0, then currently
Delay be less than half period.
It should be noted that the digital phase detection module 12 can use phase discriminator or the software generation of Any Digit structure
Code is realized, is not limited to this embodiment.
As shown in Figure 1, the number main control module 13 is connected to the output end of the digital phase detection module 12, it is based on institute
Master delay control word MCODE described in the adjusting offset of reference clock signal Refclk delay front and back is stated, and when by the reference
Master delay control word MCODE corresponding to clock signal Refclk delay a cycle is assigned to setting delay control word PCODE.
Specifically, as shown in figure 4, in the present embodiment, the number main control module 13 include with logic unit and and
Counting unit 131.It is described that adjacent two signals (the first phase that the digital phase detection module 12 exports is received with logic unit and
Bit comparison result PDQ1 and second phase comparison result PDQ2, the second phase comparison result PDQ2 lag behind first phase
Bit comparison result PDQ1) inverted signal, and carry out and operation, export operation result DEC；In the present embodiment, described and logic
Unit and is obtained using two inputs and Men Shixian, inverted signal by the first phase inverter not1 and the second phase inverter not2.The meter
Counting unit 131 is connected to the output end with logic unit and, and receives the digital phase detection module 12 exports adjacent two
One in the signal of position, in the present embodiment, the counting unit 131 receives second phase comparison result PDQ2 and passes through buffer
Signal INC after buffer；When the value of the first phase comparison result PDQ1 and the second phase comparison result PDQ2 point
Not Wei 10 when, the reference clock signal Refclk postpones a cycle, and loop is lock state, the number main control module
13, which assign the value of current master delay control word MCODE to the setting, postpones control word PCODE, and is output to the number from control
In molding block 14, lock state is equally output to the number from control module 14；When the first phase comparison result
When the value of PDQ1 and the second phase comparison result PDQ2 are respectively 00, the reference clock signal Refclk delay is greater than one
A period, the operation result DEC are high level, and the value of the master delay control word MCODE reduces, and loop is unlocked；Work as institute
When stating the value of the first phase comparison result PDQ1 and second phase comparison result PDQ2 and being respectively 11, the reference clock letter
Number Refclk delay is greater than the half period and is less than a cycle, and signal INC is high level, the master delay control word MCODE's
Value increases, and loop is unlocked；When the value of the first phase comparison result PDQ1 and the second phase comparison result PDQ2 point
Not Wei 01 when, then the reference clock signal Refclk postpones half period, and signal INC is high level, and MCODE value increases, institute
The value for stating master delay control word MCODE increases, and loop is unlocked.
It should be noted that the circuit of above-mentioned logic arbitrarily can be achieved or software code is suitable for the invention digital master
Control module 13, is not limited to this embodiment.
As shown in Figure 1, the number is connected to the output end of the digital main control module 13 from control module 14, and connect
Control signal Ctrl is received, the setting is postponed multiplied by making after setting ratio by control word PCODE based on the control signal Ctrl
To be exported from delay control word SCODE.
Specifically, as shown in fig. 6, in the present embodiment, the number includes multiplication unit 141, institute from control module 14
It states multiplication unit 141 and receives the setting delay control word PCODE and control signal Ctrl, the setting is postponed to control
The word PCODE and control signal Ctrl carries out multiplying, and then obtains described from delay control word SCODE.The control
Signal Ctrl controls the setting ratio, and the setting ratio is fixed value or adjustable value.In the present embodiment, the control letter
Number Ctrl is two BITBUS network signals, when the control signal Ctrl is 00, it is described from delay control word SCODE be 0, the mould
It is quasi- not work from delay line 15；It is described to control the simulation from delay control word SCODE when the control signal Ctrl is 01
Postpone 1/4 period from delay line 15；It is described to control institute from delay control word SCODE when the control signal Ctrl is 10
It states simulation and postpones 1/2 period from delay line 15；It is described from delay control word SCODE when the control signal Ctrl is 11
It controls the simulation and postpones 3/4 period from delay line 15.
It should be noted that can arbitrarily carry out the hardware circuit of certain proportion extraction to the setting delay control word PCODE
Or software code is suitable for the present invention, is not limited to this embodiment.The digit of the control signal Ctrl can be set as needed
Fixed, digit is about more, and the minimum adjustment ratio of the setting ratio is smaller.
As shown in Figure 1, the simulation is connected to output end of the number from control module 14 from delay line 15, and receive
With the reference clock signal Refclk with the input clock signal Clkin of frequency, based on described from delay control word SCODE control
The input clock signal Clkin delay, obtains the postpones signal Clkiout of the input clock signal.
Specifically, in the present embodiment, structure and the knot of simulating main delay line 11 of the simulation from delay line 15
Structure is identical, and the series of input signal, control signal and analogue delay unit is adaptively adjusted, and will not repeat them here.
It should be noted that the simulation can be different with the simulation main delay line 11 from the structure of delay line 15, appoint
Meaning is suitable for the invention simulation via the analog delay circuit from delay control word SCODE control adjustment delay time
From delay line 15, be not limited to the present embodiment.
It should be noted that delay lock loop 1 of the invention is suitable for secure digital input-output card (SDIO, Secure
Digital Input and Output Card), output end is connected to outside piece by IO, and the interaction of clock is carried out with SD card, is realized
Clock is aligned with data.Delay lock loop 1 of the invention is also applied for other occasions for needing to carry out delay lock, herein not
It repeats one by one.
Embodiment two
The present embodiment provides a kind of delay lock methods, and in the present embodiment, the delay lock method is based on embodiment
One delay lock loop 1 is realized, in practical applications, the structure side of being suitable for the invention of the above method arbitrarily can be achieved
Method is not limited to this embodiment.The delay lock method includes:
1) reference clock signal is postponed, the phase difference of the detection delay front and back reference clock signal, based on inspection
The phase comparison result measured generates the delay time that master delay control word adjusts the reference clock signal, until the ginseng
Examine clock signal delay a cycle.
Specifically, as shown in Figure 1, being prolonged based on the simulation main delay line 11 to the reference clock signal Refclk
Late, master delay control word MCODE described in original state is setting value.
Specifically, as shown in Figure 1, identifying the reference clock signal Refclk and institute based on the digital phase detection module 12
The phase difference of the postpones signal Refclk_delay of reference clock signal is stated, and obtains phase comparison result PDQ1 and PDQ2.?
In the present embodiment, using the reference clock signal Refclk to the postpones signal Refclk_delay of the reference clock signal
It is sampled；When sampled signal be high level, then be delayed over half period and be less than a cycle；When sampled signal is low electricity
Flat, then delay is less than half period.
Specifically, as shown in Figure 1, being adjusted based on the digital main control module 13 according to the phase comparison result PDQ
The master delay control word MCODE.The simulation main delay line 11, the digital phase detection module 12 and the digital master control molding
Block 13 constitutes phased lock loop.In the present embodiment, when judging the reference based on the adjacent two phase comparison results
The delay time of clock signal；When adjacent two phase comparison results value be 10, then determine the reference clock signal Refclk
Postpone a cycle, loop-locking；When adjacent two phase comparison results value be 00, then determine the reference clock signal
Refclk delay is greater than a cycle, reduces the value of the master delay control word MCODE, loop is unlocked；When adjacent two phases
The value of bit comparison result is 11, then determines that the reference clock signal Refclk delay is less than a cycle, increase the master and prolong
The value of slow control word MCODE, loop are unlocked；When the value of adjacent two phase comparison results is 01, then when determining the reference
Clock signal Refclk delay is half period, increases the value of the master delay control word MCODE, loop is unlocked.Constantly adjustment institute
Master delay control word MCODE is stated, the number by controlling selected analogue delay unit adjusts delay time, so that phase phase
Poor a cycle, loop-locking.
2) the corresponding master delay control word MCODE of reference clock signal Refclk delay a cycle is assigned to and is set
Surely postpone control word PCODE, and multiplied by setting ratio, obtain from delay control word SCODE.
Corresponding master delay control word MCODE is assigned to setting delay control word PCODE when specifically, by loop-locking,
Setting at this time postpones control word PCODE as the number of the corresponding analogue delay unit of delay a cycle.
Specifically, as shown in Figure 1, based on it is described number from control module 14 according to the control signal Ctrl according to setting
Ratio calculates relative delay.The setting ratio is fixed value or adjustable value.In this embodiment, when the control signal Ctrl is
When 00, it is described from delay control word SCODE be 0, the simulation does not work from delay line 15；When the control signal Ctrl is 01
When, it is described to postpone 1/4 period from the delay control word SCODE control simulation from delay line 15；When the control signal
It is described to postpone 1/2 period from the delay control word SCODE control simulation from delay line 15 when Ctrl is 10；When the control
It is described to postpone 3/4 period from the delay control word SCODE control simulation from delay line 15 when signal Ctrl processed is 11.
3) based on described from when postponing the input of control word PSCODE adjustment and the reference clock signal Refclk with frequency
The delay lock of the input clock signal Clkin is realized in the delay of clock signal Clkin.
Delay lock loop and delay lock method of the invention is combined by digital delay phase-locked loop and analog delay line,
Have the advantages that being easily integrated of digital circuit, high reliablity, and avoid digital delay line in the state of different delays,
Timing is difficult to the problem of adjusting.
In conclusion the present invention provides a kind of delay lock loop and delay lock method, comprising: simulation main delay line, number
Word phase demodulation module, digital main control module, number from control module and are simulated from delay line；The simulation main delay line is connected to
The output end of the number main control module, and reference clock signal is received, the master based on the digital main control module output
Postpone control word and controls the delayed reference clock signal；The digital phase detection module is connected to the defeated of the simulation main delay line
Outlet, and receive the reference clock signal, for identifying the phase difference before and after the delayed reference clock signal；The number
Main control module is connected to the output end of the digital phase detection module, based on the phase difference before and after the delayed reference clock signal
Adjust the master delay control word, and by master delay control word assignment corresponding to the delayed reference clock signal a cycle
Postpone control word to setting；The number is connected to the output end of the digital main control module from control module, and receives control
Signal processed, it is based on the control signal that setting delay control word is defeated from delay control word multiplied by being used as after setting ratio
Out；The simulation is connected to output end of the number from control module from delay line, and receives input clock signal, is based on institute
It states from delay control word and controls the input clock signal delay.Reference clock signal is postponed, detection delay front and back institute
The phase difference for stating reference clock signal, the phase comparison result obtained based on detection generate the master delay control word adjustment reference
The delay time of clock signal, until the delayed reference clock signal a cycle；By the delayed reference clock signal one
A period corresponding master delay control word is assigned to setting delay control word, and multiplied by setting ratio, obtains from delay control word；
Based on the delay from delay control word adjustment input clock signal, the delay lock of the input clock signal is realized.This
The delay lock loop and delay lock method of invention use digital phase discriminator and digitial controller, and reliability is higher, and loop is more
Stablize；Using analog delay line, the adjustable of delay may be implemented, and without the concern for settling time common in digital circuit
The problems such as (setup time), retention time (hold time), simplify circuit debugging difficulty.So the present invention effectively overcomes
Various shortcoming in the prior art and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (14)
1. a kind of delay lock loop, which is characterized in that the delay lock loop includes at least:
Main delay line, digital phase detection module, digital main control module, number are simulated from control module and is simulated from delay line；
The simulation main delay line is connected to the output end of the digital main control module, and receives reference clock signal, is based on
The master delay control word of the number main control module output controls the delayed reference clock signal；
The digital phase detection module is connected to the output end of the simulation main delay line, and receives the reference clock signal, uses
Phase difference before and after identifying the delayed reference clock signal；
The number main control module is connected to the output end of the digital phase detection module, is based on the delayed reference clock signal
Master delay control word described in the adjusting offset of front and back, and master corresponding to the delayed reference clock signal a cycle is prolonged
Slow control word is assigned to setting delay control word；
The number is connected to the output end of the digital main control module from control module, and receives control signal, is based on institute
It states control signal and exports setting delay control word as from delay control word multiplied by after setting ratio；
The simulation is connected to output end of the number from control module from delay line, and receives and the reference clock signal
With the input clock signal of frequency, the input clock signal delay is controlled from delay control word based on described.
2. delay lock loop according to claim 1, it is characterised in that: the simulation main delay line includes that multiple simulations are prolonged
Slow unit, the first output end of the first input end connection prime of each analogue delay unit, the second input terminal connect the of rear class
Two output ends, postpones signal of the first output end output when the first input end signal of prime analogue delay unit, the second output
End selects the first output end signal of prime or the second output terminal signal output of rear class, control by the master delay control word
End connects the master delay control word；Wherein, the first input end of first order analogue delay unit is as the simulation master delay
The input terminal of line, output end of the second output terminal as the simulation main delay line；The second of afterbody analogue delay unit
Input terminal connects low level.
3. delay lock loop according to claim 2, it is characterised in that: the analogue delay unit includes delayer and number
According to selector；First input end of the input terminal of the delayer as the analogue delay unit, output end is as the mould
First output end of quasi- delay cell；The first input end of the data selector connects the output end of the delayer, and second
Second input terminal of the input terminal as the analogue delay unit, control terminal connect the master delay control word, output end conduct
The second output terminal of the analogue delay unit, wherein export the delay when control terminal high level of the data selector
The output signal of device.
4. delay lock loop according to any one of claims 1 to 3, it is characterised in that: it is described simulation from delay line with
The structure of the simulation main delay line is identical.
5. delay lock loop according to claim 1, it is characterised in that: the digital phase detection module includes that single simulation is prolonged
Slow line, the first d type flip flop, the second d type flip flop, third d type flip flop and four d flip-flop；The single analog delay line it is defeated
Enter the postpones signal that end connects the reference clock signal, it is defeated that the single analog delay line is exported after a delay cell
Enter the adjacent delay signal of signal；The data terminal of first d type flip flop connects the postpones signal of the reference clock signal, when
Clock end connects the reference clock signal；The data terminal of second d type flip flop connects the positive output of first d type flip flop
End, clock end connect the reference clock signal, and positive output end exports first phase comparison result；The third d type flip flop
Data terminal connect the output signal of the single analog delay line, clock end connects the reference clock signal；4th D
The data terminal of trigger connects the positive output end of the third d type flip flop, and clock end connects the reference clock signal, positive
Output end exports second phase comparison result.
6. delay lock loop according to claim 1, it is characterised in that: it is described number main control module include and logic list
Member and counting unit；The inverted signal of adjacent two signals that the digital phase detection module output is received with logic unit, and
Progress and operation；The counting unit is connected to the output end with logic unit, and it is defeated to receive the digital phase detection module
One in adjacent two signals out reduces the master delay control word when phase difference is greater than a cycle, works as phase difference
Do not change the master delay control word when equal to a cycle, increases the master delay control when phase difference is less than a cycle
Word.
7. delay lock loop according to claim 1, it is characterised in that: the setting ratio is fixed value or adjustable value.
8. delay lock loop according to claim 1 or claim 7, it is characterised in that: it is described number from control module include multiplication
Unit, the multiplication unit receives the setting delay control word and the control signal, to realize multiplying.
9. delay lock loop according to claim 1, it is characterised in that: it is defeated that the delay lock loop is suitable for secure digital
Enter output card.
10. a kind of delay lock method, which is characterized in that the delay lock method includes at least:
Reference clock signal is postponed, the phase difference of the detection delay front and back reference clock signal is obtained based on detection
Phase comparison result generate master delay control word and adjust delay time of the reference clock signal, until the reference clock
Signal delay a cycle；
The corresponding master delay control word of the delayed reference clock signal a cycle is assigned to setting delay control word, and is multiplied
With setting ratio, obtain from delay control word；
Based on the delay from delay control word adjustment and input clock signal of the reference clock signal with frequency, institute is realized
State the delay lock of input clock signal.
11. delay lock method according to claim 10, it is characterised in that: the master delay control word passes through control quilt
The number for the analogue delay unit chosen adjusts delay time.
12. delay lock method according to claim 10, it is characterised in that: using the reference clock signal to described
The postpones signal of reference clock signal is sampled；When sampled signal be high level, then be delayed over half period and less than one
A period；When sampled signal is low level, then delay is less than half period.
13. delay lock method described in 0 or 12 according to claim 1, it is characterised in that: be based on the adjacent two phase ratios
Relatively result judges the delay time of the reference clock signal；When adjacent two phase comparison results value be 10, then determine institute
Delayed reference clock signal a cycle, loop-locking are stated, current master delay control word is assigned to setting delay control word；Work as phase
The value of adjacent two phase comparison results is 00, then determines that the delayed reference clock signal is greater than a cycle, reduce the master
Postpone the value of control word, loop is unlocked；When the value of adjacent two phase comparison results is 11, then reference clock letter is determined
Number delay be less than a cycle, increase the value of the master delay control word, loop is unlocked；When adjacent two phase comparison results
Value be 01, then determine the delayed reference clock signal for half period, increase the value of the master delay control word, loop is not
Lock.
14. delay lock method according to claim 10, it is characterised in that: the setting ratio is fixed value or adjustable
Value.
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