CN102594338A - Counter control type delay-locked loop circuit with mistaken locking correction mechanism - Google Patents
Counter control type delay-locked loop circuit with mistaken locking correction mechanism Download PDFInfo
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Abstract
The invention relates to a counter control type delay-locked loop (DLL) circuit with a mistaken locking correction mechanism. The circuit comprises a digital delay line, a phase discriminator, an addition/subtraction counter and a clock phase arithmetic circuit. An input reference clock signal CLK is connected to the digital delay line and the phase discriminator respectively. The output of the digital delay line is connected to the phase discriminator and the clock phase arithmetic circuit. The output of the phase discriminator is connected to the input of the addition/subtraction counter. The output of the addition/subtraction counter is connected to the digital delay line. Whether the delay of a delayed output clock signal is consistent with a locking condition or not is judged through a locking process detection window, and the delay is timely regulated according to a detection result, so that mistaken locking is avoided, and a delay locking function is accurately realized. The circuit has the advantages that: the problem that the conventional DLL structure is easily mistakenly locked is effectively solved; moreover, the circuit has a wide frequency range and much phase output; and the yield of a chip can be improved.
Description
Technical field
The present invention relates to a kind of digital delay phase-locked loop circuit, particularly a kind of counter controls type delay locked-loop circuit with error lock correction mechanism.
Background technology
Phase-locked loop (PLL) and delay phase-locked loop (DLL) are widely used in the large scale integrated circuit, with solving the skewed clock problem, to the clock signal adjustment of delaying time.Compare with PLL, DLL has more advantage, and it is a first-order system, and good stability has shorter locking time, and simplicity of design does not have jitter accumulation etc., so DLL becomes the main flow circuit that clock signal is delayed time and adjusted gradually at present.
DLL can be divided into analog D LL, digital dll and mixed mode DLL.Anti-clock jitter property and the anti-skewed clock property of analog D LL and mixed mode DLL are relatively good, but this has also limited frequency band range.In addition, analog D LL needs longer locking time and bigger chip area, and the sensitiveness of analog circuit also makes its transplanting under different technology conditions more difficult, and the Design of Simulating Circuits complexity is also bigger.And the advantage of digital dll is that locking time is shorter, designs simplyr, under different process, transplant easily, but because quantization error is arranged, its jitter immunity is good not as analog D LL.
Digital dll can roughly be divided into four types: 1) register controlled DLL; The quantity of its locking time and delay unit is along with the quantity of control figure place increases and increases.2) counter controls DLL; It has replaced the register in the first kind with counter, thereby has reduced the hardware of controller, but its locking time is similar with the first kind with required delay unit number.3) successive approximation DLL; Successive approximation DLL can shorten locking time through binary search algorithm, but its frequency range is narrow.4) time numerical digit conversion hysteria DLL.Be the shortest in all digital dlls the locking time of time numerical digit conversion hysteria DLL, but it needs bigger chip area and power consumption, especially under the broadband condition.The locking time of register controlled DLL and the quantity of delay unit are along with the quantity of control figure place increases and increases; Counter controls DLL has then replaced register with counter; The frequency range of traditional counter controls DLL and register controlled DLL is wider; But its locking time is long, and PVT mistake can occur when changing greatly and locks phenomenon.
In order to satisfy the various characteristic in the different application, DLL must have bigger frequency range, more clock phase output, and to avoid occurring the error lock phenomenon.
Traditional counter controls DLL is as shown in Figure 1, and it comprises digital delay line, phase discriminator and adds/3 main modular of down counter.Digital delay line is made up of the individual identical delay unit of N (N is a natural number), and each delay unit is by the output signal controlling of counter, and phase discriminator compares the clock signal CK after input clock signal CLK and the time-delay
NPhase place, add/down counter according to comparative result control, thereby regulate the delay time of digital delay line, make that finally delay time is a clock cycle.
Shown in Figure 2 is that conventional counter is controlled DLL error lock waveform generation mechanism.CLK is an input clock signal, CK
1Be the clock signal through once delaying time, CK
2Be clock signal through twice time-delay, by that analogy, CK
NBe clock signal through N time-delay.Work as CK
NTime-delay also do not arrive or when having surpassed a clock cycle, again by add/control signal of down counter output increases or reduces the time-delay of a delay unit, and accomplish locking.Because locking process neither one testing mechanism, only signal CK is exported in comparator input signal CLK and final time-delay separately
NThe phase place situation, CK when this just can not confirm to accomplish locking
NTime-delay whether in satisfying the scope of locking condition, therefore just might form error lock.
Summary of the invention
It is narrower to The present invention be directed to the suitable frequency of conventional digital delay locked-loop circuit; The problem that occurs the mistake lock easily; Propose a kind of counter controls type digital delay phase-locked loop circuit that mechanism is corrected in error lock that has, changed traditional circuit structure, obtained wider frequency range; Avoided mistake to lock phenomenon, and multiphase clock output is provided.
According to technical scheme provided by the invention, said counter controls type delay locked-loop circuit with error lock mechanism of correcting comprises: digital delay line, phase discriminator, add/down counter, the clock phase computing circuit; Said digital delay line be input as input reference clock signal CLK, be output as the clock signal after the time-delay; Said digital delay line is made up of n+3 identical delay unit, and wherein n is a positive integer; Input reference clock signal CLK inserts digital delay line and phase discriminator respectively; The output of digital delay line is connected into phase discriminator and clock phase computing circuit; The output of phase discriminator is connected to and adds/input of down counter, add/output of down counter is connected into digital delay line; Each delay unit is by adding/the output signal controlling of down counter, and phase discriminator is the phase place of the clock signal after input reference clock signal CLK and the time-delay relatively, and control adds/down counter according to comparative result; Said clock phase computing circuit selects the delay clock signal of delay unit output to handle, the final required clock signal of output;
Locking process judges that through detection window whether the time-delay of the clock signal after the time-delay satisfies locking condition, avoids error lock; The size of said detection window for through clock signal C Kn and the CKn of n time-delay through the phase difference between 6 inverters clock signal C K ' n afterwards; Whether the clock signal C Kn that said detection window detects through n time-delay is in the detection window scope: the rising edge of the clock signal C Kn of n time-delay of process has exceeded the scope of detection window; The time-delay that delay unit is described is too much, and delay phase-locked loop can not lock; The rising edge of the clock signal C Kn of n time-delay of process does not also get into locking process detection window scope; CKn is in the detection window scope through the rising edge of the signal CK ' n after 6 inverters; The rising edge of the clock signal C Kn+3 of n+3 time-delay of process has exceeded the locking process detection window; Explain that then the time-delay of delay unit also is not enough to reach the locking condition of delay phase-locked loop, the state of delay phase-locked loop this moment for being about to lock, but can not accomplish locking at once; The rising edge of the clock signal C Kn of n time-delay of process is in the locking process detection window scope; CKn has surpassed the scope of locking process detection window through the rising edge of the clock signal C Kn+3 of signal CK ' n after 6 inverters and n+3 time-delay of process; Explain that the time-delay size of delay unit this moment has satisfied the locking condition of delay phase-locked loop, delay phase-locked loop is accomplished correct locking.
In said digital delay line, input reference clock signal CLK at first gets into first delay unit, output obtain through once the time-delay clock signal C K1; CK1 gets into second delay unit, and output obtains the clock signal C K2 through the secondary time-delay; And the like, n delay unit output obtains the clock signal C Kn through n time-delay, and last delay unit output obtains the clock signal C Kn+3 through n+3 time-delay.
In said digital delay line, each delay unit comprises: a buffer that composes in series by two reversers, and a time-delay load blocks that constitutes by capacitor array C0 ~ Cp and selector switch array K0 ~ Kp, wherein p is any positive integer; Said time-delay load blocks inside comprises p+1 load capacitance and p+1 selector switch; The climax plate of first electric capacity is connected to the lower end of first selector switch; The sole plate of first electric capacity is connected to ground, and the upper end of first selector switch is connected to the output of said buffer; The climax plate of second electric capacity is connected to the lower end of second selector switch, and the sole plate of second electric capacity is connected to ground, and the upper end of second selector switch is connected to the output of said buffer; And the like, the climax plate of p+1 electric capacity is connected to the lower end of p+1 selector switch, and the sole plate of p+1 electric capacity is connected to ground, and the upper end of p+1 selector switch is connected to the output of said buffer.
The process of locking is: successively relatively through the clock signal C Kn, CKn of n time-delay through the signal CK ' n after 6 inverters and through the phase place situation of clock signal C Kn+3 with the output signal CK1 of first delay unit of n+3 time-delay, control with this add/down counter adds 1, subtract 1 perhaps maintenance operate; When the time-delay of signal CKn, CK ' n and CKn+3 during all above a clock cycle, the time-delay of delay unit is too much, needs the Reduction of Students' Study Load live to hold, and counter subtracts 1 operation; When the time-delay of signal CKn, CK ' n and CKn+3 did not all surpass a clock cycle, the delay unit time-delay was not enough, if this moment, selector switch array K0 ~ Kp was all closed, counter keeps operation; If it is not closed that selector switch array K1 ~ Kp also has, counter adds 1 operation, continues to increase load capacitance; When signal CKn and CK ' n time-delay surpasses a clock cycle; When the time-delay of CKn+3 surpasses a clock cycle; Delay phase-locked loop is about to locking, if this moment, selector switch array K1 ~ Kp was all closed, counter keeps operation; If it is not closed that selector switch array K1 ~ Kp also has, counter adds 1 operation; Surpass a clock cycle when signal CKn delays time, when the time-delay of CK ' n and CKn+3 surpassed a clock cycle, the delay unit time-delay reached locking condition, and counter keeps operation, delay phase-locked loop completion locking.
Said phase discriminator comprises first phase discriminator, second phase discriminator and two divided-frequency clock circuit, and input reference clock signal CLK gets into said two divided-frequency clock circuit, and output obtains two divided-frequency clock signal clk 2; Two divided-frequency clock signal clk 2 inputs first phase discriminator is as the reset signal of first phase discriminator; Delay clock signal CKm, CKm+4 ..., CKn+2, CKn+3 insert first phase discriminator, as the clock signal in first phase discriminator, carry out phase demodulation through image data, and wherein m is greater than 1 positive integer less than n-1; The output signal CK1 of first delay unit, the output signal CKn of a n delay unit and CKn all insert second phase discriminator through the signal CK ' n after 6 inverters, by CK1 CKn and CK ' n are sampled, and produce identified result.
Said adding/down counter comprises: control signal generation circuit, p position add/subtract counting circuit and four frequency-dividing clock circuit; Said p position adds/subtracts counting circuit and comprises p position adder, register and the d type flip flop that connects successively; The output of phase discriminator is OUT as a result
PDBe input to said control signal generation circuit; Output obtains Y1, Y2, Y3, four main control signals of Y4 according to the combinational logic in the control signal generation circuit; Y1, Y2, Y3, these four signals of Y4 are input to the p position respectively and add/subtract in the counting circuit; Wherein Y1 connects the lowest order of p position adder addend; Importing of Y2 and p position adder with the low level carry that has determined p position adder jointly, Y3 control p position adds/subtracts the set end of counting circuit output, and Y4 connects all addends that p position adder is removed lowest order; Input reference clock signal CLK gets into four frequency-dividing clock circuit, and output obtains four sub-frequency clock signal CLK4; Four sub-frequency clock signal CLK4 insert d type flip flop, as the clock signal of d type flip flop; Finally add/this p of down counter output K1 ~ Kp control signal controls the switch arrays in the delay unit, and wherein p is any positive integer.
Beneficial effect of the present invention is: the present invention has the counter controls type delay locked-loop circuit that mechanism is corrected in error lock; Efficiently solve the problem that traditional DLL structure is locked easily by mistake; And wider frequency and more phase place output are arranged, help to improve chip yield.
Description of drawings
Fig. 1 is conventional counter control DLL structure chart.
Fig. 2 is conventional counter control DLL error lock waveform generation mechanism.
Fig. 3 is a counter controls DLL structure chart of the present invention.
Fig. 4 is a digital delay line structure chart of the present invention.
Fig. 5 is delay unit circuit theory diagrams of the present invention.
Fig. 6 is a phase detector circuit structure chart of the present invention.
Fig. 7 is a locking process detection window sketch map of the present invention.
Fig. 8 corrects schematic diagram for error lock of the present invention.Wherein Fig. 8 (a) is the locking process too much sequential chart of delaying time; Fig. 8 (b) claimed time-delay not enough sequential chart for locking; Fig. 8 (c) correctly locks sequential chart for locking process.
Fig. 9 is a forward-backward counter structure chart of the present invention.
Figure 10 is a locking process flow chart of the present invention.
Embodiment
For making technical characterictic of the present invention more obviously understandable, the present invention is described further below in conjunction with accompanying drawing and embodiment.
As shown in Figure 3, the structure with counter controls type delay locked-loop circuit of the error lock mechanism of correcting of the present invention comprises 4 functional modules: digital delay line 1, phase discriminator 2, add/down counter 3, clock phase computing circuit 4.Digital delay line 1 is made up of (n+3) individual identical delay unit; Wherein n is any positive integer; Each delay unit is by adding/the output signal controlling of down counter 3, and phase discriminator 2 is the phase place of the output clock after input clocks and the time-delay relatively, and control adds/down counter 3 according to comparative result; Clock phase computing circuit 4 selects the time delayed signal of some delay unit output to handle, and obtains final required clock signal.Circuit connecting relation is: input clock signal CLK inserts digital delay line 1 and phase discriminator 2 respectively; The output CLKOUT of digital delay line 1 is connected into phase discriminator 2 and clock phase computing circuit 4; The output of phase discriminator 2 is connected to the input of forward-backward counter 3, and the output of forward-backward counter 3 is connected into digital delay line 1.
As shown in Figure 4, digital delay line is the Executive Module of DLL among the DLL of the present invention, and it is made up of (n+3) individual identical delay unit, and wherein n is the unit number, can be any positive integer.Input reference clock signal CLK at first gets into first delay unit 11, output obtain through once the time-delay clock signal C K1; CK1 gets into second delay unit 12, and output obtains the clock signal C K2 through the secondary time-delay; And the like, n delay unit 1n output obtains the clock signal C Kn through n time-delay, and that last delay unit 1n+3 output obtains is the clock signal C Kn+3 through n+3 time-delay.Wherein preceding n delay unit is used to form the DLL loop, and last 3 delay units are used for assisting phase discriminator 2 to accomplish phase discrimination functions.
As shown in Figure 5, the circuit of delay unit of the present invention comprises 51, one the time-delay load blocks 52 that are made up of capacitor array C0 ~ Cp and selector switch array K0 ~ Kp of buffer that composed in series by two reversers 511,512, and wherein p can be any positive integer.Time-delay load blocks 52 is connected the output of buffer 51; This circuit through add/on off state of the control signal control selector switch array K1 ~ Kp of down counter output changes the size of the output load capacitance of buffer 51, thereby realize changing the time-delay characteristics of the clock signal of buffer 51.
Time-delay load blocks 52 inside comprise p+1 load capacitance and p+1 selector switch; Wherein, first capacitor C 0 is the pattern control capacitance, is used for adapting to the clock frequency of wide region; Capacitor C 1 ~ the Cp that depends merely on digital code control is difficult to satisfy the wide region requirement, has therefore increased C0.When DLL was operated in low-speed mode, the first selector switch K0 conducting was linked into big capacitor C 0 in the capacitor array, thereby in original time-delay, added a bigger time-delay.When fast mode, the first selector switch K0 breaks off.
The climax plate of first capacitor C 0 is connected to the lower end of the first selector switch K0, and the sole plate of first capacitor C 0 is connected to ground, and the upper end of the first selector switch K0 is connected to the output of buffer 51; The climax plate of second capacitor C 1 is connected to the lower end of the second selector switch K1, and the sole plate of second capacitor C 1 is connected to ground, and the upper end of the second selector switch K1 is connected to the output of buffer 51; Equally, the climax plate of i+1 capacitor C i is connected to the lower end of i+1 selector switch Ki, and the sole plate of i+1 capacitor C i is connected to ground, and the upper end of i+1 selector switch Ki is connected to the output of buffer 51, and i is greater than the 1 any positive integer less than p; The climax plate of p+1 capacitor C p is connected to the lower end of p+1 selector switch Kp, and the sole plate of p+1 capacitor C p is connected to ground, and the upper end of p+1 selector switch Kp is connected to the output of buffer 51.
As shown in Figure 6, phase discriminator of the present invention is made up of phase discriminator 21, phase discriminator 22 and two divided-frequency clock circuit 23.The identified result OUT of phase discriminator 21 and phase discriminator 22 outputs
PDAs adding/control signal of down counter.
Reference clock signal CLK receives the input of two divided-frequency clock circuit 23, and output obtains two divided-frequency clock signal clk 2; The output of two divided-frequency clock circuit is received the input of phase discriminator 21, and two divided-frequency clock signal clk 2 is as the reset signal of phase discriminator 21; Delay clock signal CKm, CKm+4 ..., CKn+2, CKn+3 also receive the input of phase discriminator 21, and as the clock signal of circuit, wherein m is greater than the 1 any positive integer less than n-1.Phase discriminator 21 carries out phase demodulation through image data, and whether the output signal CKn+3 that mainly is used for differentiating last delay unit time-delay of the output signal CK1 of first delay unit has relatively surpassed one-period.
The output signal CK1 of first delay unit, the output signal CKn of a n delay unit and CKn all receive the input of phase discriminator 22 through the signal CK ' n after 6 inverters, phase discriminator 22 through CK1 to CK
NAnd CK '
nSample, produce identified result, whether the output signal CKn that mainly is used for differentiating last n delay unit and CKn have surpassed one-period through the time-delay of the output signal CK1 of relative first delay unit of 6 inverters signal CK ' n afterwards.
Shown in Figure 7 is locking process detection window sketch map in the phase discriminator.Signal CKn is the clock signal through n time-delay, and signal CK ' n is that signal CKn is through the clock signal after 6 inverters.The phase difference of signal CKn and CK ' n is the size of locking process detection window.
Shown in Figure 8ly be that error lock of the present invention corrects principle.Shown in Fig. 8 (a); Through the clock signal C Kn of n time-delay, CKn has all surpassed the locking process detection window through the rising edge of the clock signal C Kn+3 of signal CK ' n after 6 inverters and n+3 time-delay of process scope; The time-delay of this explanation delay unit is too much; Need be reduced the time-delay of delay unit by the control signal of forward-backward counter output, this moment, DLL can not lock.Shown in Fig. 8 (b); The rising edge of the clock signal C Kn of n time-delay of process does not also get into locking process detection window scope; CKn is in the locking process detection window scope through the rising edge of the signal CK ' n after 6 inverters; The rising edge of the clock signal C Kn+3 of n+3 time-delay of process has exceeded the locking process detection window, and the time-delay of this explanation delay unit also is not enough to reach the locking condition of DLL, the time-delay that need continue to increase or keep delay unit this moment by the control signal of forward-backward counter output; So the state of DLL this moment, but can not accomplish locking at once for being about to lock.Shown in Fig. 8 (c); The rising edge of the clock signal C Kn of n time-delay of process is in the locking process detection window scope; CKn has then surpassed the scope of locking process detection window through the rising edge of the clock signal C Kn+3 of signal CK ' n after 6 inverters and n+3 time-delay of process; The time-delay size of delay unit has satisfied the locking condition of DLL at this moment, and DLL accomplishes correct locking.
Detection through the locking process detection window; Can judge accurately whether the time-delay of delay unit satisfies locking condition, and change the time-delay size of delay unit immediately, make it reach locking condition according to testing result; Accomplish correct locking, so this mechanism has effectively avoided mistake to lock phenomenon.
As shown in Figure 9, said adding/down counter comprises: control signal generation circuit 31, p position add/subtract counting circuit 32 and four frequency-dividing clock circuit 33.Said p position adds/subtracts counting circuit 32 and comprises p position adder 321, register 322 and the d type flip flop 323 that connects successively.The output of control signal generation circuit 31 is received the input of p position plus-minus counting circuit 32; The output of p position adder 321 is received the input of register 322 in the p position plus-minus counting circuit 32, and the output of the output of register 322 and four frequency-dividing clock circuit 33 is all received the input of d type flip flop 323.
The output of phase discriminator OUT as a result at first
PDBe input in the control signal generation circuit 31, obtain four main control signals of Y1 ~ Y4 according to a series of combinational logic output in the control signal generation circuit 31.These four signals of Y1 ~ Y4 are input to the p position respectively and add/subtract in the counting circuit 32, produce corresponding tally function so that the p position adds/subtract counting circuit 32.What wherein Y1 connect is the lowest order that the p position adds/subtract adder 321 addends in p position in the counting circuit 32; Importing of Y2 and p position adder 321 with the low level carry that has determined p position adder 321 jointly; Y3 control p position adds/subtracts the set end of counting circuit 32 outputs, and Y4 connects is that the p position adds/subtract all addends that p position adder 321 in the counting circuit 32 is removed lowest order.Input reference clock signal CLK gets into four frequency-dividing clock circuit 33, and output obtains four sub-frequency clock signal CLK4; Four sub-frequency clock signal CLK4 input p position adds/subtracts counting circuit 32, adds/subtract the clock signal of d type flip flop 323 in the counting circuit 32 as the p position.Add/the control signal K1 ~ Kp of down counter output directly is used for controlling the on off state of the selector switch array K1 ~ Kp of delay unit, and to change the size of delay capacitor, wherein p is any positive integer.
Shown in Figure 10 is locking process flow chart of the present invention.The locking process of this DLL adopts the sequential search algorithm; Successively relatively through the clock signal C Kn, CKn of n time-delay through the signal CK ' n after 6 inverters and through the phase place situation of clock signal C Kn+3 with the output signal CK1 of first delay unit of n+3 time-delay, control with this add/down counter adds 1, subtract 1 perhaps maintenance operate.
When the time-delay of signal CKn, CK ' n and CKn+3 during all above a clock cycle, the time-delay of delay unit is too much, needs the Reduction of Students' Study Load live to hold, and counter subtracts 1 operation; When the time-delay of signal CKn, CK ' n and CKn+3 does not all surpass a clock cycle; The delay unit time-delay is not enough; If this moment, selector switch array K1 ~ Kp was all closed, counter keeps operation, if selector switch array K1 ~ Kp also has not closed; Counter adds 1 operation, continues to increase load capacitance; When signal CKn and CK ' n time-delay surpasses a clock cycle; When the time-delay of CKn+3 surpasses a clock cycle; DLL is about to locking, if this moment, selector switch array K1 ~ Kp was all closed, counter keeps operation; If it is not closed that selector switch array K1 ~ Kp also has, counter adds 1 operation; Surpass a clock cycle when signal CKn delays time, when the time-delay of CK ' n and CKn+3 surpassed a clock cycle, the delay unit time-delay reached locking condition, and counter keeps operation, and DLL accomplishes locking.Through the sequential search algorithm, phase discriminator with add/delay lock that down counter has well been accomplished DLL together function mutually.
After DLL locked fully, this n of CK1 ~ CKn the signal after time-delay drew final needed clock signal P1 ~ Pa through the phase place computing circuit to after wherein some clock is handled, and wherein a is any positive integer.So this DLL finally can obtain a clock phase output signal.
Counter controls DLL of the present invention can be applicable to the multi-phase clock signal of the stable low jitter of generation in the large scale integrated circuit.
Claims (6)
1. have the counter controls type delay locked-loop circuit of the error lock mechanism of correcting, it is characterized in that: comprise digital delay line, phase discriminator, add/down counter, the clock phase computing circuit; Said digital delay line be input as input reference clock signal CLK, be output as the clock signal after the time-delay; Said digital delay line is made up of n+3 identical delay unit, and wherein n is a positive integer; Input reference clock signal CLK inserts digital delay line and phase discriminator respectively; The output of digital delay line is connected into phase discriminator and clock phase computing circuit; The output of phase discriminator is connected to and adds/input of down counter, add/output of down counter is connected into digital delay line; Each delay unit is by adding/the output signal controlling of down counter, and phase discriminator is the phase place of the clock signal after input reference clock signal CLK and the time-delay relatively, and control adds/down counter according to comparative result; Said clock phase computing circuit selects the delay clock signal of delay unit output to handle, the final required clock signal of output;
Locking process judges that through detection window whether the time-delay of the clock signal after the time-delay satisfies locking condition, avoids error lock; The size of said detection window for through clock signal C Kn and the CKn of n time-delay through the phase difference between 6 inverters clock signal C K ' n afterwards; Whether the clock signal C Kn that said detection window detects through n time-delay is in the detection window scope: the rising edge of the clock signal C Kn of n time-delay of process has exceeded the scope of detection window; The time-delay that delay unit is described is too much, and delay phase-locked loop can not lock; The rising edge of the clock signal C Kn of n time-delay of process does not also get into locking process detection window scope; CKn is in the detection window scope through the rising edge of the signal CK ' n after 6 inverters; The rising edge of the clock signal C Kn+3 of n+3 time-delay of process has exceeded the locking process detection window; Explain that then the time-delay of delay unit also is not enough to reach the locking condition of delay phase-locked loop, the state of delay phase-locked loop this moment for being about to lock, but can not accomplish locking at once; The rising edge of the clock signal C Kn of n time-delay of process is in the locking process detection window scope; CKn has surpassed the scope of locking process detection window through the rising edge of the clock signal C Kn+3 of signal CK ' n after 6 inverters and n+3 time-delay of process; Explain that the time-delay size of delay unit this moment has satisfied the locking condition of delay phase-locked loop, delay phase-locked loop is accomplished correct locking.
2. the counter controls type delay locked-loop circuit with error lock correction mechanism according to claim 1; It is characterized in that; In said digital delay line, input reference clock signal CLK at first gets into first delay unit, output obtain through once the time-delay clock signal C K1; CK1 gets into second delay unit, and output obtains the clock signal C K2 through the secondary time-delay; And the like, n delay unit output obtains the clock signal C Kn through n time-delay, and last delay unit output obtains the clock signal C Kn+3 through n+3 time-delay.
3. the counter controls type delay locked-loop circuit with error lock correction mechanism according to claim 2; It is characterized in that; In said digital delay line; Each delay unit comprises: a buffer that composes in series by two reversers, and a time-delay load blocks that constitutes by capacitor array C0 ~ Cp and selector switch array K0 ~ Kp, wherein p is any positive integer; Said time-delay load blocks inside comprises p+1 load capacitance and p+1 selector switch; The climax plate of first electric capacity (C0) is connected to the lower end of first selector switch (K0); The sole plate of first electric capacity (C0) is connected to ground, and the upper end of first selector switch (K0) is connected to the output of said buffer; The climax plate of second electric capacity (C1) is connected to the lower end of second selector switch (K1), and the sole plate of second electric capacity (C1) is connected to ground, and the upper end of second selector switch (K1) is connected to the output of said buffer; And the like, the climax plate of p+1 electric capacity (Cp) is connected to the lower end of p+1 selector switch (Kp), and the sole plate of p+1 electric capacity (Cp) is connected to ground, and the upper end of p+1 selector switch (Kp) is connected to the output of said buffer.
4. the counter controls type delay locked-loop circuit with error lock correction mechanism according to claim 1; It is characterized in that; The process of locking is: successively relatively through the clock signal C Kn, CKn of n time-delay through the signal CK ' n after 6 inverters and through the phase place situation of clock signal C Kn+3 with the output signal CK1 of first delay unit of n+3 time-delay, control with this add/down counter adds 1, subtract 1 perhaps maintenance operate; When the time-delay of signal CKn, CK ' n and CKn+3 during all above a clock cycle, the time-delay of delay unit is too much, needs the Reduction of Students' Study Load live to hold, and counter subtracts 1 operation; When the time-delay of signal CKn, CK ' n and CKn+3 did not all surpass a clock cycle, the delay unit time-delay was not enough, if this moment, selector switch array K0 ~ Kp was all closed, counter keeps operation; If it is not closed that selector switch array K1 ~ Kp also has, counter adds 1 operation, continues to increase load capacitance; When signal CKn and CK ' n time-delay surpasses a clock cycle; When the time-delay of CKn+3 surpasses a clock cycle; Delay phase-locked loop is about to locking, if this moment, selector switch array K1 ~ Kp was all closed, counter keeps operation; If it is not closed that selector switch array K1 ~ Kp also has, counter adds 1 operation; Surpass a clock cycle when signal CKn delays time, when the time-delay of CK ' n and CKn+3 surpassed a clock cycle, the delay unit time-delay reached locking condition, and counter keeps operation, delay phase-locked loop completion locking.
5. the counter controls type delay locked-loop circuit with error lock correction mechanism according to claim 1; It is characterized in that; Said phase discriminator comprises first phase discriminator, second phase discriminator and two divided-frequency clock circuit; Input reference clock signal CLK gets into said two divided-frequency clock circuit, and output obtains two divided-frequency clock signal clk 2; Two divided-frequency clock signal clk 2 inputs first phase discriminator is as the reset signal of first phase discriminator; Delay clock signal CKm, CKm+4 ..., CKn+2, CKn+3 insert first phase discriminator, as the clock signal in first phase discriminator, carry out phase demodulation through image data, and wherein m is greater than 1 positive integer less than n-1; The output signal CK1 of first delay unit, the output signal CKn of a n delay unit and CKn all insert second phase discriminator through the signal CK ' n after 6 inverters, by CK1 CKn and CK ' n are sampled, and produce identified result.
6. the counter controls type delay locked-loop circuit with error lock correction mechanism according to claim 1, it is characterized in that said adding/down counter comprises: control signal generation circuit, p position add/subtract counting circuit and four frequency-dividing clock circuit; Said p position adds/subtracts counting circuit and comprises p position adder, register and the d type flip flop that connects successively; The output of phase discriminator is OUT as a result
PDBe input to said control signal generation circuit; Output obtains Y1, Y2, Y3, four main control signals of Y4 according to the combinational logic in the control signal generation circuit; Y1, Y2, Y3, these four signals of Y4 are input to the p position respectively and add/subtract in the counting circuit; Wherein Y1 connects the lowest order of p position adder addend; Importing of Y2 and p position adder with the low level carry that has determined p position adder jointly, Y3 control p position adds/subtracts the set end of counting circuit output, and Y4 connects all addends that p position adder is removed lowest order; Input reference clock signal CLK gets into four frequency-dividing clock circuit, and output obtains four sub-frequency clock signal CLK4; Four sub-frequency clock signal CLK4 insert d type flip flop, as the clock signal of d type flip flop; Finally add/this p of down counter output K1 ~ Kp control signal controls the switch arrays in the delay unit, and wherein p is any positive integer.
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