CN103441757B - Leggy delay phase-locked loop and control method thereof - Google Patents
Leggy delay phase-locked loop and control method thereof Download PDFInfo
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Abstract
The invention discloses a kind of leggy delay phase-locked loop and control method thereof.Wherein, leggy delay phase-locked loop comprises: delay unit, has multiple delay cell, for exporting multiphase clock; Search parts, be all connected with multiple delay cell, for finding target delay unit; And control assembly, and search parts and multiple delay cell is all connected, for receiving the target delay unit searched parts and send, increase time of delay of target delay unit and control lag component working under the second mode; Also for obtaining the maximum delay time of delay unit, if maximum delay time does not reach the clock cycle of clock signal of system, control lag component working in the flrst mode otherwise control lag parts export multiphase clock.By the present invention, solve the problem that in prior art, leggy delay phase-locked loop output clock phase precision is low, and then reach the effect improving leggy output clock phase precision.
Description
Technical Field
The invention relates to the field of clock circuits, in particular to a multi-phase delay phase-locked loop and a control method thereof.
Background
Delay-locked loop circuits are widely used in high-speed circuitry for generating multi-phase clocks. The multiphase delay locked loop can generate N output clocks CK1, CK2 and CK3 … CKN with the same frequency according to one input clock, and the N output clocks have an equally-spaced phase relationship (N is an integer and is generally 4, 8, 16 and the like). Therefore, the function of the multiphase delay locked loop can be defined as: generating N output clocks according to the input clock, wherein the phase difference between the N output clocks is
The related art discloses a four-phase clock generating circuit, which adopts the structure shown in fig. 1 and mainly comprises four numerical control delay chains in series connection, a control circuit is connected with the four numerical control delay chains and a phase discriminator, the phase discriminator is connected with a clock signal input end of the four-phase clock generating circuit and an output end of a maximum clock, and the four-phase clock generating circuit has the following main working principle: (1) an input clock passes through four stages of same digital control delay chains to obtain an output clock; (2) the phase relation of the output clock CK4 and the input clock is judged in the phase discriminator; (3) the control logic adjusts the delay time of the numerical control delay chain by using the delay control code according to the phase judgment result. Because the four numerical control delay chains all use a group of control codes, the delay time of the four numerical control delay chains is synchronously changed; (4) repeating the steps (2) and (3) to finally obtain an output clock CK4 with the input clock with a phase relation of 360 degrees, which is equivalent to that the output clock CK4 delays relative to the input clock by one period after passing through the delay chain, and at the moment, the locking state is achieved; (5) in the locked state, four-phase clocks CK1 to CK4 shown in fig. 2 are output with phase relationships of 90 °, 180 °, 270 °, and 360 °.
For the four-phase clock generation circuit, due to factors such as process deviation, it cannot be guaranteed that the four numerical control delay chains are absolutely identical after the chip is produced. Therefore, although their delay control codes are the same, their respective delay times are not the same. When the delay locked loop finishes locking, the total delay time of the four delay chains is equal to one clock cycle, but the delay time of each chain is not exactly equal to one quarter of the clock cycle, so that the four-phase output clock is not exactly in an equally spaced phase relationship. Therefore, the circuit structure cannot tolerate the negative influence caused by process deviation, and fine process deviation can cause the phase precision of the output clock of the delay phase-locked loop to be reduced.
Aiming at the problem of low phase precision of an output clock of a multi-phase delay phase-locked loop in the related technology, an effective solution is not provided at present.
Disclosure of Invention
The invention mainly aims to provide a multi-phase delay locked loop and a control method thereof, and aims to solve the problem that the output clock phase precision of the multi-phase delay locked loop in the prior art is low.
To achieve the above object, according to an aspect of the present invention, there is provided a multiphase delay locked loop comprising: a delay unit having a plurality of delay cells with controllable delay time, and having a first mode in which clock signals of the plurality of delay cells are all from a system clock signal of the multiphase delay phase locked loop and a second mode in which the plurality of delay cells are cascaded, the delay unit being configured to output the multiphase clock in the second mode; the searching part is connected with the plurality of delay units, and is used for searching a target delay unit from the plurality of delay units when the delay part is in the first mode, wherein the target delay unit is the delay unit with the minimum delay time in the plurality of delay units; the control part is connected with the searching part and the plurality of delay units of the delay part, and is used for receiving the target delay unit sent by the searching part, increasing the delay time of the target delay unit and controlling the delay part to work in a second mode when the delay part is in the first mode; and when the delay unit is in the second mode, the control unit is further configured to obtain the maximum delay time of the delay unit, and if the maximum delay time does not reach the clock period of the system clock signal, control the delay unit to operate in the first mode, otherwise control the delay unit to output the multi-phase clock.
Further, the delay unit has a mode selector for receiving a mode control signal to place the delay unit in the first mode or the second mode.
Further, the number of delay units is N, and the mode selector comprises a number C1To CNThe N double-path selectors are respectively and correspondingly arranged in the N delay units, the control ends of the N double-path selectors are all used for receiving mode control signals, and the first input ports of the N double-path selectors and the double-path selector C1The second input ports of the first and second input ports are all used for receiving system clock signals; the delay member also has the number D1To DNThe N number-controlled delay chains are respectively and correspondingly arranged in the N delay unitsControlled delay chain DiInput terminal and two-way selector CiAre connected to the output of the digital controlled delay chain DiOutput terminal and two-way selector Ci+1Is connected with the second input port of the digital control delay chain DNInput terminal and two-way selector CNThe output ends of the two-way valves are connected, i is 1 to N-1, and N is a natural number more than 2.
Further, the number of delay cells is N, N is a natural number of 2 or more, and the search means includes: n input ends of the first N-path selector are respectively and correspondingly connected with N delay units; n input ends of the second N-path selector are respectively and correspondingly connected with N delay units; the phase comparator is connected with the output end of the first N-way selector and the output end of the second N-way selector at the input end, and is used for comparing the delay time of the first delay unit and the delay time of the second delay unit according to a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, the first delay unit is a delay unit for generating the first output clock, the second output clock is the output clock received by the input end gated by the second N-way selector, and the second delay unit is a delay unit for generating the second output clock; and the clock selector, the input end is connected with carry-out terminal of the phase comparator, the carry-out terminal is connected with control end of the first N way selector and control end of the second N way selector, used in under the situation that the delay time of the first delay cell is smaller than the delay time of the second delay cell, change the input end that the second N way selector strobes, until confirming the goal delay cell, or under the situation that the delay time of the first delay cell is greater than the delay time of the second delay cell, change the input end that the first N way selector strobes, until confirming the goal delay cell.
Further, the number of delay cells is N, N is a natural number of 2 or more, and the search means includes: n input ends of the first N-path selector are respectively and correspondingly connected with N delay units; n input ends of the second N-path selector are respectively and correspondingly connected with N delay units; the phase comparator is connected with the output end of the first N-way selector and the output end of the second N-way selector at the input end, and is used for comparing the delay time of the first delay unit and the delay time of the second delay unit according to a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, the first delay unit is a delay unit for generating the first output clock, the second output clock is the output clock received by the input end gated by the second N-way selector, and the second delay unit is a delay unit for generating the second output clock; and the clock selector, the input end is connected with carry-out terminal of the phase comparator, the carry-out terminal is connected with control end of the first N way selector and control end of the second N way selector, used in under the situation that the delay time of the first delay cell is smaller than the delay time of the second delay cell, change the input end that the second N way selector strobes, until confirming the delay cell of the goal, or under the situation that the delay time of the first delay cell is greater than the delay time of the second delay cell, change the input end that the first N way selector strobes as the input end that the second N way selector strobes at present, then change the input end that the second N way selector strobes, until confirming the delay cell of the goal.
Further, the phase comparator includes: the data input end is connected with the output end of the first N-path selector and used for receiving a first output clock; the clock input end is connected with the output end of the second N-path selector and used for receiving a second output clock; and a sampling output terminal connected with the clock selector for sampling the first output clock under the trigger of the second output clock and outputting a sampling signal of 0 or 1, wherein, if the sampling output end samples the first output clock at the rising edge of the second output clock, the clock selector determines that the delay time of the first delay cell is greater than the delay time of the second delay cell when receiving the sampling signal 0, when the sampling signal 1 is received, the delay time of the first delay unit is determined to be less than that of the second delay unit, if the sampling output end samples the first output clock at the falling edge of the second output clock, the clock selector determines that the delay time of the first delay cell is greater than the delay time of the second delay cell upon receiving the sampling signal 1, upon receiving the sampling signal 0, it is determined that the delay time of the first delay unit is less than the delay time of the second delay unit.
In order to achieve the above object, according to another aspect of the present invention, there is provided a control method for a multi-phase delay locked loop, applied to a multi-phase delay locked loop having a delay section, wherein the delay section includes a plurality of delay units with controllable delay times, and has a first mode and a second mode, wherein clock signals of the plurality of delay units are all from a system clock signal of the multi-phase delay locked loop in the first mode, and the plurality of delay units are cascaded in the second mode, the control method comprising: when the delay part is in the first mode, searching a target delay unit from the plurality of delay units, wherein the target delay unit is the delay unit with the minimum delay time in the plurality of delay units; increasing the delay time of the target delay cell and controlling the delay unit to operate in the second mode; acquiring the maximum delay time of the delay part in the second mode; and if the maximum delay time does not reach the clock period of the system clock signal, controlling the delay unit to work in the first mode, otherwise, controlling the delay unit to output the multi-phase clock.
Further, the control method further comprises: after initializing the delay means, the delay means is controlled to operate in the first mode.
Further, the initialization delay unit includes: the delay time control codes controlling the plurality of delay units are all set to zero.
Further, increasing the delay time of the target delay cell includes: one is added to the delay time control code of the target delay cell.
Furthermore, the number of the delay units is N, N is a natural number greater than 2, the multiphase delay locked loop further includes a first N-way selector and a second N-way selector, N input ends of the first N-way selector are respectively and correspondingly connected to N delay units, N input ends of the second N-way selector are respectively and correspondingly connected to N delay units, and finding the delay unit with the minimum delay time among the plurality of delay units includes: acquiring a first output clock and a second output clock, wherein the first output clock is received by an input end gated by a first N-way selector, and the second output clock is received by an input end gated by a second N-way selector; comparing delay times of a first delay unit and a second delay unit according to a first output clock and a second output clock, wherein the first delay unit is a delay unit for generating the first output clock, and the second delay unit is a delay unit for generating the second output clock; under the condition that the delay time of the first delay unit is smaller than that of the second delay unit through comparison, the gated input end of the second N-path selector is changed, and a second output clock is obtained again until a target delay unit is determined; and under the condition that the delay time of the first delay unit is greater than that of the second delay unit, changing the gated input end of the first N-path selector, and reacquiring the first output clock until the target delay unit is determined.
Furthermore, the number of the delay units is N, N is a natural number greater than 2, the multiphase delay locked loop further includes a first N-way selector and a second N-way selector, N input ends of the first N-way selector are respectively and correspondingly connected to N delay units, N input ends of the second N-way selector are respectively and correspondingly connected to N delay units, and finding the delay unit with the minimum delay time among the plurality of delay units includes: acquiring a first output clock and a second output clock, wherein the first output clock is received by an input end gated by a first N-way selector, and the second output clock is received by an input end gated by a second N-way selector; comparing delay times of a first delay unit and a second delay unit according to a first output clock and a second output clock, wherein the first delay unit is a delay unit for generating the first output clock, and the second delay unit is a delay unit for generating the second output clock; under the condition that the delay time of the first delay unit is smaller than that of the second delay unit through comparison, the gated input end of the second N-path selector is changed, and a second output clock is obtained again until a target delay unit is determined; and under the condition that the delay time of the first delay unit is greater than that of the second delay unit, changing the input end gated by the first N-way selector to be the input end currently gated by the second N-way selector, then changing the input end gated by the second N-way selector, and reacquiring the first output clock and the second output clock until the target delay unit is determined.
Further, comparing the delay times of the first delay unit and the second delay unit according to the first output clock and the second output clock includes: sampling the first output clock at a rising edge of the second output clock; if sampling is carried out to obtain a sampling signal 0, determining that the delay time of the first delay unit is greater than that of the second delay unit; and if sampling to obtain a sampling signal 1, determining that the delay time of the first delay unit is less than that of the second delay unit.
Further, comparing the delay times of the first delay unit and the second delay unit according to the first output clock and the second output clock includes: sampling the first output clock at a falling edge of the second output clock; if sampling is carried out to obtain a sampling signal 1, determining that the delay time of the first delay unit is greater than that of the second delay unit; and if the sampling signal 0 is obtained by sampling, determining that the delay time of the first delay unit is less than that of the second delay unit.
The invention adopts a multiphase delay phase-locked loop comprising the following structures: a delay unit having a plurality of delay cells with controllable delay time, and having a first mode in which clock signals of the plurality of delay cells are all from a system clock signal of the multiphase delay phase locked loop and a second mode in which the plurality of delay cells are cascaded, the delay unit being configured to output the multiphase clock in the second mode; the searching part is connected with the plurality of delay units, and is used for searching a target delay unit from the plurality of delay units when the delay part is in the first mode, wherein the target delay unit is the delay unit with the minimum delay time in the plurality of delay units; the control part is connected with the searching part and the plurality of delay units of the delay part, and is used for receiving the target delay unit sent by the searching part, increasing the delay time of the target delay unit and controlling the delay part to work in a second mode when the delay part is in the first mode; and when the delay unit is in the second mode, the control unit is further configured to obtain the maximum delay time of the delay unit, and if the maximum delay time does not reach the clock period of the system clock signal, control the delay unit to operate in the first mode, otherwise control the delay unit to output the multi-phase clock. By arranging the searching part, the control part and the delay units with controllable delay time, the delay time of each delay unit in the delay part is regulated and controlled by increasing the delay time of the target delay unit, so that the delay time of each delay unit is ensured to be equal to the maximum extent, the output multi-phase clock has an equal interval phase relationship, the problem of low phase precision of the output clock of the multi-phase delay phase-locked loop in the prior art is solved, and the effect of improving the phase precision of the multi-phase output clock is further achieved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram of a four-phase clock generation circuit according to the related art;
FIG. 2 is a graph of the phase relationship of the output clocks of the four-phase clock generation circuit of FIG. 1;
FIG. 3 is a schematic diagram of a multi-phase delay locked loop according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a delay unit in a multiphase delay phase locked loop according to an embodiment of the present invention;
FIGS. 5 and 6 are schematic diagrams of the delay element of FIG. 4 in different modes of operation;
FIG. 7 is a schematic diagram of the operation of the control unit in the multiphase delay phase locked loop according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a specific structure of a delay unit in a multiphase delay phase-locked loop according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of the configuration of the dual path selector of FIG. 8;
FIG. 10 is a schematic diagram of the structure of the digitally controlled delay chain of FIG. 8;
FIG. 11 is a schematic diagram of a lookup unit in a multiphase delay-locked loop according to an embodiment of the present invention;
FIG. 12a is a schematic diagram of the structure of the phase comparator of FIG. 11;
FIGS. 12b and 12c are timing diagrams of the output of the phase comparator of FIG. 12 a;
FIG. 13 is a schematic diagram of the operation of the clock selector of FIG. 11;
FIG. 14 is a flow chart of a control method of a multiphase delay locked loop according to an embodiment of the present invention; and
fig. 15 is a flowchart of a control method of a multiphase delay locked loop according to a preferred embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
The embodiment of the invention provides a multi-phase delay locked loop, which is specifically introduced as follows:
fig. 3 is a schematic diagram of a multi-phase delay locked loop according to an embodiment of the present invention, and as shown in fig. 3, the multi-phase delay locked loop of the embodiment of the present invention mainly includes a delay unit, a search unit, and a control unit. Wherein,
the delay component has a plurality of delay units with controllable delay time, and has a calibration operation mode (also referred to as a first mode) and a normal operation mode (also referred to as a second mode), wherein in the first mode, the clock signals of the plurality of delay units are all from the system clock signal of the multi-phase delay phase-locked loop, in the second mode, the plurality of delay units are cascaded, the delay component is used for outputting the multi-phase clock in the second mode, namely, in the first mode, the input clock of each delay unit is the system clock signal, and in the second mode, the multi-phase delay phase-locked loop outputs the multi-phase clock through the plurality of delay units with controllable delay time.
A searching unit, connected to the plurality of delay units, for searching a target delay unit from the plurality of delay units when the delay unit is in the first mode, where the target delay unit is a delay unit with the smallest delay time among the plurality of delay units, and assuming that the number of the plurality of delay units is N, N is a natural number greater than 2, and the current delay times of the N delay units are tdelay[1]、tdelay[2]、tdelay[3]…tdelay[N]Then, the searching component for searching the target delay unit finds an integer m less than or equal to N, so that the delay time of the mth delay unit satisfies the following condition:
tdelay[m]＝MIN{tdelay[1]、tdelay[2]、tdelay[3]…tdelay[N]}。
the searching part searches the target delay unit, and can compare the phases of the output clocks CK [0] to CK [ N ] of the N delay units, judge the relationship of the delay time among the N delay units according to the phase comparison result, and finally find the delay unit with the minimum delay time.
The control part is connected with the searching part and the plurality of delay units of the delay part, and when the delay part is in the first mode, the control part is used for receiving the target delay unit sent by the searching part, increasing the delay time of the target delay unit and controlling the delay part to work in the second mode; and when the delay unit is in the second mode, the control unit is further configured to obtain the maximum delay time of the delay unit, and if the maximum delay time does not reach the clock period of the system clock signal, control the delay unit to operate in the first mode, otherwise control the delay unit to output the multi-phase clock.
According to the multi-phase delay phase-locked loop provided by the embodiment of the invention, by arranging the searching part, the control part and the delay unit with controllable delay time, the delay time of each delay unit in the delay part is regulated and controlled in a mode of increasing the delay time of the target delay unit, so that the delay time of each delay unit is ensured to be equal to the maximum extent, the output multi-phase clock has an equally spaced phase relation, the problem of low phase precision of the output clock of the multi-phase delay phase-locked loop in the prior art is solved, and the effect of improving the phase precision of the multi-phase output clock is further achieved.
Specifically, fig. 4 shows a schematic structure diagram of the delay unit, and as shown in fig. 4, the delay unit is formed by cascading N stages of delay units, and mainly functions to perform time delay on an input clock and output a multi-phase clock, where N is an integer and is generally 4, 8, 16 or more. Fig. 5 and fig. 6 show the connection relationship of the plurality of delay units corresponding to two operation modes of the delay unit, as shown in fig. 5: when the MODE control signal MODE is 0, the delay unit enters a normal operating MODE, all the delay units select to delay the output clock of the previous stage of delay unit, that is, all the delay units are cascaded together for use, and when N is 4, the system outputs a four-phase clock; when N is 8, the system outputs an eight-phase clock; when N is 16, the system outputs a sixteen-phase clock. As shown in fig. 6: when the MODE control signal MODE is 1, the delay unit enters the calibration operation MODE, and all the delay units directly delay the system input clock, that is, all the delay units are used independently. The calibration mode of operation of the delay unit ensures that the input signals of all delay cells are from the same clock, so that the current delay time of the delay cells can be compared.
As can be seen from the above description, the control component is a component responsible for the working timing sequence of the entire multi-phase delay locked loop, wherein the control of the delay component in the multi-phase delay locked loop by the control component is not limited to the control manner provided in the following embodiments of the present invention:
in an embodiment of the invention, the control part mainly uses a locking algorithm with a calibration function to complete 360-degree phase locking of the clock, so that accurate output of the multi-phase clock is ensured. The operation steps of the locking algorithm with the calibration function are shown in FIG. 7: firstly, initializing a system, namely clearing all delay time control CODEs (CODEs), namely, setting the delay time control CODEs of N delay units to zero; secondly, setting the delay component to enter a calibration working MODE, namely outputting a MODE control signal MODE equal to 1 to each delay unit; thirdly, finding a target delay unit through a searching component; step four, increasing the delay time control CODE of the target delay unit by one, namely increasing the delay time of the target delay unit; fifthly, setting the delay unit to enter a normal working MODE, namely outputting a MODE control signal MODE equal to 0 to each delay unit; and sixthly, judging whether the maximum delay time of the delay part reaches one clock cycle, if so, entering a seventh step to output an N-phase clock, and if not, repeatedly executing the second step to the sixth step.
Further, in the multi-phase delay locked loop provided in the embodiment of the present invention, each delay unit in the delay component has a MODE selector, the control component controls the operating MODE of the delay component by outputting a MODE control signal to the MODE selector, that is, controls the operating MODE of the multi-phase delay locked loop, when the MODE selector receives the MODE control signal MODE ═ 1, the clock signals of the plurality of delay units are all from the system clock signals of the multi-phase delay locked loop, and the multi-phase delay locked loop is in the calibration operating MODE; when the MODE selector receives the MODE control signal MODE ═ 0, all the delay units select to delay the output clock of the previous stage of delay unit, that is, all the delay units are cascaded together for use, and the multiphase delay phase-locked loop is in a normal working MODE. Fig. 8 shows a delay unit mainly composed of a 2:1 two-way selector and a digitally controlled delay chain, and as shown in fig. 8, the number of delay units is still specified as N:
number C1To CNThe N double-path selectors are respectively and correspondingly arranged in the N delay units, the control ends of the N double-path selectors are all used for receiving mode control signals, and the first input ports of the N double-path selectors and the double-path selector C1The 2:1 two-way selector selects the input signal of the first input port or the second input port as an output signal according to the MODE signal. Number D1To DNThe N numerical control delay chains are respectively and correspondingly arranged in the N delay units, and the numerical control delay chain DiInput terminal and two-way selector CiAre connected to the output of the digital controlled delay chain DiOutput terminal and two-way selector Ci+1Is connected with the second input port of the digital control delay chain DNInput terminal and two-way selector CNIs connected, i is 1 to N-1.
Fig. 9 shows an implementation of a 2:1 dual-way selector in the embodiment of the present invention, which is mainly formed by three nand gates and one inverter, wherein an input end of the inverter 91 is used for receiving a mode control signal, one input end of the nand gate 92 is used as an input port of the dual-way selector, another input end of the nand gate 92 is connected to an output end of the inverter 91, one input end of the nand gate 93 is used as another input port of the dual-way selector, another input end of the nand gate 93 is used for receiving the mode control signal, one input end of the nand gate 94 is connected to an output end of the nand gate 92, another input end of the nand gate 94 is connected to an output end of the nand gate 93, and an output end. When the MODE is equal to 0, a 2:1 two-way selector gates a port 0 signal to be input into the numerical control delay chain, and the port 0 is connected with an output clock of a previous stage delay unit, so that the delay component enters a normal working MODE; when MODE is 1, the 2:1 two-way selector gates the port 1 signal into the digitally controlled delay chain, and the delay unit enters the calibration MODE of operation because port 1 receives the system clock signal.
As can be seen from the above description, for a delay section mainly composed of N stages of delay cells, in which the delay time t of each delay celldelayCan be calculated with the following formula:
tdelay＝to+tstep*CODE
wherein, toDenotes the inherent delay time of the delay unit, tstepIndicating the delay time accuracy of the delay unit, and CODE is the delay time control CODE of the delay unit. When CODE is increased by 1, the delay time is correspondingly increased by tstep(ii) a Otherwise, the delay time is correspondingly reduced by one tstep. When the delay locked loop is locked, the total delay time of the delay part is tdelay[1]+tdelay[2]+…+tdelay[N]T (T represents one clock cycle), therefore, the delay time of the delay unit can be adjusted by changing the delay time control CODE used for controlling the number of the minimum delay components of the digitally controlled delay chain in the delay unit, the embodiment of the present invention provides a digitally controlled delay chain as shown in fig. 10, which is composed of a plurality of switchable capacitors connected in parallel and two stages of inverters, each stage of inverter is connected with a plurality of switchable capacitors connected in parallel, when the delay time of the delay unit is increased, the number of the closed capacitors is increased by increasing the delay time control CODE, so as to increase the delay time of the delay unit, otherwise, the number of the closed capacitors is decreased by decreasing the delay time control CODE, so as to decrease the delay time of the delay unitThe delay time, namely, the effect of changing the delay time is achieved by changing the number of load capacitors of the inverter by changing the CODE.
One implementation of the lookup component in the embodiment of the invention is shown in FIG. 11, as shown in FIG. 11:
the find component is mainly composed of two N: the system comprises a 1 multiplexer, a phase comparator and a clock selector, wherein N input ends of a first N:1 multiplexer are respectively and correspondingly connected with N delay units to select and output an output clock of a certain delay unit, N input ends of a second N:1 multiplexer are also respectively and correspondingly connected with N delay units to select and output an output clock of another delay unit, and the N:1 multiplexer can be constructed by N-1 2:1 multiplexers.
The input end of the phase comparator is connected with the output end of the first N-way selector and the output end of the second N-way selector, for comparing delay times of the first delay unit and the second delay unit based on the first output clock CK m and the second output clock CK n, wherein the first output clock CK m is the output clock received by the input end gated by the first N-way selector, the first delay unit is the delay unit generating the first output clock, the second output clock CK N is the output clock received by the input end gated by the second N-way selector, the second delay unit is the delay unit generating the second output clock, that is, two output clocks CK [ m ] and CK [ N ] are selected from the N output clocks of the delay section as inputs to the phase comparator (m, N is an integer equal to or less than N). One embodiment of a phase comparator is shown in fig. 12a, as shown in fig. 12a, the phase comparator is implemented by using a flip-flop, a data input terminal of the flip-flop is connected with an output terminal of the first N-way selector for receiving the first output clock, a clock input terminal of the flip-flop is connected with an output terminal of the second N-way selector for receiving the second output clock, a sampling output terminal of the flip-flop is connected with the clock selector for sampling the first output clock under the trigger of the second output clock and outputting a sampling signal 0 or 1, wherein if the first output clock is sampled at the rising edge of the second output clock, then a sampling signal 1 (i.e. a high level "1") is received, which indicates that the first output clock phase leads the second output clock phase, as shown in fig. 12b, this situation determines that the delay time of the first delay unit is less than the delay time of the second delay unit, when the sampling signal 0 (i.e., low level "0") is received, it indicates that the second output clock phase leads the first output clock phase, as shown in fig. 12c, which determines that the delay time of the first delay unit is greater than that of the second delay unit. Accordingly, if the first output clock is sampled at the falling edge of the second output clock, the delay time of the first delay unit is determined to be greater than the delay time of the second delay unit when the sampling signal 1 is received, and the delay time of the first delay unit is determined to be less than the delay time of the second delay unit when the sampling signal 0 is received.
In the embodiment of the present invention, the working principle of the clock selector includes, but is not limited to, the following two modes:
principle one is as follows: the clock selector changes the input end gated by the second N-path selector, namely changes the specific value of N until the target delay unit is determined under the condition that the delay time of the first delay unit is smaller than that of the second delay unit, or changes the input end gated by the first N-path selector, namely changes the specific value of m until the target delay unit is determined under the condition that the delay time of the first delay unit is larger than that of the second delay unit.
Principle two: the clock selector changes the input end gated by the second N-path selector, namely changes the specific value of N, until the target delay unit is determined under the condition that the delay time of the first delay unit is less than that of the second delay unit, or changes the input end gated by the first N-path selector to be the current gated input end of the second N-path selector and then changes the input end gated by the second N-path selector under the condition that the delay time of the first delay unit is greater than that of the second delay unit, namely changes the original value of m to the original value of N and then changes the value of N.
For the case of sampling the first output clock at the rising edge of the second output clock, fig. 13 shows a specific operation procedure of the clock selector according to the second principle, as shown in fig. 13, the clock selector starts to compare from the delay unit with the smallest code, default m is 1, default n is 2, and the clock requiring phase comparison next time is selected according to the phase comparison result of each time, case # 1: if CK [ m ] leads CK [ n ], it means that the delay unit [ m ] is shorter than the delay unit [ n ], and then CK [ m ] remains unchanged, CK [ n ] becomes the delay unit clock CK [ n +1] to be compared subsequently. Case 2 #: if the CK [ m ] phase lags behind CK [ n ], it means that the delay unit [ n ] is shorter than the delay time of the delay unit [ m ], and then CK [ m ] is changed into CK [ n ] and CK [ n ] is changed into the delay unit clock CK [ n +1] to be compared subsequently. No matter in case 1# or 2#, the CK [ m ] clock is always kept as the output clock of the delay unit with smaller delay time, so that CK [ m ] is the output clock of the delay unit with the smallest delay time after all phases are compared, and the mth delay unit is the searched target delay unit.
The present invention further provides a control method for a multi-phase delay locked loop, which is mainly used for controlling the multi-phase delay locked loop provided in the foregoing embodiments of the present invention, that is, the control method is applied to a multi-phase delay locked loop having a delay component, wherein the delay component includes a plurality of delay units with controllable delay time and has a first mode and a second mode, wherein in the first mode, clock signals of the plurality of delay units are all derived from system clock signals of the multi-phase delay locked loop, and in the second mode, the plurality of delay units are cascaded. The multiphase delay locked loop provided by the embodiment of the invention is specifically introduced as follows:
fig. 14 is a flowchart of a control method of a multi-phase delay locked loop according to an embodiment of the present invention, and as shown in fig. 14, the control method of the multi-phase delay locked loop according to the embodiment of the present invention includes steps S141 to S144 as follows:
s141: when the delay unit is in the first mode, a target delay unit is found from the plurality of delay units, and the target delay unit is the delay unit with the smallest delay time in the plurality of delay units.
Specifically, with the number of delay units being N (N is a natural number greater than 2), the multiphase delay locked loop includes a first N-way selector and a second N-way selector, where N input ends of the first N-way selector are respectively and correspondingly connected to N delay units, and N input ends of the second N-way selector are respectively and correspondingly connected to N delay units, which is taken as an example, the method for finding the target delay unit in step S141 is specifically described, where the finding method mainly determines the target delay unit by performing two-to-two comparison on a plurality of delay units, and may be implemented by, but not limited to, the following two ways:
the first method is as follows:
and acquiring a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, and the second output clock is the output clock received by the input end gated by the second N-way selector.
And comparing the delay time of a first delay unit and a second delay unit according to the first output clock and the second output clock, wherein the first delay unit is a delay unit for generating the first output clock, and the second delay unit is a delay unit for generating the second output clock.
Under the condition that the delay time of the first delay unit is smaller than that of the second delay unit, the gated input end of the second N-path selector is changed, a second output clock is obtained again until all the delay units are compared, and a target delay unit is determined; and
and under the condition that the delay time of the first delay unit is greater than that of the second delay unit, changing the gated input end of the first N-path selector, and reacquiring the first output clock until all the delay units are compared to determine the target delay unit.
The second method comprises the following steps:
and acquiring a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, and the second output clock is the output clock received by the input end gated by the second N-way selector.
And comparing the delay time of a first delay unit and a second delay unit according to the first output clock and the second output clock, wherein the first delay unit is a delay unit for generating the first output clock, and the second delay unit is a delay unit for generating the second output clock.
Under the condition that the delay time of the first delay unit is smaller than that of the second delay unit, the gated input end of the second N-path selector is changed, a second output clock is obtained again until all the delay units are compared, and a target delay unit is determined; and
and under the condition that the delay time of the first delay unit is greater than that of the second delay unit, changing the input end gated by the first N-way selector to be the currently-gated input end of the second N-way selector, then changing the input end gated by the second N-way selector, and re-acquiring the first output clock and the second output clock until all the delay units are compared to determine the target delay unit.
With regard to the first mode and the second mode, embodiments of the present invention further specifically provide the following two methods for comparing delay times of the first delay unit and the second delay unit according to the first output clock and the second output clock:
the first method is as follows: and sampling the first output clock at the rising edge of the second output clock, if sampling to obtain a sampling signal 0, determining that the delay time of the first delay unit is greater than that of the second delay unit, and if sampling to obtain a sampling signal 1, determining that the delay time of the first delay unit is less than that of the second delay unit.
The second method comprises the following steps: and sampling the first output clock at the falling edge of the second output clock, if sampling to obtain a sampling signal 1, determining that the delay time of the first delay unit is greater than that of the second delay unit, and if sampling to obtain a sampling signal 0, determining that the delay time of the first delay unit is less than that of the second delay unit.
S142: the delay time of the target delay unit is increased and the delay unit is controlled to operate in the second mode, and specifically, in the embodiment of the invention, the increase of the delay time of the target delay unit is mainly realized by increasing the delay time control code of the target delay unit.
S143: the maximum delay time of the delay unit in the second mode, that is, the delay time of the last stage delay unit in the second mode of the delay unit is obtained.
S144: and if the maximum delay time does not reach the clock period of the system clock signal, controlling the delay unit to work in the first mode, otherwise, controlling the delay unit to output the multi-phase clock.
According to the control method of the multi-phase delay locked loop, the delay time of each delay unit in the delay part is regulated and controlled in a mode of increasing the delay time of the target delay unit, so that the delay time of each delay unit is ensured to be equal to the maximum extent, the output multi-phase clock has an equal interval phase relation, the problem that the phase precision of the output clock of the multi-phase delay locked loop in the prior art is low is solved, and the effect of improving the phase precision of the multi-phase output clock is achieved.
Fig. 15 is a flowchart of a control method of a multiphase delay locked loop according to a preferred embodiment of the present invention, and as shown in fig. 15, the control method of the preferred embodiment further includes the following steps compared with the control method shown in fig. 14:
before controlling the delay unit to operate in the first mode and searching for the delay unit with the smallest delay time among the plurality of delay units, the control method of the multiphase delay locked loop of the preferred embodiment further includes: the delay unit is initialized, and particularly, the delay time control codes of a plurality of delay units can be controlled to be set to zero. The control method of the multiphase delay locked loop of the preferred embodiment is specifically described as follows:
s151: initializing a system;
the delay unit is mainly initialized, specifically, all delay time control CODEs CODE can be cleared, that is, the delay time control CODEs of N delay units are all set to zero.
S152: setting the delay element into a first mode;
that is, the MODE control signal MODE 1 is output to each delay unit.
S153: searching a target delay unit;
the specific search method is the same as the search method of the above embodiment, and is not described here again.
S154: increasing the delay time control CODE of the target delay unit by one;
that is, the delay time of the target delay cell is increased.
S155: setting the delay element into a second mode;
that is, the MODE control signal MODE is output to each delay unit as 0.
S156: judging whether the maximum delay time of the delay part reaches one clock cycle or not;
if the result indicates that the dll system is locked, the process proceeds to step S157, and if not, the process goes through step S152 to step S156.
S157: and outputting the N-phase clock.
In the preferred embodiment of the present invention, the plurality of delay units are initialized to ensure that the delay unit with the minimum delay time can be accurately found out subsequently, and further ensure that the determined delay unit is adjusted when the delay time is adjusted, thereby achieving the effect of further improving the phase precision of the multi-phase output clock.
From the above description, it can be seen that, by using the calibratable circuit structure and the locking algorithm with the calibration function, the present invention eliminates the influence of the production process deviation, avoids the problem that the phase of the output clock of the digital multi-phase delay phase-locked loop is not accurate due to the production process deviation, and achieves the effect of improving the phase accuracy of the multi-phase output clock.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and they may alternatively be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, or fabricated separately as individual integrated circuit modules, or fabricated as a single integrated circuit module from multiple modules or steps. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A multi-phase delay locked loop, comprising:
a delay unit having a plurality of delay cells with controllable delay time, and having a first mode in which clock signals of the plurality of delay cells are all from a system clock signal of the multiphase delay phase locked loop, and a second mode in which the plurality of delay cells are cascaded, the delay unit being configured to output a multiphase clock in the second mode;
the searching part is connected with the plurality of delay units, and is used for searching a target delay unit from the plurality of delay units when the delay part is in a first mode, wherein the target delay unit is the delay unit with the minimum delay time in the plurality of delay units; and
a control section connected to the search section and the plurality of delay cells of the delay section,
when the delay component is in a first mode, the control component is used for receiving the target delay unit sent by the searching component, increasing the delay time of the target delay unit and controlling the delay component to work in a second mode;
and when the delay component is in the second mode, the control component is also used for acquiring the maximum delay time of the delay component, and if the maximum delay time does not reach the clock period of the system clock signal, the control component controls the delay component to work in the first mode or otherwise controls the delay component to output the multi-phase clock.
2. The multi-phase delay locked loop of claim 1, wherein the delay element further has a mode selector for receiving a mode control signal to place the delay element in the first mode or the second mode.
3. The multiphase delay locked loop of claim 2, wherein the number of delay cells is N,
the mode selector comprises a number C1To CNThe N double-path selectors are respectively and correspondingly arranged in the N delay units, the control ends of the N double-path selectors are all used for receiving the mode control signals, the first input ports of the N double-path selectors and the double-path selector C1The second input ports of (a) are all used for receiving the system clock signal;
the delay member also has the number D1To DNThe N number control delay chains are respectively and correspondingly arranged in the N delay unitsControlled delay chain DiInput terminal and two-way selector CiAre connected to the output of the digital controlled delay chain DiOutput terminal and two-way selector Ci+1Is connected with the second input port of the digital control delay chain DNInput terminal and two-way selector CNI =1 to N-1, N being a natural number greater than 2.
4. The multiphase delay locked loop of claim 1, wherein the number of the delay units is N, N being a natural number greater than 2, the search unit comprises:
n input ends of the first N-path selector are respectively and correspondingly connected with N delay units;
n input ends of the second N-path selector are respectively and correspondingly connected with the N delay units;
a phase comparator, an input end of which is connected to both the output end of the first N-way selector and the output end of the second N-way selector, for comparing delay times of a first delay unit and a second delay unit according to a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, the first delay unit is the delay unit generating the first output clock, the second output clock is the output clock received by the input end gated by the second N-way selector, and the second delay unit is the delay unit generating the second output clock; and
and the clock selector is used for changing the input end gated by the second N-way selector under the condition that the delay time of the first delay unit is less than that of the second delay unit until the target delay unit is determined, or changing the input end gated by the first N-way selector under the condition that the delay time of the first delay unit is greater than that of the second delay unit until the target delay unit is determined.
5. The multiphase delay locked loop of claim 1, wherein the number of the delay units is N, N being a natural number greater than 2, the search unit comprises:
n input ends of the first N-path selector are respectively and correspondingly connected with N delay units;
n input ends of the second N-path selector are respectively and correspondingly connected with the N delay units;
a phase comparator, an input end of which is connected to both the output end of the first N-way selector and the output end of the second N-way selector, for comparing delay times of a first delay unit and a second delay unit according to a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, the first delay unit is the delay unit generating the first output clock, the second output clock is the output clock received by the input end gated by the second N-way selector, and the second delay unit is the delay unit generating the second output clock; and
and the clock selector is used for changing the input end gated by the second N-way selector until the target delay unit is determined, or changing the input end gated by the first N-way selector to be the currently-gated input end of the second N-way selector and then changing the gated input end gated by the second N-way selector under the condition that the delay time of the first delay unit is greater than that of the second delay unit until the target delay unit is determined.
6. The multiphase delay locked loop of claim 4 or 5, wherein the phase comparator comprises:
the data input end is connected with the output end of the first N-path selector and used for receiving the first output clock;
the clock input end is connected with the output end of the second N-path selector and used for receiving the second output clock; and
a sampling output end connected with the clock selector and used for sampling the first output clock under the trigger of the second output clock and outputting a sampling signal 0 or 1,
wherein if the sampling output terminal samples the first output clock at a rising edge of the second output clock, the clock selector determines that the delay time of the first delay unit is greater than the delay time of the second delay unit when receiving the sampling signal 0, and determines that the delay time of the first delay unit is less than the delay time of the second delay unit when receiving the sampling signal 1,
if the sampling output end samples the first output clock at the falling edge of the second output clock, the clock selector determines that the delay time of the first delay unit is greater than the delay time of the second delay unit when receiving the sampling signal 1, and determines that the delay time of the first delay unit is less than the delay time of the second delay unit when receiving the sampling signal 0.
7. A control method for a multi-phase delay-locked loop, which is applied to a multi-phase delay-locked loop having a delay unit, wherein the delay unit includes a plurality of delay units with controllable delay time, and has a first mode and a second mode, wherein in the first mode, clock signals of the plurality of delay units are all from a system clock signal of the multi-phase delay-locked loop, and in the second mode, the plurality of delay units are cascaded, the control method comprising:
when the delay part is in a first mode, searching a target delay unit from the plurality of delay units, wherein the target delay unit is the delay unit with the minimum delay time in the plurality of delay units;
increasing the delay time of the target delay unit and controlling the delay unit to operate in a second mode;
acquiring the maximum delay time of the delay part in a second mode;
and if the maximum delay time does not reach the clock period of the system clock signal, controlling the delay component to work in a first mode, otherwise, controlling the delay component to output the multi-phase clock.
8. The control method according to claim 7, characterized by further comprising:
after initializing the delay unit, controlling the delay unit to operate in the first mode.
9. The control method of claim 8, wherein the initializing the delay component comprises: and the delay time control codes controlling a plurality of delay units are all set to zero.
10. The control method of claim 9, wherein the increasing the delay time of the target delay cell comprises:
adding one to the delay time control code of the target delay cell.
11. The control method according to claim 7, wherein the number of the delay units is N, N is a natural number greater than 2, the multiphase delay locked loop further includes a first N-way selector and a second N-way selector, N input terminals of the first N-way selector are respectively and correspondingly connected to N delay units, N input terminals of the second N-way selector are respectively and correspondingly connected to N delay units, and searching for a delay unit with a smallest delay time among the plurality of delay units includes:
acquiring a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, and the second output clock is the output clock received by the input end gated by the second N-way selector;
comparing delay times of a first delay unit and a second delay unit according to the first output clock and the second output clock, wherein the first delay unit is a delay unit for generating the first output clock, and the second delay unit is a delay unit for generating the second output clock;
under the condition that the delay time of the first delay unit is smaller than that of the second delay unit, the gated input end of the second N-path selector is changed, and the second output clock is obtained again until the target delay unit is determined; and
and under the condition that the delay time of the first delay unit is greater than that of the second delay unit through comparison, changing the gated input end of the first N-way selector, and reacquiring the first output clock until the target delay unit is determined.
12. The control method according to claim 7, wherein the number of the delay units is N, N is a natural number greater than 2, the multiphase delay locked loop further includes a first N-way selector and a second N-way selector, N input terminals of the first N-way selector are respectively and correspondingly connected to N delay units, N input terminals of the second N-way selector are respectively and correspondingly connected to N delay units, and searching for a delay unit with a smallest delay time among the plurality of delay units includes:
acquiring a first output clock and a second output clock, wherein the first output clock is the output clock received by the input end gated by the first N-way selector, and the second output clock is the output clock received by the input end gated by the second N-way selector;
comparing delay times of a first delay unit and a second delay unit according to the first output clock and the second output clock, wherein the first delay unit is a delay unit for generating the first output clock, and the second delay unit is a delay unit for generating the second output clock;
under the condition that the delay time of the first delay unit is smaller than that of the second delay unit, the gated input end of the second N-path selector is changed, and the second output clock is obtained again until the target delay unit is determined; and
and under the condition that the delay time of the first delay unit is greater than that of the second delay unit, changing the input end gated by the first N-way selector to be the currently-gated input end of the second N-way selector, then changing the input end gated by the second N-way selector, and reacquiring the first output clock and the second output clock until the target delay unit is determined.
13. The control method according to claim 11 or 12, wherein comparing the delay times of the first delay unit and the second delay unit according to the first output clock and the second output clock comprises:
sampling the first output clock on a rising edge of the second output clock;
if sampling is carried out to obtain a sampling signal 0, determining that the delay time of the first delay unit is greater than that of the second delay unit; and
and if sampling to obtain a sampling signal 1, determining that the delay time of the first delay unit is less than that of the second delay unit.
14. The control method according to claim 11 or 12, wherein comparing the delay times of the first delay unit and the second delay unit according to the first output clock and the second output clock comprises:
sampling the first output clock on a falling edge of the second output clock;
if sampling is carried out to obtain a sampling signal 1, determining that the delay time of the first delay unit is greater than that of the second delay unit; and
and if the sampling signal 0 is obtained through sampling, determining that the delay time of the first delay unit is less than that of the second delay unit.
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| CN103825607B (en) * | 2014-03-06 | 2017-02-01 | 龙芯中科技术有限公司 | Digital delay phase-locked loop and adjusting method thereof |
| CN104135282B (en) * | 2014-06-25 | 2017-12-05 | 电子科技大学 | Multiphase clock generator realizes high-resolution method |
| KR20160110604A (en) * | 2015-03-09 | 2016-09-22 | 에스케이하이닉스 주식회사 | Circuit for generating clock |
| CN107592110B (en) * | 2017-10-27 | 2023-10-20 | 长鑫存储技术有限公司 | Delay phase-locked loop clock line and semiconductor memory |
| CN109088619B (en) * | 2018-07-24 | 2022-06-28 | 北京时代民芯科技有限公司 | Method and circuit for generating enable signal |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| CN112787665B (en) * | 2020-12-28 | 2024-08-30 | 珠海全志科技股份有限公司 | Phase-adjustable clock signal generation method and device |
| CN113037278A (en) * | 2021-03-16 | 2021-06-25 | 重庆百瑞互联电子技术有限公司 | Method and device for optimizing delay locking circuit and storage medium |
| CN115065359B (en) * | 2022-08-11 | 2022-11-04 | 睿力集成电路有限公司 | Delay-locked loop, clock synchronization circuit and memory |
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