CN111404536A

CN111404536A - Capacitance detection circuit of touch device, touch device and electronic equipment

Info

Publication number: CN111404536A
Application number: CN202010296811.6A
Authority: CN
Inventors: 王洁
Original assignee: Shenzhen Xihua Technology Co Ltd
Current assignee: Shenzhen Xihua Technology Co Ltd
Priority date: 2020-04-15
Filing date: 2020-04-15
Publication date: 2020-07-10

Abstract

The capacitance detection circuit comprises a capacitance control delay circuit and a D LL circuit, wherein the capacitance control delay circuit is used for generating a first clock signal according to a reference clock signal and the capacitance value of a capacitor to be detected, the first clock signal and the reference clock signal have first delay time, the D LL circuit comprises a digital phase discriminator and a digital control delay circuit, the digital phase discriminator outputs a first digital signal, the digital control delay circuit is used for controlling the delay time of a second clock signal according to the reference clock signal and the first digital signal, the second clock signal and the reference clock signal have second delay time, when the D LL circuit is locked, the difference value of the first delay time and the second delay time is N periods of the reference clock signal, and the first digital signal output by the digital phase discriminator is used for determining the capacitance value of the capacitor to be detected.

Description

Capacitance detection circuit of touch device, touch device and electronic equipment

Technical Field

The embodiments of the present application relate to the field of capacitance detection, and more particularly, to a capacitance detection circuit, a capacitance detection system, and an electronic device.

Background

Capacitive touch devices are widely used in electronic devices, for example, as input devices to provide input information, such as position, motion, force, and duration. The core of a capacitive touch device is a capacitance detection circuit. In the related art of capacitance detection, capacitance detection based on a time domain is a mainstream detection method, and is specifically implemented by charging a capacitor to be detected, converting a charge amount of the capacitor to be detected into a voltage, or converting a variation amount of the charge charged by the capacitor to be detected into a voltage, and further processing the voltage to determine a capacitance value of the capacitor to be detected, for example, sampling the voltage by an Analog to Digital Converter (ADC) and converting the voltage into a Digital signal, and then performing capacitance detection according to the Digital signal. The capacitance detection by adopting the mode is influenced by circuit noise, and the detection precision of the capacitance detection is reduced.

Disclosure of Invention

The embodiment of the application provides a capacitance detection circuit of a touch device, the touch device and electronic equipment, which can reduce the influence of circuit noise on capacitance detection, thereby improving the detection precision of capacitance detection.

In a first aspect, the present application provides a capacitance detection circuit of a touch device, the touch device further includes a touch screen, the touch screen includes a plurality of capacitances to be measured, the capacitance detection circuit is connected to the capacitances to be measured, the capacitance detection circuit includes:

the capacitance control delay circuit is used for generating a first clock signal according to a reference clock signal and the capacitance value of the capacitor to be tested, wherein the first clock signal has a first delay time relative to the reference clock signal, and the first delay time is positively correlated with the capacitance value of the capacitor to be tested;

the delay phase-locked loop D LL circuit comprises a digital phase detector and a digitally controlled delay circuit, wherein the digital phase detector comprises a first input end, a second input end and an output end, the first input end of the digital phase detector is connected to the output end of the capacitance control delay circuit, and the second input end of the digital phase detector is connected to the output end of the digitally controlled delay circuit;

the digital phase detector is used for receiving the first clock signal and a second clock signal output by the digitally controlled delay circuit, and outputting a first digital signal according to the phases of the first clock signal and the second clock signal, and the output end of the digital phase detector is used for outputting the first digital signal;

the digitally controlled delay circuit is configured to control a delay time of the output second clock signal according to the reference clock signal and the first digital signal, and output the second clock signal to a second input terminal of the digital phase detector, where the second clock signal has a second delay time with respect to the reference clock signal;

when the D LL circuit is locked, a difference between the first delay time and the second delay time is N cycles of the reference clock signal, where N is an integer, and a first digital signal output by the digital phase detector when the D LL circuit is locked is used to determine a capacitance value of the capacitor to be measured.

In some optional implementations, when the D LL circuit is locked, the first delay time and the second delay time are equal.

In some optional implementations, the D LL circuit further includes:

the processing circuit is connected with the digital phase detector and the digitally controlled delay circuit and is used for receiving the first digital signal output by the digital phase detector, processing the first digital signal and outputting the processed first digital signal to the input end of the digitally controlled delay circuit, wherein the processed first digital signal is used for controlling the delay time of the second clock signal, and the processing comprises at least one of the following steps: integration processing, signal amplification or reduction processing, and filtering processing.

In some alternative implementations, the digitally controlled delay circuit includes:

the digital-to-analog converter DAC comprises an input end and an output end, the input end is connected to the output end of the processing circuit, the DAC is used for converting a first digital signal obtained by processing of the processing circuit into a first analog signal, and the output end is used for outputting the first analog signal;

the first input end of the analog control delay line is connected to the output end of the DAC and used for receiving the first analog signal, the second input end of the analog control delay line is used for inputting the reference clock signal, the analog control delay line is used for controlling the delay time of the second clock signal according to the first analog signal and the reference clock signal, and the output end of the analog control delay line is used for outputting the second clock signal.

In some optional implementations, the analog control delay line includes a plurality of stages of delay cells connected in series, each delay cell includes a first terminal and a second terminal, the first terminal of each delay cell is used for inputting the reference clock signal, the second terminal of each delay cell is used for inputting the first analog signal, the first analog signal is used for controlling a corresponding delay time of each delay cell, and the second delay time is a total delay time of the plurality of stages of delay cells.

In some optional implementations, the first analog signal is an analog voltage and the analog controlled delay line is a voltage controlled delay line VCD L.

In some optional implementations, the capacitance detection circuit further includes:

and the processing unit is used for determining whether the capacitance value of the capacitor to be tested is changed relative to a basic capacitance according to the processed first digital signal output by the processing circuit when the D LL is locked, wherein the basic capacitance is the capacitance value of the capacitor to be tested when the touch screen is not touched.

In some optional implementations, the capacitor to be tested is formed by a detection electrode and a driving electrode in the touch screen, or the capacitor to be tested is formed by a detection electrode and an external object in the touch screen.

In some alternative implementations, some or all of the capacitance detection circuit is integrated into a touch sensing chip.

In a second aspect, the present application further provides a touch device, including:

the touch screen comprises a capacitor to be tested;

the capacitance detection circuit in the first aspect or any one of the optional implementations of the first aspect, the capacitance detection circuit is connected to the capacitor to be detected, and the capacitance detection circuit is configured to detect a capacitance value of the capacitor to be detected.

In a third aspect, the present application further provides an electronic device, including the touch device in any optional implementation manner of the second aspect or the second aspect.

Based on the technical scheme, the delay time is controlled based on the same reference clock signal by configuring the capacitance control delay circuit and the digital control delay circuit, thereby enabling the delay time of the second clock signal output by the digitally controlled delay circuit to be correlated with the delay time of the first clock signal output by the capacitance controlled delay circuit, and the delay time of the second clock signal is controlled according to the first digital signal output by the digital phase detector, i.e. the first digital signal is related to the delay time of the first clock signal, and the delay time of the first clock signal is related to the capacitance value of the capacitor under test, therefore, the first digital signal is related to the capacitance value of the capacitor to be measured, and the capacitance value of the capacitor to be measured can be determined according to the first digital signal.

Therefore, the capacitor detection can be carried out based on the principle that different clock delays can be generated by different capacitance values, the charge and discharge process of a time domain is not needed for the capacitor to be detected, the influence of circuit noise on the capacitor detection process is favorably reduced, and therefore the precision of the capacitor detection can be improved.

Drawings

Fig. 1 is a schematic configuration diagram of a capacitance detection device according to an embodiment of the present application.

Fig. 2 is a schematic block diagram of a digitally controlled delay circuit according to an embodiment of the present application.

Fig. 3 is a schematic circuit diagram of a voltage controlled delay line according to an embodiment of the present application.

FIG. 4 is a schematic block diagram of a capacitive detection system according to an embodiment of the present application.

Fig. 5 is a schematic block diagram of an electronic device according to an embodiment of the application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter can be practiced without one or more of the specific details, or with other structures, components, and so forth. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring the invention.

Further, the following terms are exemplary and are not intended to be limiting in any way. After reading this application, those skilled in the art will recognize that these terms apply to techniques, methods, physical elements, and systems (whether currently known or not), including extensions thereof that may be inferred or inferred by those skilled in the art after reading this application.

Fig. 1 is a schematic block diagram of a capacitance detection circuit 10 according to an embodiment of the present application, the capacitance detection circuit 10 is connected to a capacitor 20 to be tested, as shown in fig. 1, the capacitance detection circuit 10 includes:

a capacitance control delay circuit 11, configured to generate a first clock signal C L K1 according to a reference clock signal C L K _ REF and a capacitance value of the capacitor 20 to be tested, wherein the first clock signal C L K1 has a first delay time relative to the reference clock signal C L K _ REF, and the first delay time is positively correlated with the capacitance value of the capacitor 20 to be tested;

the delay phase-locked loop D LL circuit 12 comprises a digital phase detector 121 and a digitally controlled delay circuit 123, wherein the digital phase detector comprises a first input end, a second input end and an output end, the first input end of the digital phase detector 121 is connected to the output end of the capacitance controlled delay circuit 11, and the second input end of the digital phase detector 121 is connected to the output end of the digitally controlled delay circuit 123;

the digital phase detector 121 is configured to receive the first clock signal C L K1 and the second clock signal C L K2 output by the digitally controlled delay circuit 121, and output a first digital signal D1 according to a phase offset between the first clock signal C L K1 and the second clock signal C L K2, where an output end of the digital phase detector 121 is configured to output the first digital signal D1;

the digitally controlled delay circuit 123 is configured to control a delay time of the second clock signal C L K2 according to the reference clock signal C L K1 and the first digital signal D1, and input the second clock signal C L K2 to a second input terminal of the digital phase detector 121, where the second clock signal C L K2 has a second delay time with respect to the reference clock signal C L K _ REF;

when the D LL circuit 12 is locked, a difference between the first delay time and the second delay time is N cycles of the reference clock signal, where N is an integer, and the first digital signal D1 output by the digital phase detector 121 when the D LL circuit 12 is locked is used to determine the capacitance value of the capacitor 20 to be measured.

In this embodiment, the reference clock signal C L K _ REF may be generated by a low-noise reference clock source, and the implementation manner of the reference clock source may refer to related implementations in the prior art, which is not limited in this application.

In the embodiment of the present application, the capacitance controlled delay circuit 11 is a delay circuit controlled by the capacitance value of the capacitor 20 to be tested, i.e. the change of the capacitance value of the capacitor 20 to be tested can change the delay time of the clock signal output by the capacitance controlled delay circuit 11. specifically, the capacitance controlled delay circuit 11 can generate the first clock signal C L K1 according to the capacitance value of the capacitor 20 to be tested, and the first clock signal C L K1 has a first delay time relative to the reference clock signal C L K _ REF input by the capacitance controlled delay circuit 11, and the first delay time is positively correlated with the capacitance value of the capacitor 20 to be tested, i.e. the larger the capacitance value of the capacitor 20 to be tested, the larger the delay time of the first clock signal C L K1 relative to the reference clock signal C L K _ REF, i.e. the delay time of the first clock signal C L K1 can reflect the size of the capacitance value of the capacitor 20 to be tested.

The D LL circuit 12 may control the delay time of the output second clock signal C L K2 according to the reference clock signal C L K _ REF such that the second clock signal C L K2 and the first clock signal C L K1 are aligned in clock phase, and when the D LL circuit 12 is locked, or phase aligned, the second clock signal C L K2 has a second delay time relative to the reference clock signal C L K _ REF, and the difference between the first delay time and the second delay time is N cycles of the reference clock signal C L K _ REF, where N is an integer, and typically, N is zero.

Specifically, the D LL circuit 12 includes a digital phase detector 121 and a digitally controlled delay circuit 123, where the digital phase detector 121 outputs a first digital signal D1 by detecting a phase relationship between a first clock signal C L K1 output by the capacitance controlled delay circuit 11 and a second clock signal C L K2 output by the digitally controlled delay circuit 123, for example, if the phase of the first clock signal C L K1 is earlier than that of the second clock signal C L K2, the first digital phase detector 121 may output 1, or if the phase of the first clock signal C L K1 is later than that of the second clock signal C L K2, the first digital phase detector 121 may output 0, or vice versa, only if the adjustment logic of the delay time of the digitally controlled delay circuit 123 makes a corresponding adjustment.

Further, the input clock signal of the digitally controlled delay circuit 123 is also the reference clock signal C L K _ REF, and the digitally controlled delay circuit 123 may control the delay time of the second clock signal C L K2 according to the reference clock signal C L K _ REF and the first digital signal D1 output by the digital phase detector 121, and output the adjusted second clock signal C L K2 to the second input end 1212 of the digital phase detector 121.

The phase offset between the two clock signals is detected by the digital phase detector 121, a corresponding digital signal is output, and the digitally controlled delay circuit 123 controls a second delay time of the second clock signal C L K2 relative to the reference clock signal C L K _ REF according to the digital signal, so that finally the delay time between the first clock signal C L K1 and the second clock signal C L K2 is locked to N cycles of the reference clock signal C L K, at this time, the D LL circuit 12 is stable, or locked, and the output of the digital phase detector 121 is also stable.

In a specific implementation, when the D LL circuit 12 is locked, a first delay time of the first clock signal C L K1 with respect to the reference clock signal C L K _ REF and a second delay time of the second clock signal C L K2 with respect to the reference clock signal C L K _ REF may be controlled to be equal, that is, the first clock signal C L K1 and the second clock signal C L K2 have the same delay time with respect to the reference clock signal C L K _ REF, in other words, the first clock signal C L K1 and the second clock signal C L K1 are synchronized, in which case, an operating state of the D L0 circuit 12 is more stable, and accordingly, an output of the digital phase detector 121 is also more stable.

In summary, the present application designs the same reference clock signal as the reference clock common to the capacitance-controlled delay circuit 11 and the digitally-controlled delay circuit 123, such that the first clock signal C L K1 having a first delay time with respect to the reference clock signal C L K _ REF can be generated by the capacitance-controlled delay circuit 11, and the second clock signal C L K2 having a second delay time with respect to the reference clock signal C L K _ REF can be generated by the digitally-controlled delay circuit 123, and when the D LL circuit 12 is locked, the first delay time and the second delay time are equal.

According to the operation principle of the capacitance control delay circuit 11, the first delay time of the first clock signal C L K1 outputted from the reference clock signal C L K _ REF is positively correlated with the capacitance value of the capacitor 20 to be measured, and the second delay time is equal to the first delay time, so that the second delay time is positively correlated with the capacitance value of the capacitor 20 to be measured, and the second delay time is controlled according to the first digital signal D1, that is, the second delay time is correlated with the first digital signal, so that the capacitance value of the capacitor 20 to be measured can be determined according to the first digital signal.

Optionally, the digital Phase Detector 121 may be implemented by a Binary Phase Detector (Binary PD), a Binary Phase Frequency Detector (Binary PFD), or other equivalent circuits, as long as the Phase offset between the signals can be converted into a digital signal to gradually approximate the Phase of the signal, which is not limited in this application.

Optionally, in some embodiments of the present application, as shown in fig. 1, the D LL circuit 12 may further include:

and the processing circuit 122, which is connected to the digital phase detector 121 and the digitally controlled delay circuit 123, is configured to receive the first digital signal D1 output by the digital phase detector 121, process the first digital signal, and output the processed first digital signal D1 'to the digitally controlled delay circuit 123, so that the digitally controlled delay circuit 123 can control the delay time of the second clock signal C L K2 based on the processed first digital signal D1'.

In some embodiments of the present application, the processing of the first digital signal D1 by the processing circuit 122 includes, but is not limited to, at least one of: integration processing, enlargement or reduction processing, and filtering processing.

It is understood that different D LL circuits 12 correspond to corresponding performance criteria, such as a capacitance range of a capacitor capable of being measured, stability, a Signal-to-Noise Ratio (SNR), etc., and the processing circuit 123 may perform corresponding processing on the first digital Signal according to the corresponding performance criteria to meet the performance criteria, in one implementation, the processing circuit 122 may perform integration processing on the first digital Signal D1 output by the digital phase detector 121, further perform amplification or reduction processing so that the capacitance of the capacitor to be measured falls within the capacitance range of the capacitance detection circuit, further perform filtering processing on the amplified or reduced digital Signal, in another implementation, the processing circuit 122 may perform amplification or reduction processing on the first digital Signal D1 first, further perform integration processing, and finally perform filtering processing on the first digital Signal and output to the digitally controlled delay circuit 123, or may perform other processing on the first digital Signal, and only the performance requirements of the D LL may be met.

It should be noted that, the use of the first digital signal D1 output by the digital phase detector 121 to determine the capacitance value of the capacitor to be measured 20 may refer to that the first digital signal may be directly used to determine the capacitance value of the capacitor to be measured 10, or may refer to a signal after the processing circuit 122 processes the first digital signal, that is, D1' may be used to determine the capacitance value of the capacitor to be measured.

It should be further noted that the using of the first digital signal D1 output by the digital phase detector 121 to determine the capacitance value of the capacitor 20 to be tested may include using the first digital signal D1 output by the digital phase detector 121 to determine a change, or whether a change occurs, of the capacitance value of the capacitor 20 to be tested.

As can be seen from the foregoing capacitance detection principle, the processed first digital signal D1 'can be used to control the magnitude of the second delay time, that is, the processed first digital signal D1' is related to the second delay time, and the second delay time is equal to the first delay time, so that the processed first digital signal D1 'is related to the first delay time, and the first delay time is positively related to the capacitance value of the capacitor to be measured, so that the processed first digital signal D1' is related to the capacitance value of the capacitor to be measured. Therefore, the capacitance value of the capacitor to be measured can be determined from the processed first digital signal D1'.

Optionally, in some embodiments, the capacitor under test 20 may be, for example but not limited to, a sensing element in a touch device, for example, a capacitor under test in a touch screen of a capacitive touch device, and specifically, the touch device includes a touch panel, which may also be referred to as a touch screen. The capacitor 20 to be tested is formed by a driving electrode and a detecting electrode on the touch panel, or the capacitor 20 to be tested may be formed by a detecting electrode on the touch panel and a ground, or the capacitor 20 to be tested may be formed by a detecting electrode on the touch panel and an external object. The external object is a conductor, such as but not limited to a finger of a user. In this scenario, the capacitance value of the capacitor 20 under test can be used to determine whether the touch device is touched, for example, whether the touch device is touched can be determined according to whether the capacitance value of the capacitor 20 under test is changed. Alternatively, whether the capacitance value of the capacitor 20 to be measured changes may be whether the capacitance value of the capacitor 20 to be measured changes relative to a base capacitance, where the base capacitance is a capacitance value of the capacitor 20 to be measured when the capacitor 20 to be measured is not contacted or approached by an external object, and the capacitance value may also be referred to as a nominal capacitance.

Optionally, in some embodiments of the present application, the capacitance detection circuit 10 may further include:

and a processing unit, configured to determine whether a capacitance value of the capacitor to be tested changes from a base capacitance according to the processed first digital signal output by the processing circuit when D LL is locked, where the base capacitance is a capacitance value of the capacitor to be tested 20 when the capacitor to be tested is not contacted or approached by an external object.

Taking the capacitive touch detection scenario as an example, the processing unit may first determine that the touch device is not touched, and then record a first digital signal output by the processing circuit 122 as a nominal digital signal D1 '_ REF, where the nominal digital signal D1' _ REF corresponds to the base capacitance C _ REF of the capacitor to be tested, and the first digital signal and the nominal digital signal may be converted by a specific relationship.

Further, whether the touch device is touched may be determined according to the processed first digital signal D1 ', for example, whether the touch device is touched may be determined according to a change of the first digital signal D1 ' output by the processing circuit 122 relative to a nominal digital signal D1 ' _ REF, and as an example, if the processed first digital signal D1 ' is changed relative to the nominal digital signal D1 ' _ REF or the change amount is greater than a certain threshold value, it may be determined that the touch device is touched, otherwise, it is determined that the touch device is not touched.

In other embodiments, the processed first digital signal D1' may be further processed and converted into a corresponding capacitance value C, and whether the touch device is touched may be further determined according to the capacitance value C. For example, whether the touch device is touched may be determined according to a change of the capacitance value C corresponding to the processed first digital signal D1' relative to a base capacitance C _ REF, and for example, if the capacitance value C corresponding to the processed first digital signal changes relative to the base capacitance C _ REF or the change is greater than a certain threshold, it may be determined that the touch device is touched, otherwise, it is determined that the touch device is not touched.

Optionally, in some embodiments, the processing unit may be a processing unit in a device or an apparatus in which the capacitance detection circuit 10 is installed, for example, if part or all of the capacitance detection circuit 10 may be integrated in a touch sensing chip of a touch apparatus, the touch sensing chip is electrically connected to a touch panel for driving the touch panel to perform a touch sensing operation. The processing unit may be a processing unit in the touch device, or may also be a main control module in an electronic device in which the touch device is located.

It should be understood that, in the embodiment of the present application, the digitally controlled delay circuit 123 may provide clock signals with different phases through the internal delay stages, and may be implemented by any circuit that controls delay time according to a digital signal, which is not limited in the embodiment of the present application.

A typical implementation of the digitally controlled delay circuit 123 is described below in conjunction with fig. 2. As shown in fig. 2, the digitally controlled delay circuit 123 includes:

a digital-to-analog converter DAC1231, including an input end and an output end, the input end being connected to the output end of the processing circuit 122, the DAC1231 being configured to convert the first digital signal D1' processed by the processing circuit 122 into a first analog signal a1, and the output end being configured to output the first analog signal a 1;

an analog control delay line 1232 comprising a first input terminal, a second input terminal and an output terminal, the first input terminal of the analog control delay line 1232 is connected to the output terminal of the DAC1231 for receiving the first analog signal a1, the second input terminal of the analog control delay line 1232 is used for inputting the reference clock signal C L K _ REF, the analog control delay line 1232 is used for controlling the delay time of the second clock signal C L K2, i.e. the second delay time, according to the first analog signal a1 and the reference clock signal C L K _ REF, and the output terminal of the analog control delay line 1232 is used for outputting the second clock signal C L K2.

Since the D LL circuit 12 is a negative feedback system, the phase misalignment between the first clock signal C L K1 and the second clock signal C L K2 is gradually reduced until vanishing by the negative feedback mechanism, and at this time, the analog signal output by the DAC is kept stable, and the D LL circuit 12 is locked.

In some embodiments, the first analog signal a1 may be an analog Voltage or an analog Current, and correspondingly, the analog control Delay line 1232 may be a Voltage Controlled Delay line (VCD L, L ine) or a Current Controlled Delay line (CCD L), hereinafter, a typical implementation of the VCD L is described by taking the first analog signal as an analog Voltage, which may be implemented in other manners, which is not limited herein.

As shown in fig. 3, the analog control delay line 1232 includes a plurality of stages of delay cells 12321 connected in series, each delay cell 12321 includes a first terminal and a second terminal, the first terminal of each delay cell 12321 is used for inputting the reference clock signal C L K _ REF, the second terminal of each delay cell 12321 is used for inputting the first analog signal (taking the first analog signal as an analog voltage V-REF as an example), the first analog signal V-REF is used for controlling the corresponding delay time of each delay cell 12321, and the delay time of the second clock signal C L K2 is the total delay time of the plurality of stages of delay cells.

Specifically, each stage of delay unit of the VCD L can output a certain phase offset, the degree of the phase offset output by each stage of delay unit of the VCD L is controlled by an analog voltage V-REF, the total delay time of all the delay units constitutes the delay of the analog control delay line 1232, i.e., the delay time of the second clock signal C L K2, the first clock signal C L K1 and the second clock signal C L K2 are compared in phase by the digital phase detector 121, and corresponding digital signals are output, and the digital signals are further processed and converted into analog signals, such as the analog voltage V-REF, which is used for changing the delay time of the delay units in the VCD L.

In some embodiments, analog controlled delay line 1232 may implement a delay cell with an inverter while an active state machine is used to select the output signal.

Specifically, in the VCD L, a single delay cell represents the minimum delay time, such as the delay time of one basic inverter, since each inverter can shift the phase by 180 degrees, the VCD L can output at an even number of inverters to provide the corresponding phase, the VCD L needs to select the signal with the phase closest to the phase of the first clock signal C L K1 as the output clock signal for feedback, therefore, the output signal to be realized in the VCD L is not necessarily the last stage output of the VCD L, i.e., the second clock signal is not necessarily output at the last stage of the VCD L, but it is necessarily output at the position closest to the phase of the first clock signal C L K1, and the corresponding signal can be generated by an active state machine to select the output signal.

In a specific implementation, the delay of each delay unit has a certain relationship with the RC time constant in the delay unit. The larger the time constant, the larger the delay, and the delay of each stage of delay unit can be adjusted by changing the time constant of the delay unit, such as the impedance R or the load capacitor C.

In the embodiment of the present application, therefore, by configuring the capacitance controlled delay circuit 11 and the analog controlled delay line 1232 to perform control of the delay time based on the same reference clock signal, so that the delay time of the second clock signal is related to the delay time of the first clock signal, which is controlled by the first analog signal a1, thereby enabling the delay time of the first analog signal a1 and the first clock signal to be correlated and, further, the first analog signal a1 is obtained from the processed first digital signal, so the processed first digital signal is related to the delay time of the first clock signal, that is, the capacitance value of the capacitor under test, and therefore, and determining the change of the capacitance value of the capacitor to be measured according to the processed first digital signal.

The present application further provides a capacitance detection system 40, as shown in fig. 4, the capacitance detection system 40 includes: the capacitor 41 to be detected and the capacitance detection circuit 42, the capacitance detection circuit 42 is connected to the capacitor 41 to be detected, and the capacitance detection circuit 42 is used for detecting the capacitance value of the capacitor 41 to be detected.

Optionally, in some embodiments, the capacitance detection system is a touch device, and the capacitance value of the capacitor to be tested is used to determine whether the touch device is touched.

Alternatively, the touch device may be a capacitive touch device. Such as a mutual capacitance touch device or a self-capacitance touch device.

In a mutual capacitance-based touch system, a touch screen can include, for example, drive and sense regions, such as drive lines (or drive electrodes) and sense lines (or detection electrodes). As one example, the drive lines can form multiple rows and the sense lines can form multiple columns (e.g., orthogonal). Touch pixels can be disposed at intersections of rows and columns. During operation, the rows can be stimulated with an alternating current signal (AC) waveform, and mutual capacitances can be formed between rows and columns of the touch pixels. When an object is in proximity to the touch pixel, some of the charge coupled between the rows and columns of the touch pixel may instead be coupled to the object. This reduction in charge coupled onto the touch pixel can result in a net reduction in the mutual capacitance between rows and columns and a reduction in the AC waveform coupled onto the touch pixel. This reduction in the charge-coupled AC waveform can be detected and measured by a touch system to determine whether there is a touch, and the location of the object on the touch screen. For a mutual capacitance touch screen, the capacitor to be tested is formed by a detection electrode and a driving electrode on the mutual capacitance touch screen.

In contrast, in a self-capacitance based touch system, each touch pixel can be formed by an individual electrode that forms a self-capacitance to ground. When an object is close to the touch pixel, another capacitance to ground (capacitance to ground) may be formed between the object and the touch pixel. The further capacitance to ground may result in a net increase in the self-capacitance experienced by the touch pixel. This increase in self-capacitance can be detected and measured by the touch system to determine whether there is a touch, and the location of the object when touching the touch screen. For a self-contained touch screen, the capacitor to be tested is formed by the detection electrode on the touch screen and the ground, or the capacitor to be tested 20 is formed by the detection electrode on the touch screen and an external object. Such as, but not limited to, a conductive object such as a user's finger.

The touch panel of the touch device can be a touch screen externally hung above the display panel, and can also be integrated in the display panel (Incell), and the like, and the technical schemes are within the protection scope of the application.

Additionally, the capacitance detection system 40 may also be a fingerprint sensing device. Accordingly, the capacitance detection circuit 42 is a capacitance detection circuit in a fingerprint sensing device. The capacitor 41 to be tested is a capacitor to be tested in the fingerprint sensing device.

Fig. 5 shows a schematic structural diagram of an electronic device 50 according to an embodiment of the present application, and as shown in fig. 5, the electronic device may include a capacitance detection system 51, where the capacitance detection system 51 may be the capacitance detection system 40 in fig. 4.

It should be understood that the electronic device 100 of the present embodiment may include, but is not limited to, a smart phone, a tablet, a computer, a notebook, a smart wearable device, a smart door lock, and the like. In order to realize the basic functions of the electronic device, the electronic device in the embodiments of the present application may include other necessary modules or components in addition to the modules or components illustrated above. Taking the electronic device as a smart phone as an example, it may further include a communication module, a speaker, a microphone, a battery, and the like.

The processing unit may be an integrated circuit chip having signal processing capability. In the implementation process, the steps executed by the processing unit can be completed by hardware integrated logic circuits or instructions in the form of software in the processor. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The utility model provides a touch device's capacitance detection circuit, touch device still includes the touch-sensitive screen, the touch-sensitive screen includes a plurality of capacitances that await measuring, capacitance detection circuit is connected to the capacitance that awaits measuring, its characterized in that, capacitance detection circuit includes:

a delay locked loop circuit comprising: the digital phase detector comprises a first input end, a second input end and an output end, wherein the first input end of the digital phase detector is connected to the output end of the capacitance control delay circuit, and the second input end of the digital phase detector is connected to the output end of the digital control delay circuit;

the digital phase detector is used for receiving the first clock signal and a second clock signal output by the digitally controlled delay circuit and outputting a first digital signal according to the phases of the first clock signal and the second clock signal, and the output end of the digital phase detector is used for outputting the first digital signal;

when the delay locked loop circuit is locked, the difference value between the first delay time and the second delay time is N periods of the reference clock signal, N is an integer, and when the delay locked loop circuit is locked, the first digital signal output by the digital phase detector is used for determining the capacitance value of the capacitor to be detected.

2. The capacitance detection circuit of claim 1, wherein the first delay time and the second delay time are equal when the delay locked loop circuit is locked.

3. The capacitance detection circuit of a touch device according to claim 1, wherein the delay locked loop circuit further comprises:

4. The capacitance detection circuit of claim 3, wherein the digitally controlled delay circuit comprises:

the digital-to-analog converter comprises an input end and an output end, the input end is connected to the output end of the processing circuit, the digital-to-analog converter is used for converting a first digital signal obtained by processing of the processing circuit into a first analog signal, and the output end is used for outputting the first analog signal;

the analog control delay line comprises a first input end, a second input end and an output end, wherein the first input end of the analog control delay line is connected to the output end of the digital-to-analog converter and used for receiving the first analog signal, the second input end of the analog control delay line is used for inputting the reference clock signal, the analog control delay line is used for controlling the delay time of the second clock signal according to the first analog signal and the reference clock signal, and the output end of the analog control delay line is used for outputting the second clock signal.

5. The capacitance detection circuit of claim 4, wherein the analog control delay line comprises a plurality of stages of delay cells connected in series, each delay cell comprises a first terminal and a second terminal, the first terminal of each delay cell is used for inputting the reference clock signal, the second terminal of each delay cell is used for inputting the first analog signal, the first analog signal is used for controlling the corresponding delay time of each delay cell, and the second delay time is the total delay time of the plurality of stages of delay cells.

6. The capacitance detection circuit of claim 4, wherein the first analog signal is an analog voltage and the analog control delay line is a voltage controlled delay line.

7. The capacitance detection circuit of the touch device according to claim 3, further comprising: and the processing unit is used for determining whether the capacitance value of the capacitor to be tested is changed relative to a basic capacitance according to the processed first digital signal output by the processing circuit when the delay phase-locked loop circuit is locked, wherein the basic capacitance is the capacitance value of the capacitor to be tested when the touch screen is not touched.

8. The capacitance detection circuit of the touch device according to claim 7, wherein the capacitor under test is formed by the detection electrode and the driving electrode in the touch screen, or the capacitor under test is formed by the detection electrode and an external object in the touch screen.

9. The capacitance detection circuit of claim 1, wherein some or all of the capacitance detection circuit is integrated into a touch sensing chip.

10. A touch device, comprising:

the touch screen comprises a capacitor to be tested;

the capacitance detection circuit as claimed in any one of claims 1 to 9, connected to the capacitor under test, for detecting a capacitance value of the capacitor under test.

11. An electronic device comprising the capacitance detection system of claim 10.