CN213398729U - Capacitance detection circuit of touch device, touch device and electronic equipment - Google Patents

Abstract

The application provides a capacitance detection circuit of a touch device. The capacitance detection circuit is connected to a capacitor to be tested in a touch screen of the touch device. The capacitance detection circuit includes: the CCO is used for generating a first clock signal according to the capacitance value of the capacitor to be measured; the DLL circuit comprises a digital phase discriminator and a digital control delay circuit, wherein a first input end of the digital phase discriminator is connected to an output end of the CCO, and a second input end of the digital phase discriminator is connected to an output end of the digital control delay circuit; the digital phase discriminator is used for outputting a first digital signal according to the first clock signal and a second clock signal output by the delay circuit controlled by the number; the digitally controlled delay circuit is configured to control a delay time of the second clock signal based on the first digital signal. The application also provides a touch device and an electronic device comprising the capacitance detection circuit.

Description

Capacitance detection circuit of touch device, touch device and electronic equipment

Technical Field

The embodiments of the present application relate to the field of capacitance detection, and more particularly, to a capacitance detection circuit, a capacitance detection system, and an electronic device.

Background

Capacitive touch devices are widely used in electronic devices, for example, as input devices to provide input information, such as position, motion, force, and duration. The core of a capacitive touch device is a capacitance detection circuit. In the related art of capacitance detection, capacitance detection based on a time domain is a mainstream detection method, and is specifically implemented by charging a capacitor to be detected, converting a charge amount of the capacitor to be detected into a voltage, or converting a variation amount of the charge charged by the capacitor to be detected into a voltage, and further processing the voltage to determine a capacitance value of the capacitor to be detected, for example, sampling the voltage by an Analog to Digital Converter (ADC) and converting the voltage into a Digital signal, and then performing capacitance detection according to the Digital signal. The capacitance detection by adopting the mode is influenced by circuit noise, and the detection precision of the capacitance detection is reduced.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a capacitance detection circuit of a touch device, the touch device and electronic equipment, which can reduce the influence of circuit noise on capacitance detection, thereby improving the detection precision of capacitance detection.

In a first aspect, the present application provides a capacitance detection circuit of a touch device, the touch device further includes a touch screen, the touch screen includes a plurality of capacitances to be measured, the capacitance detection circuit is connected to the capacitances to be measured, and the capacitance detection circuit includes:

the capacitance control oscillator CCO is used for generating a first clock signal according to the capacitance value of the capacitor to be detected, wherein the period of the first clock signal is positively correlated with the capacitance value of the capacitor to be detected;

a Delay Locked Loop (DLL) circuit, comprising: the digital phase detector comprises a first input end, a second input end and an output end, wherein the first input end of the digital phase detector is connected to the output end of the CCO, and the second input end of the digital phase detector is connected to the output end of the digitally controlled delay circuit;

the digital phase discriminator is used for receiving the first clock signal and a second clock signal output by the digitally controlled delay circuit, and outputting a first digital signal according to the phase deviation of the first clock signal and the second clock signal;

the digital control delay circuit is used for controlling the delay time of the second clock signal according to the first digital signal and outputting the second clock signal to a second input end of the digital phase discriminator;

when the DLL circuit is locked, the delay time between the second clock signal and the first clock signal is N periods of the first clock signal, N is a positive integer, and the first digital signal output by the digital phase detector is used for determining the capacitance value of the capacitor to be tested.

In some alternative implementations, the delay time between the second clock signal and the first clock signal is one cycle of the first clock signal when the DLL circuit is locked.

In some optional implementations, the capacitance detection circuit further includes:

the processing circuit is connected with the digital phase detector and the digitally controlled delay circuit and is used for receiving the first digital signal output by the digital phase detector, processing the first digital signal and outputting the processed first digital signal to the input end of the digitally controlled delay circuit, wherein the processed first digital signal is used for controlling the delay time of the second clock signal, and the processing comprises at least one of the following steps: integration processing, signal amplification or reduction processing, and filtering processing.

In some alternative implementations, the digitally controlled delay circuit includes:

the digital-to-analog converter DAC comprises an input end and an output end, the input end is connected to the output end of the processing circuit, the DAC is used for converting the first digital signal obtained through processing of the processing circuit into a first analog signal, and the output end of the DAC is used for outputting the first analog signal;

the first input end of the analog control delay line is connected to the output end of the DAC and used for receiving the first analog signal, the second input end of the analog control delay line is used for inputting the first clock signal, the analog control delay line is used for controlling the delay time of the second clock signal according to the first analog signal and the first clock signal, and the output end of the analog control delay line is used for outputting the second clock signal.

In some optional implementations, the analog control delay line includes a plurality of stages of delay cells connected in series, each delay cell includes a first terminal and a second terminal, the first terminal of each delay cell is used for inputting the first clock signal, the second terminal of each delay cell is used for inputting the first analog signal, the first analog signal is used for controlling a corresponding delay time of each delay cell, and a delay time of the second clock signal is a total delay time of the plurality of stages of delay cells.

In some optional implementations, the first analog signal is an analog voltage and the analog controlled delay line is a voltage controlled delay line VCDL.

In some optional implementations, the capacitance detection circuit further includes:

and the processing unit is used for determining whether the capacitance value of the capacitor to be tested is changed relative to a basic capacitance according to the processed first digital signal output by the processing circuit when the DLL is locked, wherein the basic capacitance is the capacitance value of the capacitor to be tested when the touch screen is not touched.

In some optional implementations, the capacitor to be tested is formed by a detection electrode and a driving electrode in the touch screen, or the capacitor to be tested is formed by a detection electrode and an external object in the touch screen.

In some alternative implementations, some or all of the capacitance detection circuit is integrated into a touch sensing chip.

In a second aspect, the present application provides a touch device comprising:

the touch screen comprises a capacitor to be tested; and

the capacitance detection circuit in the first aspect or any one of the optional implementations of the first aspect, the capacitance detection circuit is connected to the capacitor to be detected, and the capacitance detection circuit is configured to detect a capacitance value of the capacitor to be detected.

In a third aspect, an electronic device is provided, which includes the touch device in the second aspect.

Based on the above technical solution, by using the output clock signal of the capacitance controlled oscillator 11, i.e. the first clock signal, as the reference clock signal of the delay circuit 123 controlled digitally, the second clock signal related to the output clock signal of the capacitance controlled oscillator 11, i.e. the first clock signal CLK1, can be generated by the delay circuit 123 controlled digitally, and when the DLL circuit 12 is locked, the delay time of the second clock signal relative to the first clock signal is N cycles of the first clock signal. The period of the first clock signal CLK1 is positively correlated to the capacitance of the capacitor under test, and the delay time of the second clock signal CLK2 is controlled according to the first digital signal D1, so the first digital signal D1 is correlated to the capacitance of the capacitor under test 20, and thus the capacitance of the capacitor under test 20 can be determined according to the first digital signal D1.

Therefore, the clock signal of different cycles or frequency is produced based on different capacitance values to this application, further carries out the capacitance detection as the principle that the DLL circuit carries out the phase locking as the reference clock based on this clock signal, need not carry out the charge-discharge process of time domain to the condenser that awaits measuring, is favorable to reducing the influence of circuit noise to the capacitance detection process to can promote the precision that capacitance detection detected.

Drawings

Fig. 1 is a schematic configuration diagram of a capacitance detection device according to an embodiment of the present application.

Fig. 2 is a schematic block diagram of a digitally controlled delay circuit according to an embodiment of the present application.

Fig. 3 is a schematic circuit diagram of a voltage controlled delay line according to an embodiment of the present application.

Fig. 4 shows an exemplary configuration of a PLL circuit.

FIG. 5 is a schematic block diagram of a capacitive detection system according to an embodiment of the present application.

Fig. 6 is a schematic block diagram of an electronic device according to an embodiment of the application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter can be practiced without one or more of the specific details, or with other structures, components, and so forth. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring the invention.

Further, the following terms are exemplary and are not intended to be limiting in any way. After reading this application, those skilled in the art will recognize that these terms apply to techniques, methods, physical elements, and systems (whether currently known or not), including extensions thereof that may be inferred or inferred by those skilled in the art after reading this application.

Fig. 1 is a schematic block diagram of a capacitance detection circuit 10 according to an embodiment of the present application, the capacitance detection circuit 10 is connected to a capacitor 20 to be tested, as shown in fig. 1, the capacitance detection circuit 10 includes:

a capacitance controlled oscillator CCO11, configured to generate a first clock signal CLK1 according to a capacitance value of the capacitor 20 to be tested, where a period of the first clock signal CLK1 is positively correlated to the capacitance value of the capacitor 20 to be tested;

a Delay Locked Loop (DLL) circuit 12, comprising: a digital phase detector 121 and a digitally controlled delay circuit 123, wherein the digital phase detector 121 includes a first input 1211, a second input 1212 and an output 1213, the first input 1211 of the digital phase detector 121 is connected to the output of the CCO11, and the second input 1212 of the digital phase detector 121 is connected to the output of the digitally controlled delay circuit 123;

the digital phase detector 121 is configured to receive the first clock signal CLK1 and the second clock signal CLK2 output by the digitally controlled delay circuit 123, and output a first digital signal D1 according to the phase shift of the first clock signal CLK1 and the second clock signal CLK 2;

the digitally controlled delay circuit 123 is configured to control a delay time of the second clock signal CLK2 according to the first digital signal D1 and output the second clock signal CLK2 to the second input terminal 1212 of the digital phase detector 121;

when the DLL circuit 12 is locked, the delay time between the second clock signal CLK2 and the first clock signal CLK1 is N cycles of the first clock signal CLK1, where N is a positive integer, and the first digital signal D1 output by the digital phase detector 121 is used to determine the capacitance value of the capacitor 20 to be tested.

In the embodiment of the present application, the Capacitance Controlled Oscillator (CCO) 11 is an Oscillator Controlled by a capacitance value of the capacitor 20 to be measured, that is, a change in the capacitance value of the capacitor 20 to be measured can change an oscillation frequency or a period of the CCO11, specifically, the CCO11 can generate the first clock signal CLK1 according to the capacitance value of the capacitor 20 to be measured, a period of the first clock signal CLK1 is positively correlated with the capacitance value of the capacitor 20 to be measured, that is, the capacitance value of the capacitor 20 to be measured is larger, the period of the first clock signal CLK1 is larger, and vice versa, the period is smaller, in other words, the frequency of the first clock signal CLK1 is inversely correlated with the magnitude of the capacitance value of the capacitor 20 to be measured, that is the larger, the frequency of the first clock signal CLK1 is smaller, and the frequency is larger.

In the embodiment of the present application, the DLL circuit 12 is a negative feedback system, and the second clock signal CLK2 and the first clock signal CLK1 are controlled to perform clock phase alignment through a negative feedback mechanism, when the DLL circuit 12 is locked, or phase aligned, the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 is N cycles of the first clock signal CLK1, where N is a positive integer, and typically, N is 1. It is understood that the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 is N periods of the first clock signal CLK1, and it is understood that the phase misalignment of the first clock signal CLK1 and the second clock signal CLK2 is gradually reduced until disappears.

Specifically, the DLL circuit 12 includes a digital phase detector 121 and a digitally controlled delay circuit 123, and the digital phase detector 121 outputs a first digital signal D1 by detecting a phase relationship between a first clock signal CLK1 output from the capacitance controlled oscillator 11 and a second clock signal CLK2 output from the digitally controlled delay circuit 123, for example, if the first clock signal CLK1 is earlier than the phase of the second clock signal CLK2, the first digital phase detector 121 may output a1, or if the first clock signal CLK1 is later than the phase of the second clock signal CLK2, the first digital phase detector 121 may output a 0, or vice versa, as long as the adjustment logic of the delay time of the digitally controlled delay circuit 123 makes a corresponding adjustment.

Further, the input clock signal of the digitally controlled delay circuit 123 is configured to be the first clock signal CLK1, and then the digitally controlled delay circuit 123 may control the delay time of the second clock signal CLK2 according to the first clock signal CLK1 and the first digital signal D1 output by the digital phase detector 121, and output the delay-time-adjusted second clock signal CLK2 to the second input terminal 1212 of the digital phase detector 121.

The phase shift between the two clock signals is detected by the digital phase detector 121, a corresponding digital signal is output, and the digitally controlled delay circuit 123 further controls the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 according to the digital signal, so that finally the delay time between the first clock signal CLK1 and the second clock signal CLK2 is locked to N cycles of the first clock signal CLK, at which time the DLL 12 is stable, or locked, and the output of the digital phase detector 121 is also stable.

In a specific implementation, when the DLL circuit 12 is locked, the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 can be controlled to be one period of the first clock signal, that is, the second clock signal CLK2 is one clock period later than the first clock signal CLK1, in other words, the second clock signal CLK2 and the first clock signal CLK1 are phase-aligned, in this case, the operating state of the DLL circuit 12 is more stable, and accordingly, the output of the digital phase detector 121 is more stable. In the following, the embodiment of the present application is described by taking an example that the first clock signal and the second clock signal are different by one clock cycle, but the present application is not limited thereto.

In summary, the present application designs the output clock signal (i.e., the first clock signal) of the oscillator 11 as the reference clock signal of the delay circuit 123, so that the second clock signal related to the output clock signal of the oscillator 11 can be generated by the delay circuit 123, and the first clock signal and the second clock signal are different by one clock cycle when the DLL circuit 12 is locked.

As can be known from the operation principle of the capacitance controlled oscillator 11, the period of the first clock signal CLK1 is positively correlated to the capacitance value of the capacitor under test 20, and the delay time of the second clock signal CLK2 is controlled according to the first digital signal D1, so that the periods of the first digital signal D1 and the first clock signal CLK1 are correlated, and thus the first digital signal D1 is correlated to the capacitance value of the capacitor under test 20, so that the capacitance value of the capacitor under test 20 can be determined according to the first digital signal D1. Therefore, the clock signal of different cycles or frequency is produced based on different capacitance values to this application, further carries out the capacitance detection as the principle that the DLL circuit carries out the phase locking as the reference clock based on this clock signal, need not carry out the charge-discharge process of time domain to the condenser that awaits measuring, is favorable to reducing the influence of circuit noise to the capacitance detection process to can promote the precision that capacitance detection detected.

Optionally, the digital Phase Detector 121 may be implemented by a Binary Phase Detector (Binary PD), a Binary Phase Frequency Detector (Binary PFD), or other equivalent circuits, as long as the Phase offset between the signals can be converted into a digital signal to gradually approximate the Phase of the signal, which is not limited in this application.

Optionally, in some embodiments of the present application, as shown in fig. 1, the DLL circuit 12 may further include:

and a processing circuit 122, connected to the digital phase detector 121 and the digitally controlled delay circuit 123, for receiving the first digital signal D1 output by the digital phase detector 121, processing the first digital signal, and outputting the processed first digital signal D1 'to the digitally controlled delay circuit 123, so that the digitally controlled delay circuit 123 can control the delay time of the second clock signal CLK2 based on the processed first digital signal D1'.

In some embodiments of the present application, the processing of the first digital signal D1 by the processing circuit 122 includes, but is not limited to, at least one of: integration processing, enlargement or reduction processing, and filtering processing.

It is understood that different DLL circuits 12 correspond to corresponding performance indicators, such as capacitance range of the capacitor capable of being measured, stability, Signal Noise Ratio (SNR), etc., and the processing circuit 123 can perform corresponding processing on the first digital Signal according to the corresponding performance indicators to satisfy the performance indicators. In one implementation, the processing circuit 122 may perform integration processing on the first digital signal D1 output by the digital phase detector 121, further perform amplification or reduction processing so that the capacitance value of the capacitor to be detected falls within the capacitance value range of the capacitance detection circuit, and further perform filtering processing on the amplified or reduced digital signal. In another implementation, the processing circuit 122 may first perform amplification or reduction processing on the first digital signal D1, further perform integration processing, and finally perform filtering processing and then output the result to the delay circuit 123 of digital control, or may also perform other processing methods on the first digital signal D1, as long as the performance requirements of the DLL circuit 12 can be met, which is not limited in this application.

It should be understood that the use of the first digital signal D1 output by the digital phase detector 121 to determine the capacitance value of the capacitor under test 20 may refer to that the first digital signal may be directly used to determine the capacitance value of the capacitor under test 10, or may refer to a signal after the processing circuit 122 processes the first digital signal, that is, D1' may be used to determine the capacitance value of the capacitor under test.

It should also be understood that the use of the first digital signal D1 output by the digital phase detector 121 to determine the capacitance value of the capacitor under test 20 may include the use of the first digital signal D1 output by the digital phase detector 121 to determine a change in the capacitance value of the capacitor under test 20, or whether a change occurs, etc.

As can be known from the foregoing capacitance detection principle, the processed first digital signal D1 'can be used to control the delay time of the second clock signal CLK2, that is, the processed first digital signal D1' is related to the delay time of the second clock signal CLK2, and the delay time of the second clock signal CLK2 is related to the period of the first clock signal CLK1, so that the processed first digital signal D1 'is related to the period of the first clock signal CLK1, and the period of the first clock signal CLK1 is positively related to the capacitance value of the capacitor to be detected 20, so that the processed first digital signal D1' is related to the capacitance value of the capacitor to be detected 20. Therefore, the capacitance value of the capacitor 20 to be measured can be determined from the processed first digital signal D1'.

Optionally, in some embodiments, the capacitor under test 20 may be, for example but not limited to, a sensing element in a touch device, for example, a capacitor under test in a touch screen of a capacitive touch device, and specifically, the touch device includes a touch panel, which may also be referred to as a touch screen. The capacitor 20 to be tested is formed by a driving electrode and a detecting electrode on the touch panel, or the capacitor 20 to be tested may be formed by a detecting electrode on the touch panel and a ground, or the capacitor 20 to be tested may be formed by a detecting electrode on the touch panel and an external object. The external object is a conductor, such as but not limited to a finger of a user. In this scenario, the capacitance value of the capacitor 20 under test can be used to determine whether the touch device is touched, for example, whether the touch device is touched can be determined according to whether the capacitance value of the capacitor 20 under test is changed. Alternatively, whether the capacitance value of the capacitor 20 to be measured changes may be whether the capacitance value of the capacitor 20 to be measured changes relative to a base capacitance, where the base capacitance is a capacitance value of the capacitor 20 to be measured when the capacitor 20 to be measured is not contacted or approached by an external object, and the capacitance value may also be referred to as a nominal capacitance.

Optionally, in some embodiments of the present application, the capacitance detection circuit 10 may further include:

a processing unit, configured to determine whether a capacitance value of the capacitor under test 20 changes from a base capacitance according to the processed first digital signal D1' output by the processing circuit 122 when the DLL circuit is locked, where the base capacitance is a capacitance value of the capacitor under test 20 when the external object is not in contact with or close to the capacitor under test. For example, taking a touch device as an example, the base capacitance is a capacitance value of the capacitor 20 to be measured when a touch screen of the touch device is not touched by an external object.

Taking the capacitive touch detection scenario as an example, the processing unit may first determine that when the touch device of the touch device is not touched, the first digital signal output by the processing circuit 122 is recorded as a nominal digital signal D1 '_ REF, where the nominal digital signal D1' _ REF corresponds to the base capacitance C _ REF of the capacitor 20 to be tested, and the two signals may be converted through a specific relationship.

Further, whether the touch device is touched may be determined according to the processed first digital signal D1 ', for example, whether the touch device is touched may be determined according to a change of the first digital signal D1 ' output by the processing circuit 122 relative to a nominal digital signal D1 ' _ REF, and as an example, if the processed first digital signal D1 ' is changed relative to the nominal digital signal D1 ' _ REF or the change amount is greater than a certain threshold value, it may be determined that the touch device is touched, otherwise, it is determined that the touch device is not touched.

In other embodiments, the processed first digital signal D1' may be further processed and converted into a corresponding capacitance value C, and whether the touch device is touched may be further determined according to the capacitance value C. For example, whether the touch device is touched may be determined according to a change of the capacitance value C corresponding to the processed first digital signal D1' relative to a base capacitance C _ REF, and for example, if the capacitance value C corresponding to the processed first digital signal changes relative to the base capacitance C _ REF or the change is greater than a certain threshold, it may be determined that the touch device is touched, otherwise, it is determined that the touch device is not touched.

Optionally, in some embodiments, the processing unit may be a processing unit in a device or an apparatus in which the capacitance detection circuit 10 is installed, for example, if part or all of the capacitance detection circuit 10 may be integrated in a touch sensing chip of a touch apparatus, the touch sensing chip is electrically connected to a touch panel for driving the touch panel to perform a touch sensing operation. The processing unit may be a processing unit in the touch device, or may also be a main control module in an electronic device in which the touch device is located.

It should be understood that, in the embodiment of the present application, the digitally controlled delay circuit 123 may provide clock signals with different phases through the internal delay stages, and may be implemented by any circuit that controls delay time according to a digital signal, which is not limited in the embodiment of the present application.

A typical implementation of the digitally controlled delay circuit 123 is described below in conjunction with fig. 2. As shown in fig. 2, the digitally controlled delay circuit 123 includes:

a digital-to-analog converter DAC1231, including an input end and an output end, the input end being connected to the output end of the processing circuit 122, the DAC1231 being configured to convert the first digital signal D1' processed by the processing circuit 122 into a first analog signal a1, and the output end of the DAC1231 being configured to output the first analog signal a 1;

an analog control delay line 1232 comprising a first input terminal, a second input terminal and an output terminal, the first input terminal of the analog control delay line 1232 is connected to the output terminal of the DAC1231 for receiving the first analog signal a1, the second input terminal of the analog control delay line 1232 is used for inputting the first clock signal CLK1, the analog control delay line 1232 is used for controlling the delay time of the second clock signal CLK2 according to the first analog signal a1 and the first clock signal CLK1, and the output terminal of the analog control delay line 1232 is used for outputting the second clock signal CLK 2.

In some embodiments, the first analog signal a1 may be an analog Voltage or an analog Current, and correspondingly, the analog Controlled Delay Line 1232 may be a Voltage Controlled Delay Line (VCDL) or a Current Controlled Delay Line (CCDL). A typical implementation of the analog controlled delay line 1232 will be described below by taking the first analog signal as an analog voltage as an example, but it is needless to say that the implementation may be realized in other ways, and the implementation is not limited herein.

As shown in fig. 3, the analog control delay line 1232 includes a plurality of stages of delay cells 12321 connected in series, each delay cell 12321 includes a first terminal and a second terminal, the first terminal of each delay cell 12321 is used for inputting the first clock signal CLK1, the second terminal of each delay cell 12321 is used for inputting the first analog signal (taking the first analog signal as an analog voltage V-REF as an example), the first analog signal V-REF is used for controlling a corresponding delay time of each delay cell 12321, and the delay time of the second clock signal CLK2 is a total delay time of the plurality of stages of delay cells.

Specifically, each stage of delay unit of the VCDL may output a certain phase offset, the degree of the phase offset output by each stage of delay unit of the VCDL is controlled by the analog voltage V-REF, and the total delay time of all the delay units constitutes the delay time of the VCDL, i.e., the delay time of the second clock signal CLK 2. The first clock signal CLK1 and the second clock signal CLK2 are phase-compared by the digital phase detector 121, and corresponding digital signals are output, and the digital signals are further processed and converted into analog signals, such as an analog voltage V-REF, which is used to change the delay time of the delay cells in the VCDL.

In some embodiments, analog controlled delay line 1232 may implement a delay cell with an inverter while an active state machine is used to select the output signal.

In particular, a single delay cell in the VCDL represents a minimum delay time, such as that of one elementary inverter, and since each inverter can shift the phase by 180 degrees, the VCDL can output at an even number of inverters to provide a corresponding phase. The VCDL needs to select a signal having a phase closest to that of the first clock signal CLK1 as an output clock signal for feedback. Therefore, the output signal to be implemented in the VCDL is not necessarily the last stage output of the VCDL, i.e. the second clock signal is not necessarily output at the last stage of the VCDL, but it is necessarily output at the position closest to the phase of the first clock signal CLK1, and the corresponding signal can be generated by an active state machine to select the output signal.

In a specific implementation, the delay of each delay unit has a certain relationship with the RC time constant in the delay unit. The larger the time constant, the larger the delay, and the delay of each stage of delay unit can be adjusted by changing the time constant of the delay unit, such as the impedance R or the load capacitor C.

Therefore, in the embodiment of the present application, by inputting the output clock of the CCO11 as a reference clock into the analog control delay line 1232, the delay time of the output second clock signal CLK2 can be correlated with the period of the first clock signal CLK1, and the delay time of the second clock signal CLK2 is controlled by the first analog signal a1, so that the periods of the first analog signal a1 and the first clock signal CLK1 can be correlated, further, the first analog signal a1 is obtained according to the processed first digital signal D1 ', so that the processed first digital signal D1 ' is correlated with the period of the first clock signal CLK1, that is, the capacitance value of the capacitor under test 20, and therefore, the processed first digital signal D1 ' can be used to determine the change of the capacitance value of the capacitor under test 20, the specific determination manner can refer to the related description of the foregoing embodiments.

In other embodiments, the locking of the phase of the second clock signal may also be implemented by a PLL circuit, for example, as shown in fig. 4, the PLL circuit 40 includes a digital phase frequency detector 41, a digital filter 42 and a digitally controlled oscillator DCO43, and the specific connection relationship is similar to that of the digital phase detector 121, the processing circuit 122 and the digitally controlled delay circuit 123 in the DLL circuit 12 in fig. 1, but the operation principle is different.

Specifically, the digital phase frequency detector 41 may receive the first clock signal CLK1 and the second clock signal CLK2 output from the DCO43, and output a first digital signal D1 according to a frequency and phase difference therebetween, the first digital signal D1 may further be filtered by the digital filter 42, the filtered first digital signal D1 'is input to the DCO43, the DCO43 may output the second clock signal CLK2 according to the filtered first digital signal D1', and when the frequencies and phases of the second clock signal CLK2 and the first clock signal CLK1 are infinitely close, the PLL40 circuit is locked, and at this time, the output of the digital filter 42 is also stable.

The DCO43 is typically implemented by a DAC (Voltage Controlled Oscillator, VCO), which functions as the DAC1231 in the previous embodiment, and a Voltage Controlled Oscillator (VCO), which can output a clock signal with a certain frequency and phase according to an analog signal output by the DAC, such as an analog Voltage, and the PLL circuit 40 locks when the clock signal infinitely approaches the input clock signal of the DCO 43.

In the PLL circuit 40, the frequency difference between the first clock signal CLK1 and the second clock signal CLK2 is related to the first digital signal D1, and the period of the first clock signal CLK1 is positively related to the capacitance value of the capacitor under test 20, so that the capacitance value of the capacitor under test 20 can also be determined according to the first digital signal, for example, the first digital signal filtered by the digital filter 42 can be integrated to determine the capacitance value of the capacitor under test 20.

However, in practical applications, the VCDL in the DLL circuit and the VCO in the PLL circuit are main noise contributors, and if the noise of the VCDL and the VCO can be reduced, the overall noise of the system can be reduced. Due to the difference of the working principles of the two, the phase noise generated by the VCDL in the DLL circuit cannot be accumulated, and the VCO in the PLL circuit usually accumulates more phase noise, so that the noise generated by the VCDL is lower than that generated by the VCO, and the capacitance detection realized by the DLL circuit is more favorable for reducing the system noise, so that the detection precision can be improved.

The present application further provides a capacitance detection system 40, as shown in fig. 5, the capacitance detection system 40 includes: the capacitor 41 to be detected and the capacitance detection circuit 42, the capacitance detection circuit 42 is connected to the capacitor 41 to be detected, and the capacitance detection circuit 42 is used for detecting the capacitance value of the capacitor 41 to be detected.

Optionally, in some embodiments, the capacitance detection system 40 is a touch device, and the capacitance value of the capacitor 41 to be tested is used for determining whether the touch device is touched.

Optionally, the touch device includes, for example, a capacitive touch screen and a capacitance detection circuit 42. For example, the capacitive touch screen includes a mutual capacitive touch screen or a self-capacitive touch screen.

In a mutual capacitance-based touch system, a touch screen can include, for example, drive and sense regions, such as drive lines (or drive electrodes) and sense lines (or detection electrodes). As one example, the drive lines can form multiple rows and the sense lines can form multiple columns (e.g., orthogonal). Touch pixels can be disposed at intersections of rows and columns. During operation, the rows can be stimulated with an alternating current signal (AC) waveform, and mutual capacitances can be formed between rows and columns of the touch pixels. When an object is in proximity to the touch pixel, some of the charge coupled between the rows and columns of the touch pixel may instead be coupled to the object. This reduction in charge coupled onto the touch pixel can result in a net reduction in the mutual capacitance between rows and columns and a reduction in the AC waveform coupled onto the touch pixel. This reduction in the charge-coupled AC waveform can be detected and measured by a touch system to determine whether there is a touch, and the location of the object on the touch screen. For a mutual capacitance touch screen, the capacitor 20 to be tested is formed by the detection electrode and the driving electrode on the mutual capacitance touch screen.

In a self-capacitance based touch system, each touch pixel can be formed by an individual electrode that forms a self-capacitance to ground. When an object is close to the touch pixel, another capacitance to ground (capacitance to ground) may be formed between the object and the touch pixel. The further capacitance to ground may result in a net increase in the self-capacitance experienced by the touch pixel. This increase in self-capacitance can be detected and measured by the touch system to determine whether there is a touch, and the location of the object when touching the touch screen. For a self-contained touch screen, the capacitor 20 to be tested is formed by a detection electrode on the touch screen and the ground, or the capacitor 20 to be tested is formed by a detection electrode on the touch screen and an external object. Such as, but not limited to, a conductive object such as a user's finger.

The touch panel of the touch device can be a touch screen externally hung above the display panel, and can also be integrated in the display panel (Incell), and the like, and the technical schemes are within the protection scope of the application.

Additionally, the capacitance detection system 40 may also be a fingerprint sensing device. Accordingly, the capacitance detection circuit 42 is a capacitance detection circuit in a fingerprint sensing device. The capacitor 41 to be tested is a capacitor to be tested in the fingerprint sensing device.

However, the capacitance detection system 40 may be modified, and is not limited to the touch device or the fingerprint sensing device.

Fig. 6 shows a schematic structural diagram of an electronic device 50 according to an embodiment of the present application, and as shown in fig. 6, the electronic device 50 may include a capacitance detection system 51, where the capacitance detection system 51 may be the capacitance detection system 40 in fig. 5.

It should be understood that the electronic device 50 of the present embodiment may include, but is not limited to, a smart phone, a tablet, a computer, a laptop, a smart wearable device, a smart door lock, etc. In order to realize the basic functions of the electronic device, the electronic device in the embodiments of the present application may include other necessary modules or components in addition to the modules or components illustrated above. Taking the electronic device as a smart phone as an example, it may further include a communication module, a speaker, a microphone, a battery, and the like.

The processing unit may be an integrated circuit chip having signal processing capability. In the implementation process, the steps executed by the processing unit can be completed by hardware integrated logic circuits or instructions in the form of software in the processor. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. The utility model provides a touch device's capacitance detection circuit, touch device still includes the touch-sensitive screen, the touch-sensitive screen includes a plurality of capacitors that await measuring, capacitance detection circuit is connected to the capacitor that awaits measuring, its characterized in that, capacitance detection circuit includes:

the capacitance control oscillator is used for generating a first clock signal according to the capacitance value of the capacitor to be detected, wherein the period of the first clock signal is positively correlated with the capacitance value of the capacitor to be detected;

a delay locked loop circuit comprising: the digital phase detector comprises a first input end, a second input end and an output end, wherein the first input end of the digital phase detector is connected to the output end of the capacitance control oscillator, and the second input end of the digital phase detector is connected to the output end of the digital control delay circuit;

the digital phase discriminator is used for receiving the first clock signal and a second clock signal output by the digitally controlled delay circuit, and outputting a first digital signal according to the phase deviation of the first clock signal and the second clock signal;

the digital control delay circuit is used for controlling the delay time of the second clock signal according to the first digital signal and outputting the second clock signal to a second input end of the digital phase discriminator;

when the delay phase-locked loop circuit is locked, the delay time between the second clock signal and the first clock signal is N, the period of the first clock signal is N, N is a positive integer, and the first digital signal output by the digital phase discriminator is used for determining the capacitance value of the capacitor to be measured.

2. The capacitance detection circuit according to claim 1, wherein a delay time between the second clock signal and the first clock signal is one cycle of the first clock signal when the delay locked loop circuit is locked.

3. The capacitance detection circuit according to claim 1, further comprising:

the processing circuit is connected with the digital phase detector and the digitally controlled delay circuit and is used for receiving the first digital signal output by the digital phase detector, processing the first digital signal and outputting the processed first digital signal to the input end of the digitally controlled delay circuit, wherein the processed first digital signal is used for controlling the delay time of the second clock signal, and the processing comprises at least one of the following steps: integration processing, signal amplification or reduction processing, and filtering processing.

4. The capacitance detection circuit of claim 3, wherein the digitally controlled delay circuit comprises:

the digital-to-analog converter comprises an input end and an output end, the input end is connected to the output end of the processing circuit, the digital-to-analog converter is used for converting the first digital signal obtained by processing of the processing circuit into a first analog signal, and the output end of the digital-to-analog converter is used for outputting the first analog signal;

the analog control delay line comprises a first input end, a second input end and an output end, wherein the first input end of the analog control delay line is connected to the output end of the digital-to-analog converter and used for receiving the first analog signal, the second input end of the analog control delay line is used for inputting the first clock signal, the analog control delay line is used for controlling the delay time of the second clock signal according to the first analog signal and the first clock signal, and the output end of the analog control delay line is used for outputting the second clock signal.

5. The capacitance detection circuit according to claim 4, wherein the analog control delay line comprises a plurality of stages of delay cells connected in series, each delay cell comprises a first terminal and a second terminal, the first terminal of each delay cell is used for inputting the first clock signal, the second terminal of each delay cell is used for inputting the first analog signal, the first analog signal is used for controlling the corresponding delay time of each delay cell, and the delay time of the second clock signal is the total delay time of the plurality of stages of delay cells connected in series.

6. The capacitance detection circuit of claim 4, wherein the first analog signal is an analog voltage and the analog controlled delay line is a voltage controlled delay line.

7. The capacitance detection circuit of claim 3, further comprising:

and the processing unit is used for determining whether the capacitance value of the capacitor to be tested is changed relative to a basic capacitance according to the processed first digital signal output by the processing circuit when the delay phase-locked loop circuit is locked, wherein the basic capacitance is the capacitance value of the capacitor to be tested when the touch screen is not touched.

8. The capacitance detection circuit according to claim 7, wherein the capacitor under test is formed by the detection electrode and the driving electrode in the touch screen, or the capacitor under test is formed by the detection electrode and the ground in the touch screen, or the capacitor under test is formed by the detection electrode and an external object in the touch screen.

9. The capacitance detection circuit of claim 1, wherein some or all of the capacitance detection circuit is integrated into a touch sensing chip.

10. A touch device, comprising:

the touch screen comprises a capacitor to be tested;

the capacitance detection circuit as claimed in any one of claims 1 to 9, connected to the capacitor under test, for detecting a capacitance value of the capacitor under test.

11. An electronic device characterized by comprising the touch device recited in claim 10.

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