JP2000298532A - Timing control circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly execute phase synchronization, to adjust a phase difference without depending on an output load based on clock signal distribution or the like and to attain low skew and low power consumption in a timing control circuit for synchronizing a phase difference between an input clock signal and an output clock signal. SOLUTION: The timing control circuit device is constituted of a rough timing control circuit CDLL11 for roughly adjusting a phase difference between an input clock signal and an output clock signal, a fine timing control circuit FDLL11 for finely adjusting the phase difference and a rough/fine conversion circuit CONV11 for transmitting a clock signal from the circuit CDLL11 to the circuit FDLL11. The circuit FDLL11 highly accurately adjusts the phase difference between an input clock signal clkin11 and an output clock signal clkout11 by using a roughly adjusted signal to remove the phase difference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a timing control circuit for generating, transmitting or distributing a synchronization signal.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a phase locked loop (PLL),
A delay locked loop (DLL) is used. 1995 International Solid State Circuits Conference Digest of Technical Papers (1995) pp. 112-113 (19
95 International Solid-State Circuits Conference,
As described in Digest of Technical Papers, pp.112-113), PLL requires a long settling time (several tens of microseconds) for the clock signal to synchronize and generate a stable signal output. I need. Similarly, the 1998 International Solid State Circuits
Conference Digest of Technical Papers (1998) 158 to 159 (1998 Interna
tional Solid-State Circuits Conference, Digest of
As described in Technical Papers, pp.158-159), the DLL has a long settling time (locking time) of about 100 clock cycles. Usually, when a system using a semiconductor integrated circuit device enters a standby state, a PLL
Alternatively, stop the DLL and reduce the power consumed by the PLL and DLL. However, as described above, returning the PLL or DLL from the standby state to the operating state requires a long settling time. Therefore, depending on the system, to avoid this long settling time, the PLL
Others have a sleep mode that does not stop the DLL. In this sleep mode, power is consumed by the PLL or DLL.

[0003] As a method of solving the above-mentioned disadvantages peculiar to PLLs and DLLs, 1997 Symposium on VISI Circuits Digest of Technical Papers (1997), pp. 109 to 110 (1997 Symposium).
on VLSI Circuits, Digestof Technical Papers, p
p.109-110), the synchronous mirror delay (S
MD) has been proposed. The SMD has a short settling time of two clock cycles. In the SMD, a dummy delay circuit simulating an output load is prepared, and a clock signal is synchronized using the dummy delay circuit. Therefore, when the output load is unknown,
If it changes, it cannot respond. To solve the shortcomings of SMD, proceedings of the 1998
・ Custom Integrated Circuits Conference (1998) pp. 511-514 (Proceeding)
s of the 1998 Custom Integrated Circuits Conferenc
e, pp.511-514), direct SMD (D-SMD) was proposed. However, in both SMDs, only an extreme signal having a duty ratio of the output clock signal of about 1/10 can be obtained, and cannot be used in a system using both the rising and falling edges of the clock signal.

[0004]

[Problems to be solved by the invention]
-250728, a timing control circuit device that overcomes all the disadvantages of PLL, DLL, SMD and D-SMD was developed. In this device, the settling time is as short as two to three cycles of the clock signal, the clock signal can be synchronized regardless of changes in the output load, and the duty ratio of the output clock signal can be set to 1/1. .

FIG. 3 or FIG. 4 shows that the applicants filed Japanese Patent Application No. 10-250.
728 shows the configuration of the timing control circuit device proposed in 728. The input clock signal clkin31 is connected to the buffer circuit BUF31,
Delayed clock signal dclk3 via delay control circuit row DCL31
Output as 1 to output clock driver DRV31 or capacitive load
An output clock signal clkout31 passes through the LD 31 to supply a clock signal to a system or the like. Input clock signal clkin31
The period of the clock is Tin and the delay time of the clock driver DRV31 is Tdrv
Then, the forward delay circuit train FDA31 and the control circuit MCC
31 and the control signal storage circuit REG31 are provided with the delayed clock signal dclk3.
1 and the phase difference between the output clock signal clkout31 and Tfd
The position of the delay element in the forward delay circuit array FDA31 where a = Tin-Tdrv is determined. This position is the delay control circuit row DC
Informed to L31, the delay time in DCL31 is Tdcl = Tfda = Tin
The position that becomes -Tdrv is selected. Then, the delay time from the input clock signal clkin31 to the output clock signal clkout31 is Tout = Tdcl + Tdrv = Tin, and a clock signal that is exactly one cycle delayed from the input is output.

As described above, in the timing control circuit for synchronizing the clock signals, the settling time is 2-3 times.
The cycle is short, and the output load (here, DRV31 or LD31)
Can be generated, and the duty ratio of the input clock signal can be transmitted as it is. Alternatively, a signal having an arbitrary duty ratio can be output by adjusting the delay element DEL31. The minimum clock frequency at which the timing control circuit device can operate can be given by Fmin = 1 / (n × Tdel). The maximum value of the skew with respect to the input signal indicated by the clock signal generated by this device is Smax = Tdel. Here, n is a delay element in the delay control circuit sequence DCL31.
The number of stages of the DEL31, Tdel, is the delay time of the delay element DEL31 per stage. As can be seen from these relationships, in this timing control circuit device, in order to reduce the skew Smax without changing the minimum operation frequency Fmin, it is necessary to reduce the delay time Tdel per delay element in one stage. The number n of element stages increases. Conversely, if the number n of delay elements is reduced without changing the minimum operation frequency Fmin, the skew Smax increases. Since the area and power consumption of the circuit depend on the number n of the delay elements, there is a trade-off between the skew representing the performance of the device and the area / power consumption.

[0007] The object of the present invention is to solve the above-mentioned Japanese Patent Application No. 10-250728.
Another object of the present invention is to improve the timing control circuit device proposed in (1), and to provide a timing control circuit device with low skew, low area and low power consumption.

That is, in the timing control circuit device, the settling time is short, synchronization can be performed even when the load of the clock buffer or the like changes, the duty ratio of the output clock signal can be adjusted, and the skew of the output clock signal can be adjusted. Another object of the present invention is to provide a timing control circuit device capable of simultaneously reducing the area and the power consumption.

[0009]

In order to solve the above problems, a reference clock signal is input to a timing control circuit device, an internal clock signal is generated using the reference clock signal, and further passed through a load circuit such as a clock driver circuit. To generate an output clock signal. At this time, the output clock signal is fed back and input to the timing control circuit device, and the internal clock signal is generated so that the output clock signal and the reference clock signal have the same phase.

The timing control circuit device includes a circuit for detecting a phase difference between the internal clock and the output clock and a delay circuit for controlling the amount of delay, and the delay circuit controls the amount of delay based on the detected phase difference. Can be changed. As a result, the output clock signal and the reference clock signal can be in phase.

The timing control circuit device is composed of a coarse timing control circuit and a fine timing control circuit. The coarse timing control circuit synchronizes the phases of the output clock signal and the reference clock signal with low accuracy, and the fine timing control circuit uses high timing. Synchronize the phases of the output clock signal and the reference clock signal with high accuracy. The skew of the generated output clock signal is determined by the delay element in the fine adjustment timing control circuit, and the skew can be reduced by reducing the delay amount per delay element stage. The circuit scale of the timing control circuit can be arbitrarily increased or decreased by the ratio of the delay amount of the delay element in the coarse adjustment timing control circuit to the delay element in the fine adjustment timing control circuit. Can be reduced.

According to the embodiment of the present invention, the settling time for stabilizing the output of the clock signal is short. As a result, the power can be reduced by operating the semiconductor circuit device only when necessary, and the power supply voltage can be reduced. Japanese Patent Application Laid-Open No. H10-210, which is able to suppress deterioration of the control accuracy of the output signal due to the above-mentioned factors and to cope with a load change in the load circuit of the clock output.
A timing control circuit device having the characteristics of the -250728 timing control circuit device and capable of simultaneously realizing low skew, low area, and low power consumption can be provided.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

In the following description, the delay time of the buffer circuit, the offset circuit, the n-input NOR circuit, and the frequency divider circuit is smaller than the delay times of the other components, and can be ignored for convenience of explanation. It is assumed that this is the case.

The input clock signal clkin21 is inputted to the coarse timing control circuit CDLL21, and the delayed clock signal dclk23
And control signals cntsig21 and cntsig22. The coarse adjustment fine conversion circuit CONV21 receives the control signals cntsig21 and cntsig22 output from the coarse adjustment timing control circuit CDLL21, and generates and transmits a delay clock signal dclk22 for the fine adjustment timing control circuit. The fine timing control circuit FDLL21 receives the delayed clock signals dclk22 and dclk23, newly generates and outputs a delayed clock signal dclk21. The clock driver DRV21 receives the delayed clock signal dclk21, and distributes the clock signal to the capacitive load LD21 as the output clock signal clkout21. The output clock signal clkout21 returns to the coarse timing control circuit CDLL21 again. The coarse timing control circuit CDLL21 includes a delay control circuit row DCL22, a forward delay circuit row FDA22, a control circuit MCC22, and a control signal storage circuit REG22.
And buffer circuits BUF21, BUF24, BUF25, n input NO
R circuit NNOR22, frequency divider DIV22, offset adjustment circuit offs
It consists of et21. Clock driver delay time
Assuming Tdrv, the delay time between the delayed clock signal dclk21 and the output clock signal clkout21 is Tdrv. In the coarse timing control circuit CDLL21, the output clock signal clkout
21 is input to the forward delay circuit array FDA22 after being received by the offset circuit offset21, and the delayed clock signal dclk21 is input to the control circuit MCC22 after being received by the buffer circuit BUF25. When the clock cycle of the input clock signal clkin21 is Tin, the control circuit MCC22 detects a position where the delay clock signal of the forward delay circuit array FDA22 satisfies the delay time Tfda = Tin−Tdrv. The control signal storage circuit REG22 includes a control circuit MCC.
The position detected by 22 is stored.

The timing for performing the storage is determined by the frequency dividing circuit DIV22.
Depending on the timing at which the delayed clock signal dclk21 is divided. The divider circuit DIV22 generates the internal clock signal inclk22, and passes through the buffer circuit BUF24 to the control signal storage circuit REG.
A signal is supplied to the control circuit 22 to store the detection position of the control circuit MCC22. The stored control signal cntsig22 is a delay control circuit train
The delay transmission position of DCL22 is determined, and the input clock signal clkin21 input through the buffer circuit BUF21 is converted to Tdcl = Tfda = T
It is sent for the delay time of in-Tdrv and output as a delay signal dclk23. When the delay signal dclk23 passes through the delay control circuit array DCL21 in the fine adjustment timing control circuit FDLL21 without delay, the delay time of the output clock signal clkout21 becomes Tout = Tdcl + Tdrv = Tin, and just the input clock signals clkin21 and clkin21 A signal that is delayed in the cycle will be transmitted,
The phases of the input signal and the output signal are synchronized. n-input NOR circuit NN
The OR22 allows the input clock signal clkin21 to be transmitted as the delay clock signal dclk23 without passing through the delay control circuit train when no delay position is selected at the time of circuit startup or the like. Also, offset circuit offset21
Is a delay element existing inside the timing control circuit device for guaranteeing a self-delay.

However, the delay time actually selected by the delay control circuit row DCL22 is a discontinuous digital quantity, and the delay time per one delay element constituting the delay control circuit row DCL22 depends on the phase between input and output signals. It remains as an error (skew).
Therefore, the phase error is fine-tuned by the timing control circuit FDLL.
Adjust with 21. The coarse adjustment fine conversion circuit CONV21 receives the delay clock signal transmitted to the position selected by the forward delay circuit array FDA22 as a control signal cntsig21, and forward delay circuit array FDA21 in the fine adjustment timing control circuit FDLL21.
As a delayed clock signal dclk22.

The delay signal dclk23 obtained by coarsely adjusting the input clock signal clkin21 by the delay control circuit row DCL22 is similarly transmitted to the delay control circuit row DCL21 in the fine adjustment timing control circuit FDLL21. Fine adjustment timing control circuit FDLL2
Within 1, the same timing control as that of the coarse adjustment timing control circuit CDLL21 is performed, and a finely adjusted delay signal dclk21 is output. By the above operation, the input clock signal clkin21 and the output clock signal clkout21 are
Synchronization can be achieved within the delay time of one delay element constituting the delay control circuit array DCL21 in the FDLL 21.

For example, the cycle of the input clock signal is 10 ns
(Frequency 100 MHz). Fine timing control circuit CDLL
Assuming that the delay time of one delay element constituting the delay control circuit array DCL22 in 1 is 1 ns, in order to synchronize this input clock signal without using a load circuit or a clock driver, a ten-stage delay element is required. Is required, and the maximum skew Smax at this time is 1 ns. Fine adjustment timing control circuit FDLL2
In 1, assuming that the delay time of one delay element constituting the delay control circuit array DCL21 is 100 ps, 10 delay elements are also required, and the maximum skew Smax = 100 ps. The number of stages of the delay element can be constituted by a total of 20 stages. On the other hand, when the timing control circuit device of Japanese Patent Application No. 10-250728 attempts to synchronize an input clock signal of 10 ns, if the number of delay elements is configured as 20, the maximum skew Smax = 50
Increases to 0ps. Alternatively, to achieve the maximum skew Smax = 100 ps, 100 stages of delay elements are required, and the circuit scale, area, and power consumption increase. Therefore, using the circuit in this embodiment, Japanese Patent Application No. 10-25072
The skew can be reduced and the circuit size, area, and power consumption can be reduced at the same time while maintaining the same features as the timing control circuit device of FIG.

FIG. 1 is a diagram showing a detailed embodiment of the present invention.

The forward delay circuit arrays FDA11 and FDA12 can be formed by AND circuits. Each of the control circuits MCC11 and MCC12 includes an RS flip-flop circuit RSFF11, an inverter circuit, and a NOR circuit. The control signal storage circuits REG11 and REG12 are composed of D-type flip-flop circuits DFF11. Delay control circuit row D
CLs 11 and 12 are composed of AND circuits and NAND circuits. The coarse / fine conversion circuit CONV11 can be constituted by a switch using a MOS transistor. FIG. 5 shows an embodiment of the buffer circuits BUF11, 12, 13, 14, 15, FIG. 6 shows an embodiment of the n-input NOR circuits NNOR11 and 12, and FIG. 7 shows an embodiment of the D-type flip-flop circuit DFF11. Figure 8 shows the RS flip-flop circuit RS
FIG. 9 shows an embodiment of the frequency divider circuits DIV11 and 12 and FIG.
FIG. 10 shows an embodiment of the offset circuit offset11.

FIG. 11 is a diagram showing another embodiment of the present invention.

The n-input NOR circuit existing in the coarse adjustment timing control circuit and the fine adjustment timing control circuit is the NNOR 111 of FIG.
It can also be configured as follows. In this case, although the delay time increases as an n-input NOR, an OR circuit can be arranged at each output of the control signal storage circuit, so that the layout can be simplified and the layout area can be reduced.

FIG. 13 is a diagram showing another embodiment of the present invention.

The coarse / fine conversion circuit can be constituted by a MOS transistor switch like CONV121 in FIG.
When configured using a tri-state buffer circuit like ONV131, the delayed clock signal from the forward delay circuit
The load on fda131-136 can be reduced. FIG. 14 shows an embodiment of the tri-state buffer circuit TSB141.

FIG. 15 is a diagram showing another embodiment of the present invention.

When the / Q output cntsig 151 of the D-type flip-flop circuit forming the control signal storage circuit REG151 is connected to the input of the AND circuit forming the forward delay circuit array FDA151, the position after the position selected by the control signal storage circuit REG151 is connected. The clock signal is not transmitted to the AND circuit in the forward delay circuit row FDA151 (the left stage in the figure). Thereby, the operating power can be reduced.

FIG. 16 is a diagram showing another embodiment of the present invention.

When an AND circuit is formed at the output of the D-type flip-flop circuit forming the control signal storage circuit REG161 as shown in the figure, when an arbitrary one of the D-type flip-flops is selected, the output of the D-type flip-flop is arranged at a stage subsequent thereto. All D-type flip-flops in the left column in the figure are not selected. That is, the control signal storage circuit REG161 does not select two locations at the same time. If two locations are selected at the same time, two locations are selected in the delay control circuit row, and synchronization is lost and a through current may flow, which is prevented.

FIG. 17 is a diagram showing another embodiment of the present invention.

In the timing control circuit device, the delay control circuit array DCL172 in the coarse adjustment timing control circuit CDLL171 is composed of m stages of delay elements, and the fine adjustment timing control circuit FDLL1
It is assumed that the delay control circuit sequence DCL171 in 71 is constituted by delay element j stages. First, it is assumed that the k-th stage of the delay control circuit array DCL172 and the first stage of the delay control circuit array DCL171 are selected as a combination for achieving synchronization during operation of the device. During operation, the delay time of a load circuit such as a clock driver changes due to temperature rise, etc.
If the position of the delay element selected in the first stage increases from the first stage to the second stage and the third stage, it moves to the j-th stage, and in order to move further, the selected position of the delay control circuit row DCL172 is changed. It is necessary to move from the kth stage to the k + 1st stage. At this time, if the position selected in the delay control circuit row DCL171 remains at the j-th stage, the delay time corresponding to one delay element of the delay control circuit row DCL172 having a large delay time appears as skew. To prevent this, when the delay element selection position of DCL172 changes, DC
The delay element selection position of L171 is forcibly determined. For example, when the number of delay elements of the DCL 172 increases from the k-th stage to the k + 1-th stage, the DCL 171 forcibly selects the first-stage delay element. An embodiment of a circuit that realizes this function is shown in the FMDE, CMD, and CMDH circuits of FIGS. 22, 23, and 24. FMDE, CM
When the delay element of DCL172 (delay element in CMD in FIG. 22) changes by each signal of fdmax, fdmin, and fix generated by D and CMDH, the delay element of DCL171 (delay element in FMD in FIG. 22) ) The selection position is forcibly determined.

FIG. 18 is a diagram showing another embodiment of the present invention.

The delay control circuit sequence DCL11 shown in FIG. 1 is composed of a delay sequence of an AND circuit and a selector of a NAND circuit. If the selector is configured by a NAND circuit in this way, a hazard may occur when the delay selection position changes. FIG. 19 is a timing chart showing the relationship between the clock signals. As shown in the chart of FIG. 19A, while the input clock signal clkin191 is in the high period, the internal clock inclk191
When the delay selection position changes here, a hazard is generated in the output clock signal clkout191. As shown in FIG. 19 (b), when the rising edge of the internal clock inclk192 occurs while the input clock signal clkout192 is in the low period, the hazard cannot be generated. As shown in FIG. 18, when the selector circuit is configured by the tri-state buffer circuit TSB181, the hazard does not occur as shown in FIGS. 19 (c) and (d).

FIG. 21 is a diagram showing another embodiment of the present invention.

In the timing control circuit device having the configuration shown in FIG. 20, the input clock signal clk201 passes through the buffer circuit BUF201, and then passes through the selector SEL201 composed of a tristate buffer circuit in the delay control circuit train DCL201.
The signal is transmitted through the AND delay element array and becomes a delay signal dclk201. This signal is frequency-divided by the frequency dividing circuit DIV201 to become the internal clock signal inclk201. In this case, the selector SE
Since the relationship between the timing of the clock signal transmitted through L201 and the timing at which the output of the control signal storage circuit REG201 is determined by the internal clock signal inclk201 changes according to the selection position of the selector SEL201, the timing relationship becomes uncertain, and FIG. In the same manner as described above, there is a possibility of causing a problem such as a hazard. To solve this problem, the delay control circuit array DCL211 may be configured as shown in FIG. DCL211
Then, the delay sequence by the AND circuit is received first, including the input clock signal clkin211 and transmitted to the selected position, and the delay signal dclk211 is output through the selector SEL211 by the tristate buffer circuit. In this case, there is almost no shift in the timing from the position selected by the selector SEL211 to the time when the frequency dividing circuit DIV211 generates a signal, so that the timing relationship can be determined.

FIG. 22 is a diagram showing another embodiment of the present invention.

The timing control circuit device shown in FIG. 22 has a circuit configuration incorporating all the embodiments described above. With this circuit, a clock synchronization circuit with low skew and low power consumption can be realized. 22, the embodiment of the FMDH, FMD and FMDE circuits, FIG. 24 shows the embodiment of the CMDH and CMD circuits, FIG. 25 shows the embodiment of the CG circuit, FIG. 26 shows the SC and FIG. 27 shows an embodiment of the SCE circuit, FIG. 27 shows an embodiment of the FF circuit, and FIG. 28 shows an embodiment of the DV2 circuit.

[0039]

As described above, the present invention has the following effects. That is, in a timing control circuit device that generates an output clock signal synchronized with an input clock signal, a synchronous clock signal is stably generated in a short time, and the synchronization signal is supplied independently of a load such as an output buffer of the clock signal. it can. Therefore, it is possible to design even if the clock distribution buffer circuit is unknown, and it is possible to cope with a change in the load of the clock distribution buffer and the like after the design. Be adaptable. Furthermore, by optimizing the delay amount of the delay elements in the coarse timing control circuit and the fine timing control circuit, the circuit size, area, and power consumption can be reduced while reducing the skew of the generated clock signal. Becomes

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a timing control circuit device developed in Japanese Patent Application No. 10-250728.

FIG. 4 is a configuration diagram of a timing control circuit device developed in Japanese Patent Application No. 10-250728.

FIG. 5 is a buffer circuit diagram.

FIG. 6 is an n-input NOR circuit diagram.

FIG. 7 is a D-type flip-flop circuit diagram.

FIG. 8 is an RS flip-flop circuit diagram.

FIG. 9 is a frequency division circuit diagram.

FIG. 10 is an offset circuit diagram.

FIG. 11 is an n-input NOR circuit diagram.

FIG. 12 is a circuit diagram of a coarse adjustment / fine adjustment conversion circuit.

FIG. 13 is a circuit diagram of a coarse / fine conversion circuit.

FIG. 14 is a circuit diagram of a tristate buffer.

FIG. 15 is a configuration diagram of another embodiment of the present invention.

FIG. 16 is a configuration diagram of another embodiment of the present invention.

FIG. 17 is an operation relation diagram of another embodiment of the present invention.

FIG. 18 is a configuration diagram of another embodiment of the present invention.

FIG. 19 is an operation waveform of another embodiment of the present invention.

FIG. 20 is a configuration diagram of another embodiment of the present invention.

FIG. 21 is a configuration diagram of another embodiment of the present invention.

FIG. 22 is a configuration diagram of another embodiment of the present invention.

FIG. 23 is a configuration diagram of an embodiment of an FMDH, FMD, and FMDE circuit.

FIG. 24 is a configuration diagram of an embodiment of a CMDH and a CMD circuit.

FIG. 25 is a configuration diagram of an embodiment of a CG circuit.

FIG. 26 is a configuration diagram of an embodiment of an SC and SCE circuit.

FIG. 27 is a configuration diagram of an embodiment of an FF circuit.

FIG. 28 is a configuration diagram of an embodiment of a DV2 circuit.

[Explanation of symbols]

BUF11, BUF12, BUF13, BUF14, BUF15, BUF21, BUF22, B
UF23, BUF24, BUF25, BUF31, BUF32, BUF33, BUF41, BU
F42, BUF43, BUF51, BUF201, BUF202, BUF203, BUF21
1, BUF212, BUF213: Buffer circuits CDLL11, CDLL21, CDLL171, CDLL221: Coarse adjustment timing control circuit CONV11, CONV21, CONV121, CONV131: Coarse adjustment fine adjustment circuit DCL11, DCL12, DCL21, DCL22, DCL31, DCL41, DCL171,
DCL172, DCL181, DCL201, DCL211: Delay control circuit array DFF11, DFF31, DFF71: D-type flip-flop circuit DIV11, DIV12, DIV21, DIV22, DIV31, DIV41, DIV91:
Divider circuit DRV11, DRV21, DRV31, DRV41, DRV201, DRV211, DRV22
1: Clock driver circuit FDA11, FDA12, FDA21, FDA22, FDA31, FDA41, FDA151,
FDA201, FDA211: Forward delay circuit train FDLL11, FDLL21, FDLL171, FDLL221: Fine timing control circuit LD11, LD21, LD31, LD41, LD201, LD211: Capacitive load MCC11, MCC12, MCC21, MCC22, MCC31, MCC41, MCC151,
MCC201, MCC211: Control circuits NNOR11, NNOR12, NNOR21, NNOR22, NNOR31, NNOR41, NN
OR61, NNOR111: n-input NOR circuit offset11, offset21, offset31, offset41, offset1
01: Offset circuit REG11, REG12, REG21, REG22, REG31, REG41, REG151,
REG161, REG171, REG172, REG181, REG201, REG211: Control signal storage circuit RSFF11, RSFF31, RSFF81: RS flip-flop circuit SEL201, SEL211: Selector TSB131, TSB141, TSB181: Tri-state buffer cntsig21, cntsig22, cntsig151: Control signal clkin11 , Clkin21, clkin31, clkin41, clkin191,
clkin192, clkin193, clkin194, clkin201, clkin2
21, clkin221: input clock signals clkout11, clkout21, clkout31, clkout41, clkout19
1, clkout192, clkout193, clkout194, clkout221: output clock signals dclk11, dclk12, dclk13, dclk21, dclk22, dclk23, dc
lk31, dclk41, dclk151, dclk221: delayed clock signal fda121, fda122, fda123, fda124, fda125, fda12
6, fda131, fda132, fda133, fda134, fda135, fd
a136: Forward delay circuit train output signal inclk11, inclk21, inclk22, inclk191, inclk192, i
nclk193, inclk194: Internal clock signals reg121, reg122, reg123, reg124, reg125, reg12
6, reg131, reg132, reg133, reg134, reg135, re
g136: Control signal storage circuit output signal CG, CMD, CMDH, FMD, FMDE, FMDH, FF, DIV2, SC, SC
E: circuit elements constituting the embodiment of FIG.

Continuing on the front page (72) Inventor Kiyoshi Hasegawa 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Co., Ltd. (72) Inventor Yu Kokubo Higashi Koigakubo, Kokubunji-shi, Tokyo 1-280, Hitachi Central Research Laboratory Co., Ltd. (72) Inventor Kowawa Aoki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In-house Hitachi, Ltd.Semiconductor Group (72) Inventor Koichiro Ishibashi Kokubunji, Tokyo 1-280 Higashi-Koigakubo F-term in Hitachi Central Research Laboratory, Ltd. (Reference)

Claims (16)

[Claims] A first logic circuit for receiving a first clock signal and outputting a second clock signal; a second logic circuit for receiving the second clock signal and outputting a third clock signal; A third logic circuit for transmitting a fifth clock signal between the first logic circuit and the second logic circuit, and a load circuit for receiving the third clock signal and outputting a fourth clock signal; And the first logic circuit feeds back the fourth clock signal and the second clock signal so that the phases of the first clock signal and the fourth clock signal are synchronized with a first accuracy. Generating a clock signal, wherein the second logic circuit generates the third clock signal such that the phases of the first clock signal and the fourth clock signal are synchronized with a second accuracy. Timing control circuit device. 2. The first logic circuit detects a first phase difference between the fourth clock signal and the third clock signal, and generates a first control signal based on the first phase difference. The first logic circuit comprises a first delay circuit row and a second delay circuit row whose delay time can be changed by the first control signal, and the second logic circuit comprises the fifth clock signal and the third clock signal. And a third delay circuit that generates a second control signal based on the second phase difference and a delay time that can be changed by the second control signal. 4.The timing according to claim 1, wherein the third logic circuit is configured to transmit the fifth clock signal from the first logic circuit to the second logic circuit. Control circuit device. 3. The first and third delay circuit rows include a forward delay circuit, a control circuit, and a control signal storage circuit, and the forward delay circuit includes an inverter, an AND or an OR.
The control circuit is mainly composed of an inverter, a NOR and a flip-flop circuit, the control signal storage circuit is mainly composed of a flip-flop circuit, and the second and fourth delay circuit columns are composed of an inverter and a NAND.
Or consist of AND and NAND or OR and NOR circuits,
3. The timing control circuit device according to claim 1, wherein the third logic circuit includes a switch using a MOS transistor. 4. The first clock signal and the fourth clock signal are composed of pulses of a synchronization signal having a fixed period, and the fourth clock signal is delayed by a desired number of pulses from the first clock signal. 4. The timing control circuit device according to claim 1, wherein the phases are synchronized. 5. The third clock signal is fed back to the first logic circuit as the fourth clock signal via the load circuit, and the load of the load circuit changes statically or dynamically. The phase of the first clock signal and the phase of the fourth clock signal are synchronized even when the delay time between the third clock signal and the fourth clock signal changes accordingly. Item 5. The timing control circuit device according to any one of Items 1 to 4. 6. The timing control circuit device according to claim 1, wherein the phases of the first clock signal and the fourth clock signal are synchronized after a desired number of pulses. . 7. A delay amount of a delay element forming the forward delay circuit in the third delay circuit row is longer than a delay amount of a delay element forming the forward delay circuit in the first delay circuit row. 7. Small, characterized by being small
The timing control circuit device according to any one of the above. 8. The apparatus according to claim 1, wherein said third logic circuit is constituted by a tri-state buffer circuit.
The timing control circuit device according to any one of the above. 9. A storage signal generated by the control signal storage circuit in the first and third delay circuit arrays is provided to a forward delay circuit, and a delay element constituting the forward delay circuit is moved from an arbitrary position. 8. The timing control circuit device according to claim 1, wherein transmission of a clock signal is stopped at a subsequent stage. 10. A storage signal generated by the control signal storage circuit in the first and third delay circuit arrays outputs a selection signal only at an arbitrary position, and otherwise outputs a non-selection signal. 8. The timing control circuit device according to claim 1, wherein: 11. A storage signal generated by the control signal storage circuit in the first and third delay circuit arrays outputs a selection signal only at an arbitrary position, and outputs a non-selection signal otherwise. 8. The timing control circuit device according to claim 1, wherein: 12. The load of the load circuit changes statically or dynamically, and the delay time between the third clock signal and the fourth clock signal changes accordingly. The position of the delay element selected in the fourth delay circuit row is determined to be an arbitrary position when the position of the delay element selected in (1) changes.
The timing control circuit device according to any one of the above. 13. The method according to claim 1, wherein said second and fourth delay circuit trains comprise an inverter and a tri-state buffer, an AND and a tri-state buffer, or an OR and a tri-state buffer circuit. A timing control circuit device according to any one of the above. 14. In the second and fourth delay circuit arrays,
The first and second clock signals are provided by an inverter or AN
Input to the delay train composed of D or OR circuit, NAND
8. The timing control circuit according to claim 1, wherein the timing control circuit outputs the second and third clock signals via a selector configured by a NOR or a tri-state buffer circuit. apparatus. 15. At least three synchronization circuits and at least two
A synchronous signal transmission circuit, wherein the synchronous circuit
The synchronizing signal transmission circuit has the same function as the first or second logic circuit according to any one of claims 1 to 15, and the synchronization signal transmission circuit has the same function as the third logic circuit according to claim 1 to 15, A timing control circuit device, wherein a delay amount of the delay elements constituting the delay circuit row in a circuit differs for each of the synchronous circuits. 16. A coarse adjustment timing control circuit for coarsely adjusting the phase difference between an input clock signal and an output clock signal, a fine adjustment timing control circuit for finely adjusting the phase difference between an input clock signal and an output clock signal, and the coarse adjustment timing. A coarse / fine conversion circuit for transmitting a clock signal from the control circuit to the fine timing control circuit; each timing control circuit includes a forward delay circuit train for outputting an input signal from an arbitrary position thereof; A coarse control timing control circuit that adjusts the phase difference between the input clock signal and the output clock signal with coarse precision, and the coarse fine control conversion circuit performs coarse adjustment. The fine adjustment timing control circuit transmits the input clock signal and the output clock signal using the coarsely adjusted signal. A timing control circuit apparatus characterized by adjusting a phase difference between the signals with high accuracy.