CN114006837A - Error code testing method and device for network port of intelligent network card and intelligent network card - Google Patents

Error code testing method and device for network port of intelligent network card and intelligent network card Download PDF

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Publication number
CN114006837A
CN114006837A CN202111242090.1A CN202111242090A CN114006837A CN 114006837 A CN114006837 A CN 114006837A CN 202111242090 A CN202111242090 A CN 202111242090A CN 114006837 A CN114006837 A CN 114006837A
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Prior art keywords
prbs
network port
cpu
code stream
prbs code
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CN202111242090.1A
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CN114006837B (en
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孙崇雨
高磊
刘齐
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H04L43/0847—Transmission error
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Abstract

The application relates to an error code testing method and device for a network port of an intelligent network card and the intelligent network card. The error code testing method of the network port of the intelligent network card comprises the following steps: when the first network port and the second network port are in a communication connection state, the CPU controls a PRBS code element generator in the programmable device to generate a first PRBS code stream; the PHY controller is controlled to send the first PRBS code stream to the second network port through the first network port, and the received second PRBS code stream is controlled to be transmitted to the PRBS code element checker for code element check; the method comprises the steps of obtaining a check result of a PRBS code element checker, determining the error rate of a first network port or/and a second network port according to the check result, automatically testing the error rate of the network port of the intelligent network card through a programmable device integrated in the intelligent network card and a CPU (central processing unit), and improving the test efficiency of the error rate of the network port of the intelligent network card.

Description

Error code testing method and device for network port of intelligent network card and intelligent network card
Technical Field
The present application relates to the field of computer technologies, and in particular, to an error code testing method and apparatus for a network port of an intelligent network card, and an intelligent network card.
Background
The intelligent network card can unload the network message processing work of the server onto the network card for processing, and has the functions of safety unloading, storage unloading, control management and the like, thereby fully releasing the computing resources of the CPU of the server host. In the data center, the server is connected with the switch through the intelligent network card. The network data port of the intelligent network card is used as an important ring of a communication link, and the stability of the port communication quality has very important significance. An important index for measuring the stability of port communication quality is the bit error rate of the port, so how to test the bit error rate of the port becomes a problem to be solved at present.
At present, the bit error rate of a port of an intelligent network card is tested, a bit error rate tester is often used for carrying out error code testing, and testing equipment comprises a code pattern generator and an error code detector. The code generator sends out the appointed PRBS (Pseudo-Random Binary Sequence) code pattern to the port of the intelligent network card, the PRBS code pattern is looped back through the PHY (Physical) layer of the intelligent network card, and then the error code detector detects the error code.
The test scheme needs manual operation of an instrument, and due to the complex operation of test equipment, error code testing can not be flexibly and rapidly performed on a network port in the production, operation and maintenance, fault diagnosis and other links of the intelligent network card, and the test efficiency is low.
Disclosure of Invention
Therefore, it is necessary to provide an error code testing method and apparatus for a network port of an intelligent network card and the intelligent network card in order to solve the above technical problems.
A method for testing error codes of network ports of an intelligent network card is provided, wherein a programmable device and a CPU which are connected through a bus are integrated in the intelligent network card, the programmable device is connected with a first network port and a second network port, the programmable device comprises a PHY controller and a PRBS controller, the PRBS controller comprises a PRBS code element generator and a PRBS code element checker, and the method comprises the following steps:
when the first network port and the second network port are in a communication connection state, the CPU controls a PRBS code element generator in the programmable device to generate a first PRBS code stream;
the CPU controls the PHY controller to send the first PRBS code stream to a second network port through a first network port, and controls the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for code element check;
and the CPU acquires the check result of the PRBS code element checker and determines the error rate of the first network port or/and the second network port according to the check result.
In one embodiment, the check result includes the number of error symbols, the CPU obtains the check result of the PRBS symbol checker, and determines the bit error rate of the first network port or/and the second network port according to the check result, including:
and the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the first PRBS code stream, or the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the second PRBS code stream.
In one embodiment, the check result includes the number of error symbols, the CPU obtains the check result of the PRBS symbol checker, and determines the bit error rate of the first network port or/and the second network port according to the check result, including:
and the CPU acquires the port rate from the PHY controller and determines the bit error rate according to the number of error code elements, the interface rate and the test duration.
In one embodiment, the above-mentioned PHY controller includes a physical medium related layer, and the CPU controls the PHY controller to send the first PRBS code stream to the second network port through the first network port, and controls the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for code element check, including:
the CPU controls the physical medium related layer to modulate the first PRBS code stream;
and the CPU controls the physical medium related layer to send the modulated code stream to a second network port through the first network port, and controls the physical medium related layer to demodulate the received second PRBS code stream and then transmit the second PRBS code stream to the PRBS code element checker for code element check.
In one embodiment, the PHY controller includes an additional layer of physical media, and the method further includes:
the CPU controls the PHY controller to load the first PRBS code stream onto the additional layer of the physical medium;
the CPU controls the physical medium additional layer to carry out serial processing on the first PRBS code stream to obtain a serial bit stream, and controls the physical medium additional layer to send the serial bit stream to a physical medium related layer;
the CPU controls the physical medium related layer to modulate the first PRBS code stream, and the method comprises the following steps:
the CPU controls the physical medium dependent layer to modulate the serial bit stream.
In one embodiment, the programmable device is an FPGA, or/and the programmable device is connected to the CPU through a pci bus;
in one embodiment, the first network port and the first network port are connected via a wired communication medium.
In one embodiment, the register of the PHY controller and the register of the PRBS controller are configured in a mem space of the pce bus, a test script runs on the CPU, the test script generates a first PRBS code stream by controlling the register of the PRBS controller and performs symbol verification on a second PRBS code stream, and the test script further controls the register of the PHY controller to send the first PRBS code stream to the second network port through the first network port.
In one embodiment, the CPU is connected to a maintenance interface.
The utility model provides an error code testing arrangement, its characterized in that error code testing arrangement is integrated in intelligent network card, still integrate in the intelligent network card and pass through the programmable device of bus and error code testing arrangement connection, programmable device is connected with first network port and second network port, programmable device includes PHY controller and PRBS controller, PRBS controller includes PRBS code element generator and PRBS code element checker, error code testing arrangement includes:
the first control unit is used for controlling a PRBS code element generator in the programmable device to generate a first PRBS code stream when the first network port and the first network port are in a communication connection state;
the second control unit is used for controlling the PHY controller to send the first PRBS code stream to a second network port through a first network port and controlling the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for checking;
and the processing unit is used for acquiring the check result of the PRBS code element checker and determining the error rate of the first network port or/and the second network port according to the check result.
An intelligent network card is characterized by comprising a programmable device and a CPU which are connected through a bus, wherein the programmable device is connected with a first network port and a second network port, the programmable device comprises a PHY controller and a PRBS controller, and the PRBS controller comprises a PRBS code element generator and a PRBS code element checker;
the CPU is used for controlling a PRBS code element generator in the programmable device to generate a first PRBS code stream when the first network port and the first network port are in a communication connection state;
the CPU is also used for controlling the PHY controller to send the first PRBS code stream to a second network port through a first network port and controlling the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for checking;
the CPU is also used for obtaining the check result of the PRBS code element checker, and determining the error rate of the first network port or/and the second network port according to the check result.
The error code testing method and device for the network port of the intelligent network card and the intelligent network card are characterized in that a programmable device and a CPU which are connected through a bus are integrated in the intelligent network card, the programmable device is connected with a first network port and a second network port, the programmable device comprises a PHY (physical layer) controller and a PRBS (pseudo random binary system) controller, the PRBS controller comprises a PRBS code element generator and a PRBS code element checker, and the method comprises the following steps: when the first network port and the second network port are in a communication connection state, the CPU controls a PRBS code element generator in the programmable device to generate a first PRBS code stream; the CPU controls the PHY controller to send the first PRBS code stream to a second network port through a first network port, and controls the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for code element check; the CPU obtains the check result of the PRBS code element checker, determines the error rate of the first network port or/and the second network port according to the check result, automatically tests the error rate of the network port of the intelligent network card through the programmable device integrated in the intelligent network card and the CPU, does not need to manually operate a test instrument for testing, solves the problem of low test efficiency caused by the complexity of the operation of the test instrument in the prior art, and improves the test efficiency of the error rate of the network port of the intelligent network card.
Drawings
FIG. 1 is a diagram of an application environment of an error code testing method for a network port of an intelligent network card in an embodiment;
fig. 2 is a schematic flow chart illustrating an error code testing method for a network port of an intelligent network card in an embodiment;
FIG. 3 is a block diagram of an embodiment of an error code tester;
fig. 4 is an internal structural diagram of the intelligent network card in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1, fig. 1 is a schematic view of an application environment of an error code testing method for an intelligent network card network port according to an exemplary embodiment of the present application. As shown in fig. 1, the application environment includes an intelligent network card 1, a programmable device 12 and a CPU13 connected through a bus 11 are integrated in the intelligent network card 1, the programmable device 12 is connected to a first network port 14 and a second network port 15, the programmable device 12 includes a PHY controller 16 and a PRBS controller 17, and the PRBS controller 16 includes a PRBS symbol generator (not shown) and a PRBS symbol checker (not shown), so as to implement the error code testing method for the intelligent network card network port of the present application.
The CPU13 is configured to control the PRBS symbol generator in the programmable device 12 to generate a first PRBS code stream when the first network port 14 and the second network port 15 are in a communication connection state; the PHY controller 16 is controlled to send the first PRBS code stream to the second network port 15 through the first network port 14, and the PHY controller 16 is controlled to transmit the received second PRBS code stream to the PRBS code element checker for code element check; and acquiring a check result of the PRBS code element checker, and determining the error rate of the first network port 14 or/and the second network port 15 according to the check result.
The PRBS code stream generator in the programmable device 12 is controlled by the CPU13 to generate a first PRBS code stream, and the PHY controller 16 in the programmable device 12 is controlled by the CPU13 to send the first PRBS code stream to the second network port 15 through the first network port 14, and transmit the received second PRBS code stream to the PRBS code stream checker for code check.
The first network port 14 and the second network port 15 are used for transmitting a first PRBS code stream or receiving a second PRBS code stream.
Bus 11 is used to enable communication connections between CPU13 and programmable machine 12. The bus 11 may be a PCIe bus.
In an embodiment, as shown in fig. 2, a method for testing an error code of a network port of an intelligent network card is provided, where a programmable device and a CPU connected through a bus are integrated in the intelligent network card, the programmable device is connected to a first network port and a second network port, the programmable device includes a PHY controller and a PRBS controller, the PRBS controller includes a PRBS symbol generator and a PRBS symbol checker, and the method is applied to the CPU in fig. 1 as an example to be described, and includes the following steps:
and S11, when the first network port and the second network port are in a communication connection state, the CPU controls a PRBS code element generator in the programmable device to generate a first PRBS code stream.
The intelligent network card integrates a programmable device and a CPU. Two network ports on the intelligent network card, a first network port and a second network port are led out by a programmable device, and a customized logic circuit is operated on the programmable device. And a PHY controller and a PRBS controller are integrated in the programmable device. The bus may be a PCIe bus.
Among them, a programmable device (PLD) is produced as a general-purpose integrated circuit, and its logic function is determined according to the programming of the device by a user. The first network port and the second network port are connected to the PHY controller, and specifically, the first network port and the second network port may be connected to each other through a high-speed cable DAC (direct cable) or an AOC (active optical cable). The first PRBS code stream is a Pseudo-random binary sequence of Pseudo-random binary sequence.
Further, the PRBS symbol generator is configured to generate a first PRBS code stream. The PRBS code element checker is used for checking the code stream received by the second network port. Specifically, the CPU operates the PRBS controller in the programmable device through the PCIe read-write tool, and starts a PRBS code element generator in the PRBS controller to generate a first PRBS code stream.
The first network port and the second network port can be connected in a wired or wireless mode, so that the first network port and the second network port are in a communication connection state. When the second network port and the second network port are in a communication connection state, the generated first PRBS code stream may be sent from the first network port to the second network port.
And S12, the CPU controls the PHY controller to send the first PRBS code stream to the second network port through the first network port, and controls the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for code element check.
The CPU operates the PHY controller and the PRBS controller in the programmable device through a PCIe read-write tool. After the CPU controls a code element generator in the PRBS controller to generate a first PRBS code stream, the PHY controller is controlled to send the generated first PRBS code stream to a second network port through a first network port, and the PHY controller is further controlled to transmit a second PRBS code stream received by the second network port to a PRBS code element checker in the PRBS controller to carry out code element check. The PHY controller is connected with the first network port and the second network port, so that the PHY controller can control the generated first PRBS code stream to be sent to the second network port through the first network port, acquire a second PRBS code stream received in the second network port, and transmit the second PRBS code stream to a PRBS code element checker in the PRBS controller for code element check.
Specifically, when the PRBS code element checker checks the second PRBS code stream, the received second PRBS code stream may be compared with the first PRBS code stream during transmission, so as to obtain the number of wrong code element bits.
S13, the CPU obtains the check result of the PRBS code element checker, and determines the error rate of the first network port or/and the second network port according to the check result.
The check result may include the number of error symbols, i.e., the number of error symbol bits. When determining the error rates of the first network port and/or the second network port according to the check result, the error rates of the first network port and/or the second network port may be specifically determined according to the number of erroneous symbol bits.
In the application, when the first network port is a sending port, the second PRBS code stream received by the second network port can be acquired for verification. When the second network port is a sending port and the first network port is a receiving port, the second PRBS code stream received by the first network port can be acquired for verification.
In one embodiment, the check result includes the number of error symbols, and the obtaining, by the CPU, the check result of the PRBS symbol checker, and determining the bit error rate of the first network port or/and the second network port according to the check result may include:
and the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the first PRBS code stream, or the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the second PRBS code stream.
Specifically, in an embodiment, the determining, by the CPU, the bit error rate according to the number of error symbols and the total number of symbols of the first PRBS code stream may include:
and the CPU determines the error rate according to the ratio of the number of the error code elements to the total code element number of the first PRBS code stream.
The determining, by the CPU, the bit error rate according to the number of error symbols and the total number of symbols of the second PRBS code stream may include:
and the CPU determines the error rate according to the ratio of the number of the error code elements to the total code element number of the second PRBS code stream.
According to the method and the device, the bit error rate is automatically generated, and the test instrument does not need to be operated manually to test the bit error rate.
In one embodiment, the check result includes the number of error symbols, and the obtaining, by the CPU, the check result of the PRBS symbol checker, and determining the bit error rate of the first network port or/and the second network port according to the check result may include:
and the CPU acquires the port rate from the PHY controller and determines the bit error rate according to the number of error code elements, the interface rate and the test duration.
The PRBS code element checker detects the received second PRBS code stream and counts the number of all error code elements received by the second network port;
the testing process continuously runs for a plurality of clock cycles, after the specified time is reached, the CPU controls to close the PRBS code element generator, stops the sending of the PRBS code stream signal, and counts a time period from the time when the PRBS code element generator is started to generate the code element to the time when the PRBS code element generator is closed as the testing time.
And the CPU reads the bit number of the error code element counted by the PRBS code element checker in the programmable device through the PCIe bus, namely the number of the error code elements. Further, the CPU obtains a port rate from the PHY controller, and determines an error rate according to the number of error symbols, the interface rate, and the test duration, where the error rate may be obtained by using the following calculation formula:
error rate is the number of error symbols/(port rate x test time)
According to the method and the device, the accuracy of the error rate can be improved by adjusting the test time, and the flexibility of the scheme is realized.
In one embodiment, the above-mentioned PHY controller includes a physical medium related layer, and the above-mentioned CPU controls the PHY controller to send the first PRBS code stream to the second network port through the first network port, and controls the PHY controller to transmit the received second PRBS code stream to the PRBS symbol checker for symbol checking, which may include:
the CPU controls the physical medium related layer to modulate the first PRBS code stream;
and the CPU controls the physical medium related layer to send the modulated code stream to a second network port through the first network port, and controls the physical medium related layer to demodulate the received second PRBS code stream and then transmit the second PRBS code stream to the PRBS code element checker for code element check.
The PHY controller comprises a physical medium related layer which is used for modulating and demodulating the first PRBS code stream so as to enable the signal to be suitable for being transmitted in the high-speed cable.
In one embodiment, the PHY controller includes an additional layer of physical media, and the method further includes:
the CPU controls the PHY controller to load the first PRBS code stream onto the additional layer of the physical medium;
the CPU controls the physical medium additional layer to carry out serial processing on the first PRBS code stream to obtain a serial bit stream, and controls the physical medium additional layer to send the serial bit stream to a physical medium related layer;
the above-mentioned controlling, by the CPU, the physical medium related layer to modulate the first PRBS code stream may include:
the CPU controls the physical medium dependent layer to modulate the serial bit stream.
In this application, the PHY controller further includes an additional layer of physical media for serializing the data sequence to generate a serial bit stream. And the CPU controls and controls the physical medium additional layer to carry out serial processing on the first PRBS code stream to obtain a serial bit stream, and then controls and controls the physical medium additional layer to send the serial bit stream to the physical medium related layer so that the physical medium related layer can modulate the serial bit stream. According to the method and the device, the first PRBS code stream is subjected to serial processing through the physical medium additional layer to obtain the serial bit stream, so that subsequent processing of the first PRBS code stream is facilitated, processing operations such as modulation and transmission are facilitated, and the calculation efficiency of the bit error rate is improved.
In one embodiment, the programmable device is an FPGA, or/and the programmable device is connected to the CPU through a pci bus;
in one embodiment, the first network port and the first network port are connected via a wired communication medium.
The fpga (field programmable gate array) is a programmable logic array. The wired communication may be through a high-speed Cable DAC (direct Cable) or AOC (active optical cables).
In another embodiment, the first network port and the second network port may be connected wirelessly.
In one embodiment, the register of the PHY controller and the register of the PRBS controller are configured in a mem space of the pce bus, a test script runs on the CPU, the test script generates a first PRBS code stream by controlling the register of the PRBS controller and performs symbol verification on a second PRBS code stream, and the test script further controls the register of the PHY controller to send the first PRBS code stream to the second network port through the first network port.
When the FPGA instantiates the IP core, after the PHY controller is generated, the control register inside the PHY controller needs to be mounted on the PCIe controller inside the FPGA, and the specific position should be placed in the mem space of the PCIe controller, that is, the register of the PHY controller and the register of the PRBS controller are configured in the mem space of the PCIe bus. The CPU will automatically scan for PCIe devices during the BIOS (basic input output system) phase. An FPGA belongs to a PCIe device for a CPU. And after the BIOS is scanned, obtaining a register configured on the PCIemem space by the FPGA.
Further, the CPU controls the PHY controller and the PRBS controller through a register of the PHY controller and a register of the PRBS controller, respectively.
In one embodiment, the CPU is connected to a maintenance interface.
The CPU runs a general operating system, and provides a maintenance port in a serial port communication mode, which is used for man-machine interaction of intelligent network card equipment, such as setting some parameters.
In one embodiment, as shown in fig. 3, an error code testing apparatus is provided, where the error code testing apparatus is integrated in an intelligent network card, a programmable device connected to the error code testing apparatus through a bus is further integrated in the intelligent network card, the programmable device is connected to a first network port and a second network port, the programmable device includes a PHY controller and a PRBS controller, the PRBS controller includes a PRBS symbol generator and a PRBS symbol checker, and the error code testing apparatus includes:
the first control unit 11 is configured to control a PRBS symbol generator in the programmable device to generate a first PRBS code stream when the first network port and the first network port are in a communication connection state;
the second control unit 12 is configured to control the PHY controller to send the first PRBS code stream to the second network port through the first network port, and control the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for checking;
and the processing unit 13 is configured to obtain a check result of the PRBS symbol checker, and determine the bit error rate of the first network port or/and the second network port according to the check result.
In one embodiment, the check result includes the number of error symbols, and the processing unit 13 may determine the error rate according to the number of error symbols and the total number of symbols of the first PRBS code stream, or the CPU may determine the error rate according to the number of error symbols and the total number of symbols of the second PRBS code stream.
In one embodiment, the check result includes the number of error symbols, and the processing unit 13 may obtain the port rate from the PHY controller, and determine the bit error rate according to the number of error symbols, the interface rate, and the test duration.
In one embodiment, the PHY controller includes a physical medium related layer, the second control unit 12 may control the physical medium related layer to modulate the first PRBS code stream, and the CPU controls the physical medium related layer to send the modulated code stream to the second network port through the first network port, and controls the physical medium related layer to demodulate the received second PRBS code stream and transmit the demodulated second PRBS code stream to the PRBS code element checker for code element check.
In one embodiment, the PHY controller includes an additional layer of a physical medium, the error code device further includes a loading unit (not shown), the loading unit may control the PHY controller to load the first PRBS code stream onto the additional layer of the physical medium, the CPU controls the additional layer of the physical medium to perform serial processing on the first PRBS code stream to obtain a serial bit stream, and controls the additional layer of the physical medium to send the serial bit stream to a layer related to the physical medium, and the second control unit 12 may control the layer related to the physical medium to modulate the serial bit stream.
In one embodiment, the programmable device is an FPGA, or/and the programmable device and the CPU are connected through a pci bus.
In one embodiment, the first network port and the first network port are connected via a wired communication medium.
In one embodiment, the register of the PHY controller and the register of the PRBS controller are configured in a mem space of the pce bus, the CPU runs a test script, the test script generates a first PRBS code stream by controlling the register of the PRBS controller and performs symbol verification on a second PRBS code stream, and the test script further controls the register of the PHY controller to send the first PRBS code stream to the second network port through the first network port.
In one embodiment, the CPU is connected to a maintenance interface.
In one embodiment, as shown in fig. 4, an intelligent network card 41 is provided, which is characterized by comprising a programmable device 43 and a CPU44 connected through a bus 42, wherein the programmable device 43 is connected with a first network port 45 and a second network port 46 with respect to the FPGA in the figure, the programmable device 43 comprises a PHY controller 47 and a PRBS controller 48, and the PRBS controller 48 comprises a PRBS symbol generator (not shown) and a PRBS symbol checker (not shown);
the CPU44 is configured to control the PRBS symbol generator in the programmable device 43 to generate a first PRBS code stream when the first network port and the first network port are in a communication connection state;
the CPU44 is further configured to control the PHY controller 47 to send the first PRBS code stream to the second network port 46 through the first network port 45, and control the PHY controller 47 to transmit the received second PRBS code stream to the PRBS symbol checker for checking;
the CPU44 is further configured to obtain a check result of the PRBS symbol checker, and determine the bit error rate of the first network port 45 or/and the second network port 46 according to the check result.
In an embodiment, the check result includes the number of error symbols, and when the CPU performs the steps of obtaining the check result of the PRBS symbol checker and determining the bit error rate of the first network port or/and the second network port according to the check result, the CPU specifically performs the following steps:
and the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the first PRBS code stream, or the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the second PRBS code stream.
In an embodiment, the check result includes the number of error symbols, and when the CPU performs the steps of obtaining the check result of the PRBS symbol checker and determining the bit error rate of the first network port or/and the second network port according to the check result, the CPU specifically performs the following steps:
and the CPU acquires the port rate from the PHY controller and determines the bit error rate according to the number of error code elements, the interface rate and the test duration.
In an embodiment, the PHY controller includes a physical medium related layer, and when the CPU executes the step of controlling the PHY controller to send the first PRBS code stream to the second network port through the first network port, and controls the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for code element check, the CPU specifically executes the following steps:
the CPU controls the physical medium related layer to modulate the first PRBS code stream;
and the CPU controls the physical medium related layer to send the modulated code stream to a second network port through the first network port, and controls the physical medium related layer to demodulate the received second PRBS code stream and then transmit the second PRBS code stream to the PRBS code element checker for code element check.
In an embodiment, the PHY controller includes an additional layer of physical media, and the CPU further performs the following steps:
controlling the PHY controller to load the first PRBS code stream onto an additional layer of the physical medium;
the CPU controls the physical medium additional layer to carry out serial processing on the first PRBS code stream to obtain a serial bit stream, and controls the physical medium additional layer to send the serial bit stream to a physical medium related layer;
when the CPU executes the step of controlling the physical medium related layer to modulate the first PRBS code stream, the following steps are specifically executed:
the CPU controls the physical medium dependent layer to modulate the serial bit stream.
In one embodiment, the programmable device is an FPGA, or/and the programmable device and the CPU are connected through a pci bus.
In one embodiment, the first network port and the first network port are connected via a wired communication medium.
In an embodiment, the register of the PHY controller and the register of the PRBS controller are configured in a mem space of the pce bus, a test script runs on the CPU, the test script generates a first PRBS code stream by controlling the register of the PRBS controller and performs symbol check on a second PRBS code stream, and the test script further controls the register of the PHY controller to send the first PRBS code stream to the second network port through the first network port.
In one embodiment, the CPU is connected with a maintenance interface.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method for testing error codes of network ports of an intelligent network card is provided, wherein a programmable device and a CPU which are connected through a bus are integrated in the intelligent network card, the programmable device is connected with a first network port and a second network port, the programmable device comprises a PHY controller and a PRBS controller, the PRBS controller comprises a PRBS code element generator and a PRBS code element checker, and the method comprises the following steps:
when the first network port and the second network port are in a communication connection state, the CPU controls a PRBS code element generator in the programmable device to generate a first PRBS code stream;
the CPU controls the PHY controller to send the first PRBS code stream to the second network port through the first network port, and controls the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for code element check;
and the CPU acquires a check result of the PRBS code element checker, and determines the error rate of the first network port or/and the second network port according to the check result.
2. The method of claim 1, wherein the check result comprises a number of error symbols, wherein the CPU obtains the check result of the PRBS symbol checker, and determines the bit error rate of the first network port or/and the second network port according to the check result, comprising:
and the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the first PRBS code stream, or the CPU determines the error rate according to the number of the error code elements and the total number of the code elements of the second PRBS code stream.
3. The method of claim 1, wherein the check result comprises a number of error symbols, wherein the CPU obtains the check result of the PRBS symbol checker, and determines the bit error rate of the first network port or/and the second network port according to the check result, comprising:
and the CPU acquires a port rate from the PHY controller and determines the error rate according to the number of the error code elements, the interface rate and the test duration.
4. The method according to any one of claims 1 to 3, wherein the PHY controller includes a physical media dependent layer, and the CPU controls the PHY controller to transmit the first PRBS code stream to the second network port through the first network port and controls the PHY controller to transmit the received second PRBS code stream to the PRBS symbol checker for symbol checking, including:
the CPU controls the physical medium related layer to modulate the first PRBS code stream;
and the CPU controls the physical medium related layer to send the modulated code stream to the second network port through the first network port, and controls the physical medium related layer to demodulate the received second PRBS code stream and then transmit the demodulated second PRBS code stream to the PRBS code element checker for code element check.
5. The method of claim 4, wherein the PHY controller comprises an additional layer of physical media, the method further comprising:
the CPU controls the PHY controller to load the first PRBS code stream onto the additional layer of the physical medium;
the CPU controls the physical medium additional layer to carry out serial processing on the first PRBS code stream to obtain a serial bit stream, and controls the physical medium additional layer to send the serial bit stream to the physical medium related layer;
the CPU controls the physical medium related layer to modulate the first PRBS code stream, and the method comprises the following steps:
the CPU controls the physical medium dependent layer to modulate the serial bit stream.
6. The method according to any one of claims 1 to 3, wherein the programmable device is an FPGA, or/and the programmable device and the CPU are connected through a PCle bus;
preferably, the first network port and the first network port are connected by a wired communication medium.
7. The method of claim 6, wherein the register of the PHY controller and the register of the PRBS controller are configured in a mem space of the PCle bus, the CPU runs a test script, the test script generates the first PRBS code stream by controlling the register of the PRBS controller and performs symbol check on the second PRBS code stream, and the test script further controls the register of the PHY controller to send the first PRBS code stream to the second network port through the first network port.
8. The method according to any one of claims 1 to 7, wherein a maintenance interface is connected to the CPU.
9. An error code testing device, wherein the error code testing device is integrated in an intelligent network card, a programmable device connected with the error code testing device through a bus is further integrated in the intelligent network card, the programmable device is connected with a first network port and a second network port, the programmable device comprises a PHY controller and a PRBS controller, the PRBS controller comprises a PRBS code element generator and a PRBS code element checker, and the error code testing device comprises:
the first control unit is used for controlling the PRBS code element generator in the programmable device to generate a first PRBS code stream when the first network port and the first network port are in a communication connection state;
the second control unit is used for controlling the PHY controller to send the first PRBS code stream to the second network port through the first network port and controlling the PHY controller to transmit the received second PRBS code stream to the PRBS code element checker for checking;
and the processing unit is used for acquiring a check result of the PRBS code element checker and determining the error rate of the first network port or/and the second network port according to the check result.
10. An intelligent network card is characterized by comprising a programmable device and a CPU (central processing unit) which are connected through a bus, wherein the programmable device is connected with a first network port and a second network port and comprises a PHY (physical layer) controller and a PRBS (pseudo random binary system) controller, and the PRBS controller comprises a PRBS code element generator and a PRBS code element checker;
the CPU is used for controlling a PRBS code element generator in the programmable device to generate a first PRBS code stream when the first network port and the first network port are in a communication connection state;
the CPU is further configured to control the PHY controller to send the first PRBS code stream to the second network port through the first network port, and control the PHY controller to transmit the received second PRBS code stream to the PRBS symbol checker for checking;
the CPU is further used for obtaining a check result of the PRBS code element checker, and determining the error rate of the first network port or/and the second network port according to the check result.
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