CN104639176A - Asynchronous decoder and asynchronous decoding method for BMC (Biphase Mark Coding) signal - Google Patents
Asynchronous decoder and asynchronous decoding method for BMC (Biphase Mark Coding) signal Download PDFInfo
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- CN104639176A CN104639176A CN201310552559.0A CN201310552559A CN104639176A CN 104639176 A CN104639176 A CN 104639176A CN 201310552559 A CN201310552559 A CN 201310552559A CN 104639176 A CN104639176 A CN 104639176A
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Abstract
The invention discloses an asynchronous decoder for a BMC (Biphase Mark Coding) signal. The asynchronous decoder comprises a deburring circuit, a phase jump detection circuit, a level counter, a register, an adaptive logic circuit and a judgment logic circuit, wherein the phase jump detection circuit is used for detecting the edge of the phase change of the BMC signal, and taking the edge of the phase change as a judgment point of data, a reset point of the level counter and an update point of a half-bit sample point quantity; the level counter is used for recording the sample point quantity of each level; at the judgment point of the data, a judgment on whether 0 or 1 is received is made through comparison of the size relation between the level counter and the half-bit sample point quantity; and the half-bit sample point quantity is acquired through the adaptive logic circuit. The invention further discloses an asynchronous decoding method for the BMC signal. Through adoption of the asynchronous decoder and the asynchronous decoding method, the reception performance of the asynchronous decoder for the BMC signal can be improved, and reception data errors are avoided.
Description
Technical field
The present invention relates to the label coding of a kind of BMC(two-phase) asynchronous decoder of signal.The invention still further relates to a kind of asynchronous decoding method of BMC signal.
Background technology
BMC Signal coding waveform as shown in Figure 1, belongs to a kind of coding method of phase-modulation, is the coding method transmitted together with data mixing by clock; Its principle is that use clock frequency doubling transmission bit rate is as benchmark, an original bit data is splitted into two parts, 10 or 01 is become this intermediate change current potential (1->0 or 0->1) when data are 1 time, when data are 0 time, then do not change current potential, become 11 or 00.The level that level and the previous position of simultaneously each beginning end up otherwise together, such receiving terminal could judge the border of each.Use BMC coding that transmission ends and receiving terminal can be allowed only to need a data wire just by transmission correct for data and reception, and good synchronism can be kept at reception two ends.
Asynchronous decoder performance when Received signal strength is jagged of existing BMC signal is bad, easily causes reception corrupt data.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of asynchronous decoder of BMC signal, can improve its receptivity, avoids receiving corrupt data; For this reason, the present invention also will provide a kind of asynchronous decoding method of BMC signal.
For solving the problems of the technologies described above, the asynchronous decoder of BMC signal of the present invention, comprising:
One deburring circuit, for removing the burr in BMC signal;
One phase hit testing circuit, is connected with described deburring circuit, and for detecting the edge of BMC signal phase change, and the edge this phase place changed is as the determination point of data, the reduction point of level counter and the renewal point of half bit sampling point number;
One level counter, is connected with described phase hit testing circuit, for remembering BMC signal level length;
One register and adaptive logic circuit, be connected with described level counter, and its adaptive logic circuit adopts adaptive mode to obtain half bit sampling point number; Its register is for preserving this half bit sampling point number;
One decision logic circuit, be connected with register and adaptive logic circuit with described phase hit testing circuit, level counter, at the determination point of each data, the half bit sampling point number of preserving in the count value of described level counter and a half bit sampling point number register is compared; Adjudicating the data received is 0 or 1.
The asynchronous decoding method of described BMC signal adopts following technical scheme to realize:
Adopt a frequency much larger than the clock of BMC signal bit rate as clock signal, the low level of the BMC signal received with a level counter record or the interior clock signal number counted of high level; At the reduction point of level counter, count again after clear for this level counter 0;
By the sampled point number i.e. half bit sampling point number of a register record BMC signal half-bit width, after this at the determination point of each data, the value of described level counter and half bit sampling point number are compared, if the value of level counter is between 1.5 times ~ 2.5 times of half bit sampling point number, what receive is 0, if the value of level counter is between 0.75 times ~ 1.5 times of half bit sampling point number, what expression received is 1.
The described asynchronous clock signal referring to decoding circuit and the BMC signal that receives not necessarily homology clock generating.
The present invention utilizes high speed sampling clock to carry out demodulation to BMC signal, and the asynchronous decoder improving BMC signal receives data performance, can avoid receiving corrupt data, and it is fast to have self adaptation when Received signal strength is jagged, advantage accurately of decoding.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is BMC signal waveform schematic diagram;
Fig. 2 is the asynchronous decoder structured flowchart of described BMC signal.
Embodiment
The asynchronous decoder of described BMC signal shown in composition graphs 2 to realize principle as follows:
Adopt a frequency much larger than the clock of BMC signal bit rate as sampling clock and clock signal clk, the low level of the BMC signal received with a level counter record or the interior clock signal number counted of high level.At the reduction point of level counter, count again after clear for this level counter 0.
By the sampled point number (hereinafter referred to as half bit sampling point number) of a register record BMC signal half-bit width.After this at the determination point of each data, the value of level counter and half bit sampling point number are compared, if the value of level counter is between 1.5 times ~ 2.5 times of half bit sampling point number, what receive is 0, if the value of level counter is between 0.75 times ~ 1.5 times of half bit sampling point number, what expression received is 1.Because data 1 phase hit occurs in bit(bit) in the middle of, data 0 phase hit occurs in bit end, and therefore the determination point of visual data 1 is in the middle of bit, and the determination point of data 0 is at bit end.
As long as therefore obtain half bit sampling point number, what just can be easy to judge to receive is 1 or 0.The adaptive principle of following description half bit sampling point number.
First the register reset defaults of record half bit sampling point number is set to 0, at the renewal point of each half bit sampling point number, the value of the value of counter and register is compared later.If the value of counter is less than the value of register or is greater than the value 4 times of register, then the value of register is upgraded and become current Counter Value, otherwise the value of register keeps initial value.Adopt in this way after several bit, just can obtain the actual samples point number of half-bit width.
Assuming that level counter starts counting once powering on, the time starting to transmit due to BMC signal is uncertain, different because of system.Therefore, when the edge of first phase place change of BMC signal arrives, the numerical value of level counter is uncertain, can be divided into following 4 kinds of situations:
(1) 1/2 of half bit sampling point number is less than or equal to.
(2) be greater than 1/2 of half bit sampling point number and be less than or equal to half bit sampling point number.
(3) be greater than half bit sampling point number and be less than whole bit sampling point number.
(4) whole bit sampling point number is greater than.
Because the first value that makes of half bit sampling point number is 0, therefore at the edge of the 1st phase place change, the count value of level counter is certain to be updated in register.Also be namely the one in above 4 kinds of situations in the value of the edge late register of first phase place change.
Follow-up adaptive process is analyzed as follows:
For (1) in this case, after first by the time will receiving data 0, the value of register can be updated to the actual sampling point number of whole bit; Half bit actual samples point number will be updated to after waiting until the edge of the phase place change receiving data 1 again; Follow-uply can not to upgrade again.
For in (2), (3) and (4) these three kinds of situations, be all etc. will be updated to half bit actual samples point number behind the edge of the phase place change receiving data 1; Follow-uply can not to upgrade again.
Therefore, as long as the demodulation method of this BMC signal just correctly can be adjudicated 1 and 0 after multiple bits.And the agreement generally adopting BMC to communicate all can provide training sequence when communicating incipient, therefore this demodulation method is very simple and effective.
Because this demodulation mode can use high speed sampling clock, in order to the impact eliminating burr prevents decoded in error, BMC signal one carries out demodulation after coming in need to utilize high speed sampling clock and clock signal clk to carry out deburring process again.
Shown in Figure 2, in the embodiment shown in Figure 2, the asynchronous decoder of described BMC signal, comprising: a deburring circuit, a phase hit testing circuit, a level counter, a register and adaptive logic circuit, a decision logic circuit.
The asynchronous decoder of described BMC signal has 3 input signals:
1, clock signal clk;
2, reset signal rstn;
3, BMC signal decode_in;
The asynchronous decoder of described BMC signal has 1 output signal: i.e. decode value decode_out.
Described deburring circuit, adopt clock signal clk to input BMC signal adopt 3 bats, compare the 2nd clap and the 3rd clap output whether equal, if equal, using the 3rd clap output as new output, otherwise maintenance initial value.This deburring circuit can be removed length and be less than burr in the BMC signal in 1 clock signal clk cycle, is then input to phase hit testing circuit.
Described phase hit testing circuit, be connected with described deburring circuit, for adopting clock signal clk adopt 1 bat and export the output signal of deburring circuit, whether the output signal of more described phase hit testing circuit is equal with the output signal of deburring circuit, produce phase hit index signal, if unequal, export 1 and indicate phase hit, otherwise output 0 represents do not have phase hit.
Described level counter, is connected with described phase hit testing circuit, and for remembering BMC signal level length, the clock signal clk number namely counted in the low level of BMC signal decode_in or high level, at BMC signal decode_in phase hit along clear 0.Because this level counter is simultaneously also by rstn clear 0, therefore also have one in Fig. 2 and produce circuit with door as the asynchronous reset of level counter, for the inverted value phase of reset signal rstn and phase hit index signal and be processed into the reset terminal that a signal delivers to level counter again.
Described register and adaptive logic circuit, be connected with described level counter, and its adaptive logic circuit adopts the mode adapted to obtain half bit sampling point number; Its register is for preserving this half bit sampling point number.
Because BMC signal waveform is all for least unit with half bit, data 0 are two double-lengths of half bit, data 1 are made up of 2 half bits, as long as therefore judging that the value of current level counter and the magnitude relationship of half bit sampling point number just can rule out what be currently received at the determination point of data is 0 or 1.The judgement of 0 is at bit end, and the judgement of 1 is in the middle of bit.If half bit sampling point number is by the mode of hardware self-adapting, only needs several bit just can complete adaptive process, demodulate data accurately.
Described decision logic circuit, is connected with register and adaptive logic circuit with described phase hit testing circuit, level counter, at the determination point of data, compares the value of described level counter and half bit sampling point number; If the value of described level counter is between 1.5 times ~ 2.5 times of half bit sampling point number, what receive is 0, if the value of described level counter is between 0.75 times ~ 1.5 times of half bit sampling point number, what expression received is 1.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. an asynchronous decoder for BMC signal, is characterized in that, comprising:
One deburring circuit, for removing the burr in BMC signal;
One phase hit testing circuit, is connected with described deburring circuit, and for detecting the edge of BMC signal phase change, and the edge this phase place changed is as the determination point of data, the reduction point of level counter and the renewal point of half bit sampling point number;
One level counter, is connected with described phase hit testing circuit, for remembering BMC signal level length;
One register and adaptive logic circuit, be connected with described level counter, and its adaptive logic circuit adopts adaptive mode to obtain half bit sampling point number; Its register is for preserving this half bit sampling point number;
One decision logic circuit, be connected with register and adaptive logic circuit with described phase hit testing circuit, level counter, at the determination point of each data, the half bit sampling point number of preserving in the count value of described level counter and register is compared; Adjudicating the data received is 0 or 1.
2. asynchronous decoder as claimed in claim 1, it is characterized in that: described deburring circuit, adopt clock signal to input BMC signal adopt 3 bats, compare the 2nd clap and the 3rd bat output whether equal, if equal, using the 3rd output of clapping as new output, otherwise keep initial value.
3. asynchronous decoder as claimed in claim 1, it is characterized in that: described phase hit testing circuit, for adopting clock signal adopt 1 bat and export to the output signal of deburring circuit, whether the output signal of more described phase hit testing circuit is equal with the output signal of deburring circuit, if unequal, indicate phase hit, otherwise there is no phase hit.
4. asynchronous decoder as claimed in claim 1, is characterized in that: described level counter note BMC signal level length, is the clock signal number counted in the low level or high level of BMC signal, checks up 0 in the reset of level counter.
5. asynchronous decoder as claimed in claim 1, it is characterized in that: the mode that described adaptive logic circuit adopts adaptive mode to obtain half bit sampling point number is: described register reset defaults is set to 0, at the renewal point of each half bit sampling point number, the value of described level counter and the value of register are compared later; If the value of level counter is less than the value of register or is greater than the value 4 times of register, then the value of register is upgraded and become current Counter Value, otherwise the value of register keeps initial value; After too much doing a bit, then obtain the actual samples point number of half-bit width, i.e. half bit sampling point number.
6. asynchronous decoder as claimed in claim 1, it is characterized in that: described decision logic circuit adjudicate the data received be " 0 " or " 1 " according to being, if the value of described level counter is between 1.5 times ~ 2.5 times of half bit sampling point number, what receive is 0, if the value of described level counter is between 0.75 times ~ 1.5 times of half bit sampling point number, what expression received is 1.
7. an asynchronous decoding method for BMC signal, is characterized in that:
Adopt a frequency much larger than the clock of BMC signal bit rate as clock signal, the low level of the BMC signal received with a level counter record or the interior clock signal number counted of high level; At the reduction point of level counter, count again after clear for this level counter 0;
By the sampled point number i.e. half bit sampling point number of a register record BMC signal half-bit width, after this at the determination point of each data, the value of described level counter and half bit sampling point number are compared, if the value of level counter is between 1.5 times ~ 2.5 times of half bit sampling point number, what receive is 0, if the value of level counter is between 0.75 times ~ 1.5 times of half bit sampling point number, what expression received is 1.
8. method as claimed in claim 7, is characterized in that: described half bit sampling point number adopts adaptive mode to obtain, and method is:
The register reset defaults of record half bit sampling point number is set to 0, at the renewal point of each half bit sampling point number, the value of described level counter and the value of register is compared later; If the value of level counter is less than the value of register or is greater than the value 4 times of register, then the value of register is upgraded and become current Counter Value, otherwise the value of register keeps initial value; After too much doing a bit, then obtain the actual samples point number of half-bit width.
9. method as claimed in claim 7 or 8, is characterized in that: it is characterized in that: before carrying out asynchronous decoding to BMC signal, adopts the burr removed with the following method in BMC signal; Adopt described clock signal to input BMC signal adopt 3 bats, compare the 2nd clap and the 3rd clap output whether equal, if equal, using the 3rd clap output as new output, otherwise maintenance initial value.
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| CN110647483A (en) * | 2019-08-02 | 2020-01-03 | 福州瑞芯微电子股份有限公司 | BMC code asynchronous receiving method suitable for USB-PD protocol and storage device |
| CN114117972A (en) * | 2022-01-26 | 2022-03-01 | 之江实验室 | Synchronous device and method of asynchronous circuit |
| CN114117972B (en) * | 2022-01-26 | 2022-06-10 | 之江实验室 | Synchronous device and method of asynchronous circuit |
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