CN108551387A - A kind of BMC code self-adaptings decoding system and coding/decoding method - Google Patents
A kind of BMC code self-adaptings decoding system and coding/decoding method Download PDFInfo
- Publication number
- CN108551387A CN108551387A CN201810679019.1A CN201810679019A CN108551387A CN 108551387 A CN108551387 A CN 108551387A CN 201810679019 A CN201810679019 A CN 201810679019A CN 108551387 A CN108551387 A CN 108551387A
- Authority
- CN
- China
- Prior art keywords
- signal
- decoding
- bit
- synchronous head
- subelement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/20—Conversion to or from representation by pulses the pulses having more than three levels
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
Abstract
The present invention relates to a kind of BMC code self-adaptings decoding system and coding/decoding methods.The coding/decoding method of the BMC codes, filter unit is first passed through to be filtered input signal, eliminate burr interference, then hopping edge detection and analysis is carried out to the synchronous head signal in filtering signal, adaptive configuration decodes the parameter of threshold value, finally, according to the level saltus step situation among decoding Threshold Analysis individual bit signal, corresponding decoding is carried out, accuracy is decoded and decoding efficiency is high.In addition, using the decoding system of this coding/decoding method, simple in structure, cost is relatively low.
Description
Technical field
The present invention relates to communication technique fields, and in particular to a kind of BMC code self-adaptings decoding system and coding/decoding method.
Background technology
With the development of electronic technology, the application of USB interface offer electric energy has had increased to be weighed on an equal basis with data transmission
The status wanted.The USB Type-C Power Delivery agreements (hereinafter referred to as PD agreements) of newest publication are to be based on USB
3.1 versions, i.e., a kind of power transmission protocol based on Type-C interfaces.USB PD maximums can support 100W（20V/5A）Power
Transmission, while supporting power supply role transforming, Most electronic equipment power demands can be met.In USB Type-C interfaces,
USB PD communications are encoded using two-way mark（Biphase Mark Coding, BMC）, in the channels CC transmitting data.This side
Method simple and flexible has been used as PD communication standards to issue, has just gradually been widely used at present.BMC codings belong to a kind of phase
The coding techniques of position modulation, is the coding method that clock and data are mixed to transmission.The characteristics of BMC is encoded is, every
Level will carry out saltus step at the beginning of one bit period.Logic is indicated using level change in a bit period, such as
Fruit level saltus step among bit period, then it represents that otherwise logical one indicates logical zero.Transmission can be allowed using BMC codings
End only needs a data line that can correctly transmit data and receive with receiving terminal, and keeps good in transmitting-receiving two-end
Synchronism.PD agreements provide that BMC code transmission frequencies are 300K, i.e., each bit period is 3.33us.Each communication data band
There is the lead code of 64 bits as synchronous head.PD agreements allow the coding have +/- 10% frequency departure, but in practical applications
It is influenced since transmission device individual difference, channel are different in size, or by noise, electromagnetic environment etc., it is past in receiving terminal frequency departure
Toward bigger.
Invention content
In view of the above problems, the present invention provides a kind of BMC code self-adaptings decoding system and coding/decoding method, it can be according to synchronization
The parameter of head adaptive configuration decoding threshold value, eliminates the influence of frequency departure, is correctly decoded to BMC coded datas.The present invention's
Specific technical solution is as follows：
A kind of BMC code self-adaptings decoding system, including signal filter unit, synchronous head detection unit and BMC decoding units.Its
In：The signal filter unit is for receiving input signal, and after being filtered to the input signal, and output filtering signal is extremely
The synchronous head detection unit.The synchronous head detection unit is used to receive the filtering signal, and in the filtering signal
Synchronous head signal sampled, and determine decoding threshold value.The BMC decoding units are used to individually be compared according to decoding Threshold Analysis
Whether level saltus step is occurred among special signal, if there is level saltus step, then at the end of bit signal into shift register
High level signal is deposited, low level signal is otherwise deposited into shift register at the end of bit signal, finally displacement is posted
The high level signal and low level signal deposited in storage are exported as decoding data.
Further, the signal filter unit includes input sample subelement and sampling processing subelement.Wherein：It is described
Input sample subelement is used to carry out continuous sampling to the input signal according to clock signal.The sampling processing subelement is used
In judging in signal that the input sample subelement is sampled with the presence or absence of all identical level letter in continuous preset time
Number, and in the case where the judgment result is yes, identical level signal is exported using as filtering signal.
Further, the synchronous head detection unit includes hopping edge detection sub-unit, hopping edge number register, time
Counter and decoding threshold register.Wherein：The hopping edge detection sub-unit is for detecting synchronous head in the filtering signal
The hopping edge of signal.The hopping edge number register is used to deposit the hopping edge detected by the hopping edge detection sub-unit
Total number.When the time counter is used to calculate synchronous head signal in the filtering signal from start to end total
Between.For the decoding threshold register for depositing decoding threshold value, the decoding threshold value is the total time and the total number
The ratio value corresponding to the product with preset ratio again.
Further, the BMC decoding units include bit signal timer, bit signal end mark subelement, number
According to mark subelement and shift register.Wherein：The bit signal timer is used for since each bit signal starting point
Timing is carried out, and when the time of subsequent detection to hopping edge being more than the decoding threshold value, timing time is reset, bit signal
Terminate, then the bit signal timer starts the timing of next bit signal again.The bit signal terminates to mark
Measure unit is used at the end of bit signal, exports single pulse signal.The Data Labels subelement is used in a bit
When detecting hopping edge in the time cycle of signal, output data mark high level, and output identification at the end of bit signal
Signal low level.The shift register is used at the end of bit signal, the corresponding Data Labels subelement output
Data Labels high level and deposit high level signal, the Data Labels low level of the corresponding Data Labels subelement output and
Deposit low level signal.
A kind of BMC code self-adaptings coding/decoding method decodes system based on above-mentioned BMC code self-adaptings, and the method includes such as
Lower step：The signal filter unit receives input signal, and after being filtered to the input signal, and output filtering signal is extremely
The synchronous head detection unit；The synchronous head detection unit receives the filtering signal, to the synchronization in the filtering signal
Head signal is sampled, and determines decoding threshold value；The BMC decoding units according to decoding Threshold Analysis individual bit signal among
Whether there is level saltus step, if there is level saltus step, then deposits high level into shift register at the end of bit signal
Otherwise signal deposits low level signal at the end of bit signal into shift register, finally being posted in shift register
The high level signal and low level signal deposited are exported as decoding data.
Further, the signal filter unit receives input signal, and after being filtered to the input signal, output
It the step of filtering signal to synchronous head detection unit, specifically includes：Input sample in the signal filter unit is single
Member carries out continuous sampling according to clock signal to the input signal；Sampling processing subelement in the signal filter unit is sentenced
With the presence or absence of all identical level signal in continuous preset time in the signal that the disconnected input sample subelement is sampled, and
In the case where the judgment result is yes, identical level signal is exported using as filtering signal.
Further, the preset time is 5 clock cycle.
Further, the synchronous head detection unit receives the filtering signal, to the synchronous head in the filtering signal
Signal is sampled, and the step of determining decoding threshold value, is specifically included：Hopping edge detection in the synchronous head detection unit
Unit detects the hopping edge of synchronous head signal in the filtering signal, and passes through the hopping edge in the synchronous head detection unit
Number register deposits the total number of the hopping edge detected by the hopping edge detection sub-unit；The synchronous head detection unit
In time counter calculate the total time of synchronous head signal from start to end in the filtering signal；The synchronous head inspection
Survey the decoding threshold register deposit decoding threshold value in unit.Wherein, the decoding threshold value is the total time and described total
Several ratio value corresponding to the product with preset ratio again.
Further, the preset ratio is 3/4ths.
Further, the BMC decoding units according to decoding Threshold Analysis individual bit signal among whether there is level
Saltus step then deposits high level signal at the end of bit signal if there is level saltus step into shift register, otherwise than
Low level signal is deposited at the end of special signal into shift register, finally the high level signal deposited in shift register
The step of being exported as decoding data with low level signal, specifically includes：Bit signal timer in the BMC decoding units
Timing is proceeded by from each bit signal starting point, and when subsequent detection is to hopping edge, judges whether timing time is more than
The decoding threshold value, if it is not, then continuing timing, if it is, timing time is reset, the bit signal timer is again heavy
The timing for newly starting next bit signal, subsequently into next step；Bit signal in the BMC decoding units terminates to mark
The bit signal finish time that measure unit is reset in timing time exports single pulse signal；Number in the BMC decoding units
Judge whether hopping edge occur within the time cycle of a bit signal according to mark subelement, it is if there is hopping edge, then defeated
Go out Data Labels high level, and output data mark low level at the end of bit signal, subsequently into next step；It is described
Shift register in BMC decoding units is at the end of bit signal, the data mark of the corresponding Data Labels subelement output
Chigo level and deposit high level signal, the Data Labels low level of the corresponding Data Labels subelement output and deposit low electricity
Ordinary mail number, it is finally, after receiving end of data, the high level signal and low level signal deposited is defeated as decoding data
Go out.
BMC code self-adaptings coding/decoding method of the present invention, first passes through filter unit and is filtered to input signal, eliminates
Burr interferes, and then carries out hopping edge detection and analysis to the synchronous head signal in filtering signal, and adaptive configuration decodes threshold value
Parameter, finally, according to decoding Threshold Analysis individual bit signal among level saltus step situation, carry out corresponding decoding, decoding
Accuracy and decoding efficiency are high.In addition, using the decoding system of this coding/decoding method, simple in structure, cost is relatively low.
Description of the drawings
Fig. 1 is the structure diagram of the decoding system of the BMC codes.
Fig. 2 is the flow diagram of the coding/decoding method of the BMC codes.
Fig. 3 is the sequence diagram of each signal in BMC decoding process.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is retouched in detail
It states.It should be appreciated that specific embodiment disclosed below is only used for explaining the present invention, it is not intended to limit the present invention.
BMC code self-adaptings as shown in Figure 1 decode system, including signal filter unit, the synchronous head contacted successively detect
Unit and BMC decoding units.Wherein, the signal filter unit is carried out for receiving input signal, and to the input signal
After filtering, output filtering signal to the synchronous head detection unit.The synchronous head detection unit is for receiving the filtering letter
Number, and the synchronous head signal in the filtering signal is sampled, and determine decoding threshold value.The BMC decoding units are used for
According to whether there is level saltus step among decoding Threshold Analysis individual bit signal, if there is level saltus step, then believe in bit
High level signal is deposited at the end of number into shift register, is otherwise deposited into shift register at the end of bit signal low
Level signal is finally exported using the high level signal and low level signal deposited in shift register as decoding data.Institute
The system of stating first passes through filter unit and is filtered to input signal, burr interference is eliminated, then to the synchronous head in filtering signal
Signal carries out hopping edge detection and analysis, and adaptive configuration decodes the parameter of threshold value, finally, is individually compared according to decoding Threshold Analysis
Level saltus step situation among special signal carries out corresponding decoding, decodes accuracy and decoding efficiency is high.In addition, the decoding system
Simple in structure, cost is relatively low.
Preferably, the signal filter unit includes input sample subelement and sampling processing subelement.The input is adopted
Sub-unit is used to carry out continuous sampling to the input signal according to high-speed clock signal, and sampled result is exported to described
Sampling processing subelement.The sampling processing subelement be used to judge in signal that the input sample subelement is sampled whether
There are all identical level signals in continuous preset time, and in the case where the judgment result is yes, export identical level
Signal is using as filtering signal.Wherein, the preset time can be accordingly arranged according to specific design requirement, Ke Yishe
Any one value being set in 3 to 10 clock cycle preferably could be provided as 5 clock cycle.The filter unit passes through
Judged and handled as unit of the sampled signal of continuous preset time, the hair that length is less than preset time can be effectively filtered out
The interference of the clutters such as thorn, improves the accuracy of signal.
Preferably, the synchronous head detection unit includes hopping edge detection sub-unit, hopping edge number register, time meter
Number device and decoding threshold register.The hopping edge detection sub-unit is used to detect the jump of synchronous head signal in the filtering signal
Become edge.The hopping edge number register is used to deposit total of the hopping edge detected by the hopping edge detection sub-unit
Number.The time counter is used to calculate the total time of synchronous head signal from start to end in the filtering signal.It is described
Threshold register is decoded for depositing decoding threshold value.Wherein, the decoding threshold value is the ratio of the total time and the total number
It is worth the value corresponding to the product with preset ratio again.The preset ratio can accordingly be set according to specific design requirement
It sets, any one value that could be provided as between 1/2 to 4/5 preferably could be provided as 3/4.The synchronous head signal is to send
The a series of signal sent before useful signal sends useful signal immediately after synchronous head signal is sent.Synchronous head
The effect of signal is to remind to receive chip, i.e., by transmission is useful signal, pays attention to receiving, in order to avoid loss useful signal.It is described
Synchronous head detection unit by analyze synchronous head signal hopping edge total number and total time, therefrom determine decoding threshold value, with for
Subsequent data decoding provides accurate reference frame.
Preferably, the BMC decoding units include bit signal timer, bit signal end mark subelement, data
Indicate subelement and shift register.The bit signal timer from each bit signal starting point based on proceeding by
When, and when the time of subsequent detection to hopping edge being more than the decoding threshold value, timing time is reset, bit signal terminates,
Then the bit signal timer starts the timing of next bit signal again.Bit signal end mark is single
Member is at the end of bit signal, exporting single pulse signal.The Data Labels subelement is used in bit signal
When detecting hopping edge in the time cycle, output data mark high level, and output identification signal is low at the end of bit signal
Level.The shift register is used at the end of bit signal, the data mark of the corresponding Data Labels subelement output
Chigo level and deposit high level signal, the Data Labels low level of the corresponding Data Labels subelement output and deposit low
Level signal.The BMC decoding units decode the sequential relationship of threshold value and hopping edge by analysis, can be in a shift register
Corresponding deposit signal is accurately input, to ensure that decoded accuracy.
BMC code self-adapting coding/decoding methods as shown in Figure 2, include the following steps：First, the signal filter unit receives
Input signal, and after being filtered to the input signal, output filtering signal to the synchronous head detection unit.Then, institute
It states synchronous head detection unit and receives the filtering signal, the synchronous head signal in the filtering signal is sampled, and determine
Decode threshold value.Then, the BMC decoding units according to decoding Threshold Analysis individual bit signal among whether there is level jump
Become, if there is level saltus step, then high level signal is deposited into shift register at the end of bit signal, otherwise in bit
Low level signal is deposited at the end of signal into shift register.Finally the high level signal deposited in shift register and
Low level signal is exported as decoding data.The coding/decoding method first passes through filter unit and is filtered to input signal, eliminates
Burr interferes, and then carries out hopping edge detection and analysis to the synchronous head signal in filtering signal, and adaptive configuration decodes threshold value
Parameter, finally, according to decoding Threshold Analysis individual bit signal among level saltus step situation, carry out corresponding decoding, decoding
Accuracy and decoding efficiency are high.
Preferably, the signal filter unit receives input signal, and after being filtered to the input signal, output filter
It the step of wave signal to synchronous head detection unit, specifically includes：First, input sample in the signal filter unit
Unit carries out continuous sampling according to high-speed clock signal to the input signal.Then, the sampling in the signal filter unit
Processing subelement judges in the signal that the input sample subelement is sampled with the presence or absence of all identical in continuous preset time
Level signal export identical level signal using as filtering signal and in the case where the judgment result is yes.Wherein, institute
Stating preset time can be accordingly arranged according to specific design requirement, could be provided as arbitrary in 4 to 8 clock cycle
One value.The filter step can be filtered effectively by being judged and being handled as unit of the sampled signal of continuous preset time
Except length is less than the interference of the clutters such as the burr of preset time, the accuracy of signal is improved.
Preferably, the preset time is 5 clock cycle, can not so be influenced while ensureing to filter out burr
The reception of normal signal.
Preferably, the synchronous head detection unit receives the filtering signal, believes the synchronous head in the filtering signal
It number is sampled, and the step of determining decoding threshold value, is specifically included：First, the hopping edge inspection in the synchronous head detection unit
It surveys subelement and detects the hopping edge of synchronous head signal in the filtering signal, and pass through the jump in the synchronous head detection unit
Become the total number that the hopping edge detected by the hopping edge detection sub-unit is deposited along number register.Then, the synchronization
Time counter in head detection unit calculates the total time of synchronous head signal from start to end in the filtering signal.Most
Afterwards, the decoding threshold register deposit decoding threshold value in the synchronous head detection unit.Wherein, the decoding threshold value is described total
The ratio of time and the total number value corresponding to the product with preset ratio again.The preset ratio is set as 3/4, i.e. institute
State the corresponding time value in 3/4 position place that decoding threshold value is each bit signal.The synchronous head detection unit passes through analysis
The hopping edge total number of synchronous head signal and total time therefrom determine decoding threshold value, it is accurate to be provided for the decoding of subsequent data
Reference frame.
The preset ratio is set as 3/4, decodes threshold value by thus identified, can relatively accurately judge bit
The case where whether occurring level reversion among signal, avoiding erroneous judgement, to improve decoded accuracy.
Preferably, the BMC decoding units according to decoding Threshold Analysis individual bit signal among whether there is level jump
Become, if there is level saltus step, then high level signal is deposited into shift register at the end of bit signal, otherwise in bit
Low level signal is deposited at the end of signal into shift register, finally the high level signal deposited in shift register and
The step of low level signal is exported as decoding data, specifically includes：First, the bit signal meter in the BMC decoding units
When device proceed by timing from each bit signal starting point, and when subsequent detection is to hopping edge, whether judge timing time
More than the decoding threshold value, if it is not, then continuing timing, if it is, timing time is reset, the bit signal timer
The timing for starting next bit signal again, subsequently into next step.Then, the bit in the BMC decoding units
The bit signal finish time that signal end mark subelement is reset in timing time exports single pulse signal（It is just set after setting 1
0）.System detectio is to the single pulse signal, you can is judged as that bit signal terminates.Then, the data in the BMC decoding units
Mark subelement judges whether hopping edge occur within the time cycle of a bit signal, if there is hopping edge, then exports
Data Labels high level, and output data mark low level at the end of bit signal, subsequently into next step；If no
There is hopping edge, then keeps output data mark low level.When system detectio is to Data Labels high level signal, then it can obtain
Occurs level reversion in corresponding bit signal；When detecting Data Labels low level signal, then show in corresponding ratio
Do not occur level reversion in special signal.And then, the shift register in the BMC decoding units terminates in bit signal
When, it corresponds to the Data Labels high level of the Data Labels subelement output and deposits high level signal, the corresponding data mark
A measure unit output Data Labels low level and deposit low level signal.Finally, after receiving end of data, what is deposited
High level signal and low level signal are exported as decoding data.The coding/decoding method is by analyzing single pulse signal and data mark
Will signal in shift register come to being written related data so that and what is deposited in shift register is accurate decoding data,
To ensure the accuracy of system output decoding data.
Specifically, as shown in figure 3, system power-on reset, after data are initial, signal filter unit uses high-speed clock signal
Clk adopts 5 bats to the BMC signals of input（Sample 5 clock cycle）If the data of 5 bats are all equal and are all 0, defeated
Go out low level signal 0；If the data of 5 bats are all equal and are all 1, high level signal 1 is exported.The signal filter unit energy
Enough removal length is less than the burr in the BMC signals in 5 clock signal clk periods, then that carrot-free signal after filtering is defeated
Go out to synchronous head detection unit.
Synchronous head detection unit is equipped with decoding threshold register data_threshold, hopping edge number register pulse_
Cnt and time counter timer_val.Because each BMC communication data packets carry the lead code conduct that 64 bits 0 and 1 interlock
Synchronous head.Synchronous head detection unit is using high-speed clock signal clk to 64 bit synchronous head signals of the BMC signals after deburring
Sampling.The characteristics of according to BMC codes, the lead code synchronous head that 64 bits 0 and 1 interlock can collect 96 signal saltus steps in total
Edge.Hopping edge number register pulse_cnt is synchronized since first lead code synchronous head of transmission to 64 bit preambles
Head terminates, and count is incremented for each signal hopping edge, count down to 96 expression lead code synchronous heads and is transmitted.Time counter
The total time of timer_val recording synchronism head start to finish, i.e. hopping edge number register pulse_cnt are total from 0 to 96
Time.Threshold register data_threshold=timer_val/96*3/4 is decoded, as shown in figure 3, the time of decoding threshold value sets
It sets at the 3/4 of each bit total time, i.e. threshold point signal pointed location.
It, can be in a bit period since BMC codings level at the beginning of each bit period will be inverted
It is interior that logic is indicated using level change, if level inverts among bit period, then it represents that otherwise logical one indicates to patrol
It collects " 0 ".Therefore, as long as at the end of each bit, judge whether there is level reversion in 1 bit period, number can be distinguished
According to 0 and 1, to be correctly decoded data.Shown BMC decoding units are equipped with the data mark of output data marking signal data1_flag
Measure unit, bit signal timer bit_timer, and output bit end mark signal bit_over（That is single pulse signal）
Bit signal end mark subelement.Bit time counter bit_timer timing since each bit beginning, to often
A hopping edge is compared with the value of decoding threshold register data_threshold, if bit_timer is less than data_
Threshold indicates that current bit does not have the end of transmission, count value to continue growing；If bit_timer is more than data_
Threshold indicates that the current bit end of transmission, bit time counter bit_timer clear 0 count again.As shown in figure 3,
Bit_over signals are generated at the end of each bit, i.e., bit_over signals are clear 0 after first setting 1.In each hopping edge bit_
Timer is compared with the value of data_threshold, if bit_timer is less than data_threshold, indicates current bit week
There are level saltus step, data flag signal data1_flag to set 1 in phase, after each bit transfer, i.e. bit_over signals
When setting 1, data flag signal data1_flag clear 0.
The BMC decoding units are additionally provided with the shift register of 5 bits.As shown in figure 3, when bit_over signals set 1,
If data flag signal data1_flag=1, it is to have level reversion to represent in 1 bit period, is write toward shift register
“1”；If when data flag signal data1_flag=0, it is no level reversion to represent in 1 bit period, is posted toward displacement
Storage is write " 0 ".After having received 5 bit data, exported using the value of shift register as decoding data.
The BMC codes of this patent introduction decode system, improve the performance that BMC decoding signals receive data, are receiving number
It according to flash removed can be removed in the case of jagged, and is not influenced by the variation of distinct device BMC code frequencies, according to BMC data
The parameter of preamble synchronization code self-adapting configuration decoding threshold value, has adaptive ability strong, decodes accurate advantage.
Finally it should be noted that：Each embodiment is described by the way of progressive in this specification, each embodiment emphasis
What is illustrated is all the difference with other embodiments, and just to refer each other for same or similar part between each embodiment, respectively
Technical solution between embodiment can be combined with each other.The above various embodiments is only used to illustrate the technical scheme of the present invention,
Rather than its limitations, although present invention has been described in detail with reference to the aforementioned embodiments, the ordinary skill people of this field
Member still can be with technical scheme described in the above embodiments is modified, either to which part or whole technologies
Feature carries out equivalent replacement；And these modifications or replacements, the present invention that it does not separate the essence of the corresponding technical solution is each to be implemented
The range of example technical solution.
Claims (10)
1. a kind of BMC code self-adaptings decode system, which is characterized in that including signal filter unit, synchronous head detection unit and BMC
Decoding unit, wherein：
The signal filter unit exports filtering signal for receiving input signal, and after being filtered to the input signal
To the synchronous head detection unit；
The synchronous head detection unit is carried out for receiving the filtering signal, and to the synchronous head signal in the filtering signal
Sampling, and determine decoding threshold value；
The BMC decoding units are used to level saltus step whether occur according among decoding Threshold Analysis individual bit signal, if
There is level saltus step, then high level signal is deposited into shift register at the end of bit signal, otherwise in bit signal knot
Low level signal is deposited when beam into shift register, finally the high level signal and low level deposited in shift register
Signal is exported as decoding data.
2. system according to claim 1, which is characterized in that the signal filter unit include input sample subelement and
Sampling processing subelement, wherein：
The input sample subelement is used to carry out continuous sampling to the input signal according to clock signal；
The sampling processing subelement is used to judge in the signal that the input sample subelement is sampled with the presence or absence of continuous
All identical level signal in preset time, and in the case where the judgment result is yes, export identical level signal using as
Filtering signal.
3. system according to claim 1, which is characterized in that the synchronous head detection unit includes that hopping edge detection is single
Member, hopping edge number register, time counter and decoding threshold register, wherein：
The hopping edge detection sub-unit is used to detect the hopping edge of synchronous head signal in the filtering signal；
The hopping edge number register is used to deposit the total number of the hopping edge detected by the hopping edge detection sub-unit；
The time counter is used to calculate the total time of synchronous head signal from start to end in the filtering signal；
For the decoding threshold register for depositing decoding threshold value, the decoding threshold value is the total time and the total number
The ratio value corresponding to the product with preset ratio again.
4. system according to claim 1, which is characterized in that the BMC decoding units include bit signal timer, ratio
Special signal end mark subelement, Data Labels subelement and shift register, wherein：
The bit signal timer is used to proceed by timing from each bit signal starting point, and in subsequent detection to saltus step
When the time on edge is more than the decoding threshold value, timing time is reset, bit signal terminates, then the bit signal timer
Start the timing of next bit signal again；
The bit signal end mark subelement is used at the end of bit signal, exports single pulse signal；
When the Data Labels subelement is used to detect hopping edge within the time cycle of a bit signal, output data mark
Chigo level, and output identification signal low level at the end of bit signal；
The shift register is used at the end of bit signal, the Data Labels of the corresponding Data Labels subelement output
High level and deposit high level signal, the Data Labels low level of the corresponding Data Labels subelement output and deposit low electricity
Ordinary mail number.
5. a kind of BMC code self-adaptings coding/decoding method, based on BMC code self-adaptings any one of Claims 1-4 decoding system
System, which is characterized in that described method includes following steps：
The signal filter unit receives input signal, and after being filtered to the input signal, output filtering signal to institute
State synchronous head detection unit；
The synchronous head detection unit receives the filtering signal, is sampled to the synchronous head signal in the filtering signal,
And determine decoding threshold value；
The BMC decoding units according to decoding Threshold Analysis individual bit signal among whether there is level saltus step, if there is
High level signal is then deposited in level saltus step at the end of bit signal into shift register, otherwise at the end of bit signal
Low level signal is deposited into shift register, finally the high level signal and low level signal deposited in shift register
It is exported as decoding data.
6. according to the method described in claim 5, it is characterized in that, the signal filter unit receives input signal, and to institute
The step of stating after input signal is filtered, exporting filtering signal to the synchronous head detection unit, specifically includes：
Input sample subelement in the signal filter unit carries out continuous sampling according to clock signal to the input signal；
Sampling processing subelement in the signal filter unit judges
No there are all identical level signals in continuous preset time, and in the case where the judgment result is yes, export identical electricity
Ordinary mail number is using as filtering signal.
7. according to the method described in claim 6, it is characterized in that, the preset time is 5 clock cycle.
8. according to the method described in claim 5, it is characterized in that, the synchronous head detection unit receives the filtering signal,
Synchronous head signal in the filtering signal is sampled, and the step of determining decoding threshold value, is specifically included：
Hopping edge detection sub-unit in the synchronous head detection unit detects the saltus step of synchronous head signal in the filtering signal
Edge, and the hopping edge detection sub-unit is deposited by the hopping edge number register in the synchronous head detection unit and is examined
The total number of the hopping edge measured；
Time counter in the synchronous head detection unit calculates the synchronous head signal in the filtering signal from starting knot
The total time of beam；
Decoding threshold register deposit decoding threshold value in the synchronous head detection unit；
Wherein, the decoding threshold value is corresponding to the ratio of the total time and the total number again product with preset ratio
Value.
9. according to the method described in claim 8, it is characterized in that, the preset ratio is 3/4ths.
10. according to the method described in claim 5, it is characterized in that, the BMC decoding units are single according to decoding Threshold Analysis
Whether level saltus step is occurred among bit signal, if there is level saltus step, then toward shift register at the end of bit signal
Middle deposit high level signal, otherwise deposits low level signal, finally displacement at the end of bit signal into shift register
The step of high level signal and low level signal deposited in register are exported as decoding data, specifically includes：
Bit signal timer in the BMC decoding units proceeds by timing from each bit signal starting point, and rear
It is continuous to judge whether timing time is more than the decoding threshold value when detecting hopping edge, if it is not, then continue timing, if it is,
Timing time is reset, the bit signal timer starts the timing of next bit signal again, subsequently into next
Step；
Bit signal end mark subelement in the BMC decoding units is at the end of the bit signal that timing time is reset
It carves, exports single pulse signal；
Data Labels subelement in the BMC decoding units judges whether jumped within the time cycle of a bit signal
Become edge, if there is hopping edge, then output data mark high level, and the low electricity of output data mark at the end of bit signal
It is flat, subsequently into next step；
Shift register in the BMC decoding units is at the end of bit signal, the corresponding Data Labels subelement output
Data Labels high level and deposit high level signal, the Data Labels low level of the corresponding Data Labels subelement output and
Low level signal is deposited, finally, after receiving end of data, using the high level signal and low level signal deposited as decoding
Data export.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810679019.1A CN108551387A (en) | 2018-06-27 | 2018-06-27 | A kind of BMC code self-adaptings decoding system and coding/decoding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810679019.1A CN108551387A (en) | 2018-06-27 | 2018-06-27 | A kind of BMC code self-adaptings decoding system and coding/decoding method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108551387A true CN108551387A (en) | 2018-09-18 |
Family
ID=63493024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810679019.1A Pending CN108551387A (en) | 2018-06-27 | 2018-06-27 | A kind of BMC code self-adaptings decoding system and coding/decoding method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108551387A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109331793A (en) * | 2018-10-12 | 2019-02-15 | 广东石油化工学院 | A kind of magnetic crosslinking beta cyclo dextrin polymer adsorbent and preparation method thereof |
| CN109639613A (en) * | 2019-01-17 | 2019-04-16 | 广东高云半导体科技股份有限公司 | A kind of coding/decoding method based on two-phase symbolic coding, mobile device and storage medium |
| CN112152955A (en) * | 2020-09-24 | 2020-12-29 | 无锡华润矽科微电子有限公司 | Method for realizing FSK decoding based on wireless charging system |
| CN113517975A (en) * | 2021-09-13 | 2021-10-19 | 天津飞旋科技股份有限公司 | Carrier synchronization control method, system, converter device and readable storage medium |
| CN114189314A (en) * | 2021-11-25 | 2022-03-15 | 苏州博创集成电路设计有限公司 | BMC signal receiving method and device, USB power supply and readable storage medium |
| CN115118386A (en) * | 2022-06-21 | 2022-09-27 | 上海艾为电子技术股份有限公司 | Decoding method, device, decoder, readable storage medium and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552595A (en) * | 2008-03-31 | 2009-10-07 | 联想(北京)有限公司 | Electronic product volume regulating method and device thereof |
| CN105915327A (en) * | 2015-02-23 | 2016-08-31 | 瑞萨电子株式会社 | BMC processing circuit, USB power delivery controller and BMC reception method |
| CN107515836A (en) * | 2017-09-21 | 2017-12-26 | 英特格灵芯片(天津)有限公司 | The BMC decoding apparatus and method of a kind of dynamic bi-threshold |
-
2018
- 2018-06-27 CN CN201810679019.1A patent/CN108551387A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552595A (en) * | 2008-03-31 | 2009-10-07 | 联想(北京)有限公司 | Electronic product volume regulating method and device thereof |
| CN105915327A (en) * | 2015-02-23 | 2016-08-31 | 瑞萨电子株式会社 | BMC processing circuit, USB power delivery controller and BMC reception method |
| CN107515836A (en) * | 2017-09-21 | 2017-12-26 | 英特格灵芯片(天津)有限公司 | The BMC decoding apparatus and method of a kind of dynamic bi-threshold |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109331793A (en) * | 2018-10-12 | 2019-02-15 | 广东石油化工学院 | A kind of magnetic crosslinking beta cyclo dextrin polymer adsorbent and preparation method thereof |
| CN109639613A (en) * | 2019-01-17 | 2019-04-16 | 广东高云半导体科技股份有限公司 | A kind of coding/decoding method based on two-phase symbolic coding, mobile device and storage medium |
| CN112152955A (en) * | 2020-09-24 | 2020-12-29 | 无锡华润矽科微电子有限公司 | Method for realizing FSK decoding based on wireless charging system |
| CN112152955B (en) * | 2020-09-24 | 2022-03-04 | 华润微集成电路(无锡)有限公司 | Method for realizing FSK decoding based on wireless charging system |
| CN113517975A (en) * | 2021-09-13 | 2021-10-19 | 天津飞旋科技股份有限公司 | Carrier synchronization control method, system, converter device and readable storage medium |
| CN113517975B (en) * | 2021-09-13 | 2021-12-07 | 天津飞旋科技股份有限公司 | Carrier synchronization control method, system, converter device and readable storage medium |
| CN114189314A (en) * | 2021-11-25 | 2022-03-15 | 苏州博创集成电路设计有限公司 | BMC signal receiving method and device, USB power supply and readable storage medium |
| CN114189314B (en) * | 2021-11-25 | 2024-04-09 | 苏州博创集成电路设计有限公司 | BMC signal receiving method and device, USB power supply and readable storage medium |
| CN115118386A (en) * | 2022-06-21 | 2022-09-27 | 上海艾为电子技术股份有限公司 | Decoding method, device, decoder, readable storage medium and electronic equipment |
| CN115118386B (en) * | 2022-06-21 | 2024-04-12 | 上海艾为电子技术股份有限公司 | Decoding method, decoding device, decoder, readable storage medium and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108551387A (en) | A kind of BMC code self-adaptings decoding system and coding/decoding method | |
| CN104820812B (en) | The coding/decoding method and decoding apparatus of a kind of miller code of subcarrier modulation | |
| CN108551433A (en) | The decoding system and coding/decoding method of BMC codes | |
| CN208768080U (en) | A kind of BMC code self-adapting decoding system | |
| JP5325107B2 (en) | Serial digital data communication interface | |
| CN103297060B (en) | A kind of decoding circuit being applicable to two-forty correction miller coding signal | |
| CN108512552A (en) | A kind of the decoding system and coding/decoding method of Manchester code | |
| CN108390752A (en) | Signal acceptance method | |
| AU672861B2 (en) | Method and apparatus for discriminating computer network signals | |
| CN104639176B (en) | The asynchronous decoder and method of BMC signals | |
| CN109327366A (en) | A kind of high speed 1553B bus signals decoder design method | |
| US7277478B2 (en) | Method for transmitting data between a base station and a transponder | |
| CN100458825C (en) | Ultrahigh frequency RFID reader baseband signal decoding method | |
| CN104639482B (en) | Decode the decoder for the BPSK modulated signals that TYPE B cards are sent | |
| US8315292B2 (en) | Communication apparatus | |
| CN211018863U (en) | Decoding system of BMC (baseboard management controller) code | |
| SE515886C2 (en) | Methods of data transfer and data transfer device operating at two frequencies | |
| CN103595418B (en) | Decode the decoder for the TYPE A 847K data rate signals that card reader is sent | |
| CN101964668A (en) | Difference frequency hopping communication method based on correlation capture of m sequence | |
| CN114189314B (en) | BMC signal receiving method and device, USB power supply and readable storage medium | |
| CN110865957A (en) | Data receiving method and device of UART interface | |
| CN104242953A (en) | Decoder for one-out-of-four mode signal | |
| CN112688892B (en) | Subcarrier detection method, carrier signal demodulation method and demodulation device | |
| CN204244256U (en) | A kind of multichannel E1 separates frame system | |
| CN104242952B (en) | 256 select 1 mode signal decoder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 519000 2706, No. 3000, Huandao East Road, Hengqin new area, Zhuhai, Guangdong Applicant after: Zhuhai Yiwei Semiconductor Co.,Ltd. Address before: Room 105-514, No.6 Baohua Road, Hengqin New District, Zhuhai City, Guangdong Province Applicant before: AMICRO SEMICONDUCTOR Co.,Ltd. |
|
| CB02 | Change of applicant information |