CN104242952B - 256 select 1 mode signal decoder - Google Patents
256 select 1 mode signal decoder Download PDFInfo
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- CN104242952B CN104242952B CN201310250221.XA CN201310250221A CN104242952B CN 104242952 B CN104242952 B CN 104242952B CN 201310250221 A CN201310250221 A CN 201310250221A CN 104242952 B CN104242952 B CN 104242952B
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Abstract
1 mode signal decoder is selected the invention discloses card reader in a kind of decoding ISO/IEC15693 agreements is sent 256, including：One high level length counter, a preamble detecting circuit, a data decoding circuit, postamble detection circuit, one receives Signal coding error detection logic circuit, a Status Flag generation circuit.High level length of the present invention between high level length counter counts groove, obtains count value cnt；Referring next to ISO/IEC15693 agreements, this different coding characteristic of the high level length between the groove between different coding, then mated condition marking signal are utilized, it is possible to detect frame head, postamble, and data are decoded and produced with reception Signal coding error flag signal.The present invention can improve support scope of the decoder to recess width, and can improve its antijamming capability.
Description
Technical field
1 mode signal decoder is selected the present invention relates to card reader in a kind of decoding ISO/IEC15693 agreements is sent 256.
Background technology
1 mode signal is selected to have frame head, data and the species of postamble 3 in card reader is sent in ISO/IEC15693 agreements 256
Type.Wherein：
Fig. 1 is the frame head waveform diagram that 1 mode signal is selected in card reader is sent in ISO/IEC15693 agreements 256, figure
Middle transverse axis is the time, and the longitudinal axis is envelope range value.Card reader first sends out the low level envelope signal of 128 carrier cycles, then sends out 768
The high level envelope signal of carrier cycle, finally sends out the low level envelope signal of 128 carrier cycles, and carrier frequency is
13.56M。
Fig. 2 is 256 of card reader transmission in the ISO/IEC15693 agreements waveform for selecting that the data value of 1 mode signal is 225
When transverse axis is that 0 to 255 marks on time, transverse axis have gone out contained in 1 data encoding time section 256 in schematic diagram, figure
Between groove, the longitudinal axis is envelope range value.In Fig. 2 it can be seen that each data encoding time section includes 256 time slots, low level groove
Which occur in time slot, corresponding data are exactly the sequence number of this time slot.The data that sending value is 225 are shown in Fig. 2
Coding waveforms, it can be seen that now low level groove occurs in the 225th time slot.
Fig. 3 is that transverse axis is the time in the waveform diagram of the 225th time slot containing groove in Fig. 2, figure, and the longitudinal axis is envelope
Amplitude.The 224th, 225 and 226 totally 3 time slots are shown in figure, it is low level later half to have marked in the 225th time slot
Section and the front half section for high level.I.e. in the 255th time slot of the groove containing low level, low level is that occur in the second half section
, each time slot is containing 256 carrier cycles, wherein preceding 128 carrier cycles are high level envelope, rear 128 carrier cycles
For low level envelope.
Fig. 4 is the postamble waveform diagram that 1 mode signal is selected in card reader is sent in ISO/IEC15693 agreements 256, figure
Middle transverse axis is the time, and the longitudinal axis is envelope range value.Card reader first sends out the high level envelope signal of 256 carrier cycles, then sends out 128
The low level envelope signal of carrier cycle, finally sends out the high level envelope signal of 128 carrier cycles.
Fc is carrier frequency 13.56M in above-mentioned figure.
In ISO/IEC15693 agreements, the normal frames that card reader is sent are by frame head, and data add postamble to constitute again.Read in addition
Card device can also individually send out postamble waveform, i.e., do not send out frame head and data, only send out postamble waveform.
The content of the invention
The technical problem to be solved in the present invention is to provide 256 that card reader in a kind of decoding ISO/IEC15693 agreements is sent
1 mode signal decoder is selected, support scope of the decoder to recess width can be improved, its antijamming capability is improved.
In order to solve the above technical problems, card reader is sent in the decoding ISO/IEC15693 agreements of the present invention 256 select 1 mould
Formula decoding signals, the clock exported is demodulated as clock signal using analog radio frequency demodulation module, including：
One high level length counter, the subcarrier envelope signal for demodulating output in analog radio frequency demodulation module is high level
When, the clock signal is counted, obtains and exports counter value signal, the counter value signal is high level length；Institute
The count range for stating counter value signal is 0~30688, no longer cumulative to counter value signal when meter is to 130688；In the pair
When carrier envelope signal is low level, the counter value signal clear 0；
One preamble detecting circuit, is connected with the high level length counter, for detection frame bow wave shape, produces frame head
Marking signal；
One data decoding circuit, is connected with the high level length counter and preamble detecting circuit, for detecting number
According to waveform, decoding data signal is produced；
One postamble detects circuit, is connected with the high level length counter and data decoding circuit, for detection frame
Coda wave shape, produces postamble waveform signal；
One receives Signal coding error detection logic circuit, with the high level length counter and data decoding circuit phase
Connection, Signal coding mistake is received for detecting, is produced and is received Signal coding error flag signal；
One Status Flag generation circuit, with the preamble detecting circuit, receive Signal coding error detection logic circuit and
Postamble detection circuit is connected, and for producing Status Flag signal, distinguishes the different reception stages.
High level length of the present invention between high level length counter counts groove, obtains count value cnt.Referring next to
ISO/IEC15693 agreements, using this different coding characteristic of high level length between the groove between different coding, then coordinate shape
State marking signal, it is possible to detect frame head, postamble, and data are decoded and produced with reception Signal coding error flag signal.
The present invention can improve support scope of the decoder to recess width, and can improve its antijamming capability.
The present invention with reference to ISO/IEC15693 agreements, using the high level length between the groove between different coding it is different this
Coding characteristic is decoded, and by setting suitable threshold value distinguishes different coding waveforms, thus can be by adjusting threshold value
To coordinate the demodulation feature of simulation radio circuit, different coding waveforms are distinguished to the full extent, so as to correctly be decoded
Value.
Overall structure of the present invention is clear, and the type of error that can be detected is also complete, is easy to hardware to realize.
Brief description of the drawings
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is the 256 frame head waveform diagrams for selecting 1 mode signal；
Fig. 2 is 256 waveform diagrams for selecting that the data value of 1 mode signal is 225；
Fig. 3 is the waveform diagram of the 225th time slot containing groove in Fig. 2；
Fig. 4 is the 256 postamble waveform diagrams for selecting 1 mode signal；
Fig. 5 is 256 structured flowcharts for selecting 1 mode signal decoder.
Embodiment
Shown in Figure 5, card reader is sent in the decoding ISO/IEC15693 agreements 256 select 1 mode signal to decode
Device, demodulates the clock rf_clk signals 1 exported as clock signal using analog radio frequency demodulation module, utilizes different coding sequence
High level length difference between groove realizes decoding；Utilization state marking signal judges that card reader is waiting the reception frame head stage
Or receiving data and postamble stage；Data and postamble stage are being received, by the conjunction for judging the high level length between groove
Method, Signal coding error flag is received to provide；There is provided 2 kinds of postamble detection modes, respectively detect whole frame in postamble with
And the postamble in individual frames.
The decoder has 3 input signals, is respectively：
A, the clock rf_clk signals 1 of analog radio frequency demodulation module demodulation output.
B, the subcarrier envelope signal rf_dout signals 2 of analog radio frequency demodulation module demodulation output.
C, mark need detection individual frames EOF（Postamble）Signal det_eof_alone_win signals 9.
The decoder has 4 output signals, is respectively：
A, decoding data signal dec_dout signals 8, bit wide are 8.
B, frame head marking signal sof_flag signals 4.
C, postamble marking signal eof_flag signals 6.
D, reception Signal coding error flag signal bit_coding_err signals 5.
The decoder includes：One high level length counter, a preamble detecting circuit, a data decoding circuit, a frame
Tail detects circuit, and one receives Signal coding error detection logic circuit, a Status Flag generation circuit.Same sequence number signal in figure
Port is to be connected with each other.
The high level length counter, the subcarrier envelope signal rf_ of output is demodulated in analog radio frequency demodulation module
When dout signals 2 are high level, the clock rf_clk signals 1 are counted, obtains and exports count value cnt signals 3, should
Count value cnt signals 3 are high level length；The count range of the count value cnt signals 3 is 0~30688, so counting
Value cnt signals 3 have 17；It is no longer cumulative to count value cnt signals 3 when meter is to 130688；In the subcarrier envelope signal
When rf_dout signals 2 are low level, the count value cnt signals 3 clear 0.
The preamble detecting circuit, by a pre- judgement logic circuit, a conclusive judgement logic circuit is constituted.Frame head
High level length between two grooves is that 3*256 is 768 carrier cycles, then exported when the Status Flag generation circuit
Status Flag signal dec_state signals 7 are initial value, and the pre- judgement logic circuit passes through the subcarrier envelope signal
When rf_dout signals 2 detect groove generation, then the scope of count value cnt signals 3 is judged, if scope is in 768-N_
In the range of slew to 768+N_slew, just produce anticipation and determine marking signal sof_flag_t, wherein N_slew allows for simulation
After the demodulated envelope deformation that demodulator circuit is caused, the surplus reserved, generally not greater than 64 integer.According to ISO/
Recurrent groove is at least after 128 carrier cycles after IEC15693 agreements, second groove of frame head, so, first
The anticipation marking signal sof_flag_r that determines is latched when groove occurs.The conclusive judgement logic circuit, is being adjudicated in advance
Marking signal sof_flag_r is 1, and count value cnt signals 3 are equal to setting value N_sof_high_least and the state mark
The Status Flag signal dec_state signals 7 of will generation circuit output are initial value, when this 3 conditions are simultaneously effective, are produced most
Whole frame head marking signal sof_flag signals 4.Wherein described setting value N_sof_high_least for no more than 128 it is whole
Number.At the time of the groove occurs, it can be judged by the edge of the subcarrier envelope signal rf_dout signals 2.
The data decoding circuit, the decode logic computing cnt [17 following for realizing:8]-（255-dec_dout）,
Result of calculation is designated as dec_dout_t；Wherein cnt [17:8] the 17th to the 8th of the count value cnt signals 3, dec_ are represented
Dout is the upper decoding data signal 8 that the data decoding circuit is exported.When groove occurs, dec_dout_t is stored in
It is exactly this decoding data signal dec_dout signals 8 of the data decoding circuit output in trigger.It is described receiving
After the frame head marking signal sof_flag signals 4 of preamble detecting circuit output, then the decoding data signal dec_dout is believed
Numbers 8 initial value is set to 255.
According to the groove in one data encoding time section of ISO/IEC15693 agreements and the high level between previous groove
Length is that count value cnt signals 3 can be expressed as N*256+128, wherein, N is integer, and N can be by count value cnt signals
3 value is obtained after 8 after removing, and " * " represents multiplication sign.This N is left after subtracting the groove of previous data encoding time section
High level length N_left, the data value dec_dout just decoded, i.e. decoding data signal dec_dout signals 8.Its
In, N_left can subtract upper decoded data values dec_dout signals 8 to obtain by fixed number 255.Due to frame head ripple
There is no high level after 2nd groove of shape, it is similar with the coding waveforms of data 255, so receiving frame head marking signal
After sof_flag signals 4, the initial value of decoding data signal dec_dout signals 8 is set to 255.
The postamble detects circuit, and by a pre- judgement logic circuit, a conclusive judgement logic circuit is constituted.
Pre- 2 parts of judgement logic circuit point, detect the postamble in the postamble and individual frames in whole frame respectively.
Detect the postamble of whole frame, the following logical operation for realizing, cnt- (255-dec_dout) * 256, if meter
Calculate result and pre- decision signal eof_flag_t0 is produced between 256-N_slew to 256+N_slew, just, wherein, N_slew is
After the demodulated envelope deformation caused in view of analog demodulation circuit, the surplus reserved, generally not greater than 64 integer.According to
High level length between ISO/IEC15693 agreements, the previous groove of groove distance of postamble is 256+N_left*256, so
When Status Flag signal dec_state signals 7 are inverse values, count value cnt signals 3 subtract N_left*256 value,
If its result is between 256-N_slew to 256+N_slew, pre- decision signal eof_flag_t0 is just produced.
When detecting the postamble of individual frames, because postamble waveform has the high level of 256 carrier cycles before groove, so
When groove occurs, the value of count value cnt signals 3 is judged, when this value is more than 255, just produce pre- decision signal eof_flag_
t1。
Needed to detect individual frames EOF signal det_eof_alone_win signals 9 according to the mark of input to select anticipation
Certainly 1 in signal eof_flag_t0 and pre- decision signal eof_flag_t1 determines marking signal eof_ as final anticipation
flag_t.Because postamble waveform at least keeps the high level of 128 carrier cycles after groove, so when groove occurs, first
Anticipation determine marking signal eof_flag_r latch.
The conclusive judgement logic circuit, judges that anticipation is determined marking signal eof_flag_t, count value cnt signals 3 and shape
State marking signal dec_state signals 7；If anticipation is determined, marking signal eof_flag_t is equal to 1, and count value cnt signals 3 are equal to
N_eof_high_least, Status Flag signal dec_state signal 7 is the value after upset, and this 3 conditions are met simultaneously, then
Produce and output frame tail marking signal eof_flag signals 6, wherein N_eof_high_least be generally not greater than 128 it is whole
Number.
The reception Signal coding error detection logic circuit, is made up of 3 decision logic circuits, judges respectively in coding
Groove between high level length it is long, the high level length between groove is too short and groove location does not receive signals to 3 kinds and compiled
Code mistake.According to data encoding feature, it is possible that above-mentioned 3 kinds of receptions Signal coding mistake.
The long logic circuit of high level length between groove is adjudicated, whether the value of detection count value cnt signals 3 exceedes
130688, if it exceeds just going out the long code error mark in groove interval.High level length between two grooves most long situation
It is 0 to occur in previous data, and latter data are 255, at this moment, and the high level length of two recessed spacings of tanks is (255*
256) * 2+128 are 130688.So detection count value cnt signals 3, when count value cnt signals 3 be judged to more than 130688, just it is recessed
High level length between groove is long.
The too short logic circuit of high level length between groove is adjudicated, when groove occurs, cnt- (255-dec_ are judged
Dout) whether * 256 be less than 128-N_slew, if it is, the high level length being just judged between groove is too short, wherein N_slew is same
After the demodulated envelope deformation that the analog demodulation circuit that sample allows for is caused, the surplus reserved, generally not greater than 64 integer.
High level length between two grooves most short situation occurs in previous data to be 255, and latter data are 0, at this moment, interval
For 128.So remaining high level is long after the first groove for count value cnt signals 3 being subtracted previous data encoding time section
Degree is cnt-N_left*256, if result is less than 128-N_slew, then the high level length being just judged between groove is too short.
Judge that groove location to logic circuit, when groove occurs, does not judge cnt- (255-dec_dout) * 256, if
As a result not between 256-N_slew to 256+N_slew, also not in N_value*256+128-N_slew to N_value*256+
Between 128+N_slew, then be judged to groove location not right.Wherein N_slew equally allows for what analog demodulation circuit was caused
After demodulated envelope deformation, the surplus reserved, generally not greater than 64 integer, arbitrary integer during N_value can use 0 to 255.
According to data encoding feature, the high level length between two grooves is N*256+128 carrier cycle, if count value cnt
Signal 3 subtracts remaining high level length i.e. cnt-N_left*256 after the groove of previous data encoding time section, then
Obtained result should be just N_value*256+128, and wherein N_value is exactly this encoded radio, that is to say, that 0 can be taken to arrive
Arbitrary integer in 255.And if if a data followed by postamble, then cnt-N_left*256 should be just 256, so
If this value is not between 256-N_slew to 256+N_slew, also not in N_value*256+128-N_slew to N_
Between value*256+128+N_slew, then be just judged to groove location not right.
Just go out to receive Signal coding error flag when being not detected by frame head to shield, so needing to judge three of the above
Any one of mistake occurs after Status Flag signal dec_state signals 7 is the values after upset, just goes out to receive Signal coding
Error flag signal bit_coding_err signals 5.That is, after the upset of Status Flag signal dec_state signals 7,
Any one generation of above-mentioned 3 kinds of receptions Signal coding mistake then produces and exports reception code error marking signal bit_
Coding_err signals 5.
The Status Flag generation circuit, after frame head marking signal sof_flag signal 4 are received, its state mark exported
Will signal dec_state signals 7 are overturn, and code error marking signal bit_coding_err signals 5 or postamble are received when receiving
After marking signal eof_flag signals 6, its Status Flag signal dec_state signal 7 exported reverts to initial value.Due to not
When detecting frame head, reception code error can be reported by mistake, in addition, frame head be also only capable of frame start be detected, data decoding and it is complete
The postamble detection of whole frame is also only capable of just proceeding by after in preamble detecting, so needing to distinguish detection frame head by Status Flag
State phase and detection data and postamble stage.
The present invention with 256 of card reader transmission ISO/IEC15693 agreements suitable for selecting 1 Signal coding mode identical
Signal.
The present invention is described in detail above by embodiment, but these are not constituted to the present invention's
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (10)
1. card reader is sent in a kind of decoding agreements of ISO/IEC 15693 256 select 1 mode signal decoder, it is characterised in that
The clock exported is demodulated as clock signal using analog radio frequency demodulation module, including：
One high level length counter, when the subcarrier envelope signal that analog radio frequency demodulation module demodulates output is high level,
The clock signal is counted, obtains and exports counter value signal, the counter value signal is high level length；The meter
The count range of numerical signal is 0~30688, no longer cumulative to counter value signal when meter is to 130688；In the subcarrier
When envelope signal is low level, the counter value signal clear 0；
One preamble detecting circuit, is connected with the high level length counter, for detection frame bow wave shape, produces frame head mark
Signal；
One data decoding circuit, is connected with the high level length counter and preamble detecting circuit, for detecting data wave
Shape, produces decoding data signal；
One postamble detects circuit, is connected with the high level length counter and data decoding circuit, for detection frame coda wave
Shape, produces postamble waveform signal；
One receives Signal coding error detection logic circuit, is connected with the high level length counter and data decoding circuit
Connect, Signal coding mistake is received for detecting, produce and receive Signal coding error flag signal；
One Status Flag generation circuit, with the preamble detecting circuit, reception Signal coding error detection logic circuit and postamble
Detection circuit is connected, and for producing Status Flag signal, distinguishes the different reception stages.
2. decoder as claimed in claim 1, it is characterised in that：The Status Flag generation circuit, when receiving the frame head
After the frame head marking signal for detecting circuit output, its Status Flag signal exported upset；Signal coding mistake is received when receiving
After the postamble marking signal for receiving Signal coding error flag signal or postamble detection circuit output for detecting logic circuit output,
Its Status Flag signal exported reverts to initial value.
3. decoder as claimed in claim 1 or 2, it is characterised in that：The preamble detecting circuit, in Status Flag production
The Status Flag signal of raw circuit output is initial value, when detecting groove generation, then judges that the high level length is counted
The scope of the counter value signal of device output, if in the range of 768-N_slew to 768+N_slew, producing anticipation award of bid will
Signal；And anticipation marking signal of determining is latched when groove occurs；
Marking signal is determined for " 1 " in the anticipation, and the counter value signal is equal to setting value, and the Status Flag signal is initial
Value, when this 3 conditions are simultaneously effective, then produce and exports frame header will signal.
4. decoder as claimed in claim 3, it is characterised in that：The N_slew is the integer less than or equal to 64；It is described to set
Definite value is the integer less than or equal to 128.
5. decoder as claimed in claim 1, it is characterised in that：The data decoding circuit, the following decoding for realizing
Logical operation cnt [17:8]-(255-dec_dout), result of calculation is designated as dec_dout_t；Wherein, cnt [17:8] institute is represented
State the counter value signal of high level length counter output the 17th to the 8th, dec_dout is that the data decoding circuit is defeated
The upper decoding data signal gone out；When groove occurs, dec_dout_t is stored in a trigger, then produces and exports this
Secondary decoding data signal.
6. decoder as claimed in claim 5, it is characterised in that：Receiving the frame header of the preamble detecting circuit output
After will signal, then the initial value of the decoding data signal is set to 255.
7. decoder as claimed in claim 1, it is characterised in that：The postamble detects circuit, by a pre- judgement logic circuit,
One conclusive judgement logic circuit is constituted；
The pre- judgement logic circuit, detects the postamble in the postamble and individual frames in whole frame respectively；
The postamble of whole frame is detected, when the Status Flag signal that the Status Flag generation circuit is exported is inverse values, is used for
Realize following logical operation, cnt- (255-dec_dout) * 256, if result of calculation is in 256-N_slew to 256+N_
Between slew, then the first pre- decision signal is produced；Wherein, " * " represents multiplication sign, and dec_dout exports for the data decoding circuit
A upper decoding data signal, cnt be the high level length counter export counter value signal；
The postamble of individual frames is detected, when groove occurs, the counter value signal of the high level length counter output is judged
Value, if greater than 255, then produces the second pre- decision signal；
The first pre- decision signal or the second pre- judgement letter according to the mark of input needs detection individual frames postamble signal behavior
Number determined marking signal as anticipation；And when groove occurs, by the anticipation award of bid will signal latch；
The conclusive judgement logic circuit, judges that the anticipation is determined marking signal, counter value signal and Status Flag signal；If
Anticipation determines marking signal equal to 1, and counter value signal is equal to N_eof_high_least, and Status Flag signal is the value after upset,
This 3 conditions are met simultaneously, then are produced and output frame tail marking signal.
8. decoder as claimed in claim 7, it is characterised in that：The N_eof_high_least is less than or equal to 128
Integer；N_slew is the integer less than or equal to 64.
9. decoder as claimed in claim 1, it is characterised in that：The reception Signal coding error detection logic circuit, bag
Include：
The long logic circuit of high level length between groove is adjudicated, the count value letter of the high level length counter output is detected
Number value whether more than 1664, if it does, then produce the long error flag in groove interval；
The too short logic circuit of high level length between groove is adjudicated, when groove occurs, cnt- (3-dec_dout) * 256 is judged
Whether 128-N_slew is less than, if it is, producing the too short error flag of high level length between groove；
Judge that groove location to logic circuit, when groove occurs, does not judge cnt- (3-dec_dout) * 256, if result is not
Between 256-N_slew to 256+N_slew, also not in N_value*256+128-N_slew to N_value*256+128+N_
Between slew, then groove location is produced not to error flag；
Wherein, " * " represents multiplication sign, and dec_dout is a upper decoding data signal for the data decoding circuit output, and cnt is
The counter value signal of the high level length counter output；
After the Status Flag signal upset that the Status Flag generation circuit is exported, if producing the above-mentioned long mistake in groove interval
The too short error flag of high level length and groove location between mark, groove be not to appointing in 3 kinds of error flags of error flag by mistake
Meaning is a kind of, then produces and export reception Signal coding error flag signal.
10. decoder as claimed in claim 9, it is characterised in that：The N_slew is the integer less than or equal to 64；The N_
Value is the arbitrary integer in 0 to 255.
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| CN201310250221.XA CN104242952B (en) | 2013-06-21 | 2013-06-21 | 256 select 1 mode signal decoder |
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| CN101841385A (en) * | 2009-03-20 | 2010-09-22 | 天际微芯(北京)科技有限公司 | Method for indicating frame ending |
| CN102833036A (en) * | 2011-06-15 | 2012-12-19 | 株式会社电装 | Coding apparatus, coding method, data communication apparatus, and data communication method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841385A (en) * | 2009-03-20 | 2010-09-22 | 天际微芯(北京)科技有限公司 | Method for indicating frame ending |
| CN102833036A (en) * | 2011-06-15 | 2012-12-19 | 株式会社电装 | Coding apparatus, coding method, data communication apparatus, and data communication method |
Non-Patent Citations (1)
| Title |
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| 基于ISO/IEC15693协议的射频识别系统设计;刘志宇等，;《杭州电子科技大学学报》;20061231;第26卷(第6期);第53-56页 * |
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