CN105718835B - A kind of number shaping circuit - Google Patents
A kind of number shaping circuit Download PDFInfo
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- CN105718835B CN105718835B CN201610024018.4A CN201610024018A CN105718835B CN 105718835 B CN105718835 B CN 105718835B CN 201610024018 A CN201610024018 A CN 201610024018A CN 105718835 B CN105718835 B CN 105718835B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
- G06K7/10118—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the sensing being preceded by at least one preliminary step
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/0008—General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
- G06K7/10297—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves arrangements for handling protocols designed for non-contact record carriers such as RFIDs NFCs, e.g. ISO/IEC 14443 and 18092
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Abstract
The invention discloses a kind of digital shaping circuits.Number shaping circuit provided in this embodiment includes: effective failing edge detection device and low level recovery device；The demodulated envelope signal and carrier clock that effective failing edge detection device is used to be exported according to analog demodulation circuit carry out shaping to demodulated envelope signal, pseudo- low level is carried out to the failing edge signal obtained after shaping and filters out processing, effective failing edge signal is exported, and effective failing edge signal is transferred to low level recovery device；Low level recovery device is used to generate shaping envelope signal according to effective failing edge signal and carrier clock.The present invention solves problem poor to the fault-tolerant ability of the generally existing decoding circuit of decoding of non-contact IC card in the prior art and that the anti-fake low level ability of decoding circuit is poor.
Description
Technical field
The present invention relates to decoding technique and digital field of circuit technology, espespecially a kind of digital shaping circuit.
Background technique
Contact-free integrated circuit (Integrated Circuit Card, referred to as are as follows: IC) card has been widely used in use
In the daily life at family, such as various types of bus cards, residents ' health card, the ID card, financial IC card, near-field communication
(Near Field Communication, referred to as are as follows: NFC) equipment and radio frequency identification (Radio Frequency
Identification, referred to as are as follows: RFID) electronic tag etc..
International Organization for standardization (International Organisation for Standardisation, referred to as are as follows:
ISO) and International Electrotechnical Commission (IEC) (International Electrotechnical Commission, referred to as are as follows:
IEC the international standard of non-contact IC card, i.e. ISO/IEC14443 agreement) have been formulated.With determining in ISO/IEC14443 agreement
It is explained for the TPYEA type card of justice, in the information exchange of TPYEA type card and card reader, card reader is with modified Miller code
The format of (also referred to as delay modullation code) issues data information；In the downlink of information, the quality of modified Miller code is by many
The influence of factor, such as whether field strength is stable, whether accurate, rate the difference of analog circuit demodulation, normally, by above-mentioned various
The influence of factor, after information reaches the chip interior of TPYEA type card, information quality can be reduced, and show as the low electricity of miller coding
Flat (pause) can be extended, compressed or be demodulated the pseudo- low level of generation, so as to cause decoding error.It is apparent that non-contact logical
Letter is easy the interference by environment for contact communication, and stability is poor, therefore, how real in complex environment
The problem of accurate decoding of existing non-contact IC card is current urgent need to resolve.
It is poor to the fault-tolerant ability of the generally existing decoding circuit of decoding of non-contact IC card in the prior art, and decoding
The poor problem of the anti-fake low level ability of circuit.
Summary of the invention
It is right in the prior art to solve in order to solve the above-mentioned technical problems, the present invention provides a kind of digital shaping circuit
The fault-tolerant ability of the generally existing decoding circuit of decoding of non-contact IC card is poor and the anti-fake low level ability of decoding circuit
Poor problem.
In a first aspect, a kind of digital shaping circuit provided by the invention, comprising: effective failing edge detection device and low level
Recovery device；
When demodulated envelope signal and carrier wave that effective failing edge detection device is used to be exported according to analog demodulation circuit
Clock carries out shaping to the demodulated envelope signal, carries out pseudo- low level to the failing edge signal obtained after shaping and filters out processing, defeated
Effective failing edge signal out, and effective failing edge signal is transferred to the low level recovery device；
The low level recovery device is used to generate shaping packet according to effective failing edge signal and the carrier clock
Network signal.
In the first possible implementation of the first aspect, effective failing edge detection device includes failing edge inspection
Survey unit, pseudo- low level filters out unit and the first logic unit；
Wherein, the failing edge detection unit includes the first register, the second register and the second logic unit, and described the
The input of one register includes the carrier clock and the demodulated envelope signal, and the input of second register includes described
First time delayed signal of carrier clock and first register output, the input of second logic unit includes described first
Second time delayed signal of time delayed signal and second register output, the output of second logic unit are to the demodulation
Envelope signal carries out the failing edge signal after shaping；
It includes the first counter and third register, the input packet of first counter that the puppet low level, which filters out unit,
Include the output of the carrier clock and first logic unit, the input of the third register include the carrier clock and
First count signal of the first counter output, the output of the third register are to filter pseudo- low level signal；
First logic unit is first and door, and the input of first logic unit includes the pseudo- low level letter of the filter
Number and the failing edge signal, export as effective failing edge signal.
According to the first possible implementation of first aspect, in the second possible implementation, described second
Logic unit includes or door and second and door, and described or door input is first postpones signal, and described first is defeated with door
Enter for second time delayed signal and described or door output, described second and the output of door are the failing edge signal.
According to the first possible implementation of first aspect, in the third possible implementation, described first
Counter is used for when each effective failing edge signal arrives, after the counting that preset quantity is carried out to the carrier clock, output
First count signal.
According to the first possible implementation of first aspect, in the fourth possible implementation, described first
Counter is 6 bit counters.
In the fifth possible implementation of the first aspect, the low level recovery device include the second counter,
Third logic unit and the 4th register；
Wherein, the input of second counter includes effective failing edge signal and the carrier clock, and described
The input of three logic units includes the second count signal and described that effective failing edge signal, second counter export
The output of 4th register, the input of the 4th register include the defeated of the carrier clock and the third logic unit
Out, the output of the 4th register is the shaping envelope signal.
According to the 5th of first aspect the kind of possible implementation, in a sixth possible implementation, the third
Logic unit includes the first nor gate and the second nor gate, and the input of first nor gate includes the second signal and described
The output of 4th register, the input of second nor gate include effective failing edge signal and first nor gate
Output, the output of second nor gate are the output of the third logic unit.
According to the 5th of first aspect the kind of possible implementation, in the 7th kind of possible implementation, described second
Counter is used for when each effective failing edge signal arrives, after the counting that preset quantity is carried out to the carrier clock, output
Second count signal, wherein the gate time of the carrier clock of the preset quantity be 0.25 bit transfer it is lasting when
Between.
According to the 5th of first aspect the kind of possible implementation, in the 8th kind of possible implementation, described second
Counter is 4 bit counters.
According to first aspect, first aspect the first into the 8th kind of possible implementation any one, the 9th
In the possible implementation of kind, the number shaping circuit further includes rate selection device, the input of the rate selection device
Including the shaping envelope signal, demodulated envelope signal and rate selecting signal, the number shaping circuit is used for according to input
To the rate selecting signal in the rate selection device, the shaping envelope signal or the demodulated envelope signal are selected, and
Selected envelope signal is exported by the rate selection device.
Number shaping circuit provided by the invention, the solution that analog demodulation circuit is exported by effective failing edge detection device
It adjusts envelope signal to carry out shaping, and filters out the pseudo- failing edge in the failing edge signal after shaping, obtain effective failing edge signal, then
Low level recovery processing is carried out by low level recovery device, it is available to higher with original envelope signal degree of closeness
Shaping envelope signal realizes and removes pseudo- low level to demodulated envelope signal, so that the envelope signal close to desirable is obtained,
It filters out pseudo- low level processing mode while the fault-tolerant ability of digital shaping circuit can be improved；The present invention solves the prior art
In it is poor to the fault-tolerant ability of the generally existing decoding circuit of decoding of non-contact IC card and decoding circuit is anti-fake low level
The poor problem of ability.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is a kind of structural schematic diagram of digital shaping circuit provided in an embodiment of the present invention；
Fig. 2 is the application scenarios schematic diagram for the digital shaping circuit that embodiment illustrated in fig. 1 provides；
Fig. 3 is that a kind of structure of effective failing edge detection device is shown in the digital shaping circuit that provides of embodiment illustrated in fig. 1
It is intended to；
Fig. 4 is a kind of schematic diagram of envelope signal defined in ISO/IEC14443 agreement；
A kind of structural schematic diagram of low level recovery device in the digital shaping circuit that Fig. 5 provides for embodiment illustrated in fig. 1；
Fig. 6 is the signal schematic representation for the digital shaping circuit that embodiment illustrated in fig. 1 provides；
Fig. 7 is the structural schematic diagram of another digital shaping circuit provided in an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable
Sequence executes shown or described step.
Above-mentioned have been described above is decoded existing some Universal Problems to non-contact IC card.Below by existing
There are several specific technical solutions in technology to be explained:
First, the technical solution of Patent No. " CN201510508213 ", by being under 106 bit rates (kbps) to rate
Low level between high level counted, whether in [0,90], [96,156], [160,222] and be greater than according to count value
224 these four situations decode current bit in conjunction with previous decoding data.But this method may be implemented to be correctly decoded
Range it is smaller, be typically only capable to support 106kbps rate.
Second, the technical solution of Patent No. " CN201310266357 ", using data " X " low level occur rule into
Row decoding, is utilized relatively-stationary low level failing edge as decoding standard, has reached and improved the fault-tolerant of decoding circuit
Ability and anti-interference ability.But this method cannot apply to basal rate, and can occur in data " X " second half section continuous
The low level greater than 140 nanoseconds (ns) when may malfunction.Bit period is determined by counting, and analog circuit loss is occurring
When clock, the problem of be easy to causeing clock that cannot be aligned with data.
Third, the technical solution of Patent No. " CN200910056988 " generate synchronous data using two-stage frequency divider
Clock, output and received radio frequency (Radio Frequency, referred to as are as follows: RF) signal to two-stage frequency divider carry out data solution
Code is, it can be achieved that a variety of traffic rates, there is certain jamproof ability.But the decoding circuit anti-interference ability is inadequate, specifically
The pseudo- low level less than 140ns can only be filtered out, the low level width tolerance being correctly decoded in the case where enhancing rate is relatively narrow.
4th, the technical solution of Patent No. " in Chinese patent CN201110240793 " uses RF module and number electricity
Road combines, and counts to the low level duration, when count value is identical as preset value, draws high marking signal, and will
The signal feeds back to RF module, RF module is resetted, so that low level to be reverted to the width of preset value.But the program cannot
The case where compatible low level compression, ideal low level cannot be recovered well when demodulation generates pseudo- low level.
As can be seen that the prior art is poor to the fault-tolerant ability of the generally existing decoding circuit of decoding of non-contact IC card,
And the problem that the anti-fake low level ability of decoding circuit is poor；Although fault-tolerant ability can be improved in some methods, however, can not
Improve the ability of anti-fake level simultaneously.
Technical solution of the present invention is described in detail below by specific embodiment, the following embodiment of the present invention
In digital shaping circuit be all set in the chip interior of non-contact IC card, which is usually located at analog demodulator
Between circuit and digital decoding circuit.The present invention provides following specific embodiment and can be combined with each other, for identical or
Similar concept or process may be repeated no more in some embodiments.
Fig. 1 is a kind of structural schematic diagram of digital shaping circuit provided in an embodiment of the present invention.As shown in Figure 1, this implementation
The digital shaping circuit 10 that example provides includes: effective failing edge detection device 100 and low level recovery device 200.
Wherein, the demodulated envelope signal and load that effective failing edge detection device 100 is used to be exported according to analog demodulation circuit
Wave clock carries out shaping to demodulated envelope signal, carries out pseudo- low level to the failing edge signal obtained after shaping and filters out processing, defeated
Effective failing edge signal out, and effective failing edge signal is transferred to low level recovery device 200.
Normally, low level rate to be decoded includes: the basic rate and enhancing rate of 106kbps, enhances rate packets
Include 212kbps, 424kbps and 848kbps.In the present embodiment, analog demodulation circuit is used for the information read according to card reader
Demodulated envelope signal is obtained, and in the case where enhancing rate, analog demodulation circuit can also be restored in entire bit period
Carrier clock out, but because of the difference of analog demodulation circuit, between the demodulated envelope signal and original envelope signal of acquisition
Difference can be especially big, shows that low level is compressed, extended, and demodulate pseudo- low level.Number provided in this embodiment is whole
The input of shape circuit 10 includes carrier clock, thus be suitable for enhancing rate in the case where, it is specifically, defeated to analog demodulation circuit
Demodulated envelope signal out carries out shaping, and the detailed process of shaping, which can be, extracts the failing edge of demodulated envelope signal,
Such as when each failing edge arrives, jump is high level, and becomes low level again after preset delay, by which
Signal after shaping is failing edge signal.However, in the failing edge signal, there may be pseudo- low levels, and hence it is also possible to filter out
Fall the pseudo- low level in failing edge signal, specifically, the duration between two low levels under special speed is relatively solid
Fixed, it is starting with first failing edge, the failing edge within the above-mentioned duration may be considered pseudo- low level, filter out
Pseudo- low level in the duration, next failing edge may be considered effective failing edge.
Low level recovery device 200 is used to generate shaping envelope signal according to effective failing edge signal and carrier clock.
Although effective failing edge detection device 100 in the present embodiment has got effective failing edge signal, this is effectively
Although failing edge signal can embody the low level distribution of original envelope signal, since effective failing edge signal is stealthily substituted in solution
Jumping after the failing edge arrival of network signal is high level, therefore the low and high level of effective failing edge signal and original envelope signal
Low and high level on the contrary, need to carry out low level recovery processing, that is, restore the shaping packet being closer to original envelope signal
Network signal wishes the ideal envelope signal that the digital shaping circuit provided through this embodiment obtains.
As shown in Fig. 2, the application scenarios schematic diagram of the digital shaping circuit provided for embodiment illustrated in fig. 1.The present invention is real
The digital shaping circuit 10 of example offer is applied between analog demodulation circuit 20 and digital decoding circuit 30, and three circuits
Module is respectively positioned in non-contact IC card, and analog demodulation circuit 20 is believed by the signal acquisition that card reader is transmitted to demodulated envelope
Number, in the case where enhancing rate, carrier clock can also be restored, the decoding for following digital shaping circuit 10.
In the downlink of data, letter may all will affect from the demodulation for being modulated to analog demodulation circuit 20 of card reader
Number quality, lead to differing greatly for demodulated envelope signal and original envelope signal, cause decoding error.It is provided in this embodiment
Digital shaping circuit 10 carries out shaping to demodulated envelope signal using digital circuit, is starting mark using low level failing edge
Demodulated envelope signals revivification is envelope signal ideally, makes the standard envelop forms for meeting agreement by will, and
The pseudo- failing edge in failing edge signal is filtered out, different types of analog demodulation circuit 20 can be compatible with.Number provided in this embodiment
Shaping circuit carries out filtering out pseudo- low level in specific treatment process by the failing edge signal for generating demodulated envelope signal
Processing, it is available to indicate effectively low level pulse signal, i.e., effective failing edge signal, to be believed with the effective failing edge
Based on number, in conjunction with basic principle low level in envelope signal, the envelope signal close to desirable can be recovered, is filtered out
Low level and the processing mode for restoring envelope signal all follow the principle and requirement of signal processing, therefore can effectively improve this reality
The fault-tolerant ability of the digital shaping circuit of example offer is provided.
Number shaping circuit provided in this embodiment, exports analog demodulation circuit by effective failing edge detection device
Demodulated envelope signal carries out shaping, and filters out the pseudo- failing edge in the failing edge signal after shaping, obtains effective failing edge signal,
Low level recovery processing is carried out by low level recovery device again, it is available to higher with original envelope signal degree of closeness
Shaping envelope signal, realize and pseudo- low level removed to demodulated envelope signal, so that the envelope obtained close to desirable is believed
Number, it filters out pseudo- low level processing mode while the fault-tolerant ability of digital shaping circuit can be improved；The present embodiment solves existing
Have that poor to the fault-tolerant ability of the generally existing decoding circuit of decoding of non-contact IC card in technology and decoding circuit is anti-fake low
The poor problem of the ability of level.
Below to the effective failing edge detection device 100 and low level recovery device 200 in embodiment illustrated in fig. 1 of the present invention
Specific structure do with exemplary illustration.
Optionally, Fig. 3 is a kind of effective failing edge detection device in the digital shaping circuit that provides of embodiment illustrated in fig. 1
Structural schematic diagram.As shown in figure 3, effective failing edge detection device 100 in the present embodiment include failing edge detection unit 110,
Pseudo- low level filters out unit 120 and the first logic unit 130；Wherein, failing edge detection unit 110 include the first register 111,
Second register 112 and the second logic unit 113, the input of the first register 111 include carrier clock and demodulated envelope letter
Number, the input of the second register 112 includes the first time delayed signal that carrier clock and the first register 111 export, the second logic
The input of unit 113 includes the second time delayed signal that the first time delayed signal and the second register 112 export, the second logic unit
113 output is that the failing edge signal after shaping is carried out to demodulated envelope signal.It includes the first meter that pseudo- low level, which filters out unit 120,
Number devices 121 and third register 122, the input of the first counter 121 include the defeated of carrier clock and the first logic unit 130
Out, the input of third register 122 includes the first count signal that carrier clock and the first counter 121 export, third deposit
The output of device 122 is to filter pseudo- low level signal.First logic unit 130 is first and door, the input packet of the first logic unit 130
The pseudo- low level signal of filter and failing edge signal are included, is exported as effective failing edge signal.In the concrete realization, second patrols the present embodiment
Volume unit 113 include or door and second and the input of door or door be the first postpones signal, first and the input of door are the second delay
The output of signal and/or door, second with the output of door is failing edge signal；Second logic unit 113 is used to believe the first delay
Number " logic NOT " and the second time delayed signal carry out " logical AND " operation.In effective failing edge detection device 100 shown in Fig. 3 not
The specific structure of second logic unit 113 is shown, which is made of simple logic gates, it is above-mentioned
Its specific structure is depicted.
The present embodiment carries out two-stage to demodulated envelope signal by failing edge detection unit 110 and synchronizes, and obtains failing edge letter
Number.Meanwhile in order to filter out the pseudo- low level on envelope, i.e. burr on failing edge signal, unit 120 is filtered out by pseudo- low level
It generates and filters pseudo- low level signal, failing edge when which is high level is effective failing edge, filters pseudo- low level
The method of the generation of signal is dragged down when previous effective failing edge arrives, and the first counter 121 carries out carrier clock pre-
The counting of quantity is set, completes to export the first count signal after counting.
It should be noted that shortest time between adjacent falling edges be 1 (elementry time unite, referred to as are as follows:
Etu), 1etu is specially 1 bit transfer duration, such as output first counts when can be set to count down to 0.75etu
Signal is drawn high at this point, pseudo- low level signal will be filtered；Then the failing edge signal that sampling obtains is done with pseudo- low level signal is filtered
" logical AND " operation has thus filtered out the pseudo- low level after effective failing edge in the 0.75etu time.In the concrete realization, right
The counting of 0.75etu can be presented as the counting to carrier clock, be to enhance common 212kbps and 424kbps in rate
Example is explained, under 212kbps rate, 1etu=64 carrier clock (clk), and 0.75etu=48clk；424kbps rate
Under, 1etu=32clk, 0.75etu=24clk may be implemented using 6bit counter to 48clk and 24clk in the case
The compatibility of counting.It is empirical value that 0.75etu is set as in the present embodiment, if value setting is smaller, such as is set as
0.5etu possibly can not filter out the pseudo- low level between two effective low levels, cause decoded in error；If the value setting compared with
Greatly, such as it is set as 0.9etu, card reader non-type for some periods, i.e. the duration between two failing edges is not
1etu, the 0.9etu being arranged at this time are likely larger than the duration between two low levels, in this way can filter out effective low level
Fall, equally will cause decoded in error.
It as described in Figure 4, is a kind of schematic diagram of envelope signal defined in ISO/IEC14443 agreement.Horizontal seat in Fig. 4
It is designated as the time (t), ordinate indicates the ratio of current field strength and initial field strength, i.e. H/Hinitial, a in figure is coefficient, hovs
It indicates to exceed HinitialValue, can be and exceed or exceed downwards upwards；From Fig. 4 it can be found that successively decreasing since envelope
During being incremented to smoothly to envelope, envelope is variation, during this period if the variation of envelope is not dull, and is changed
When larger, it is possible to pseudo- low level is demodulated, on the contrary, pseudo- low level will not be demodulated during envelope is steady.Therefore, with
One effective failing edge is initial time, and the pseudo- low level after filtering out in the 0.75etu time, which can be equivalent to, have been filtered out entirely
Pseudo- low level in envelope signal.
Optionally, a kind of structure of low level recovery device in the digital shaping circuit that Fig. 5 provides for embodiment illustrated in fig. 1
Schematic diagram.As shown in figure 5, the low level recovery device 200 in the present embodiment includes the second counter 210, third logic unit
220 and the 4th register 230；Wherein, the input of the second counter 210 includes effective failing edge signal and carrier clock, third
The input of logic unit 220 includes effective failing edge signal, the second count signal of the second counter 210 output and the 4th deposit
The output of device 230, the input of the 4th register 230 include the output of carrier clock and third logic unit 220, the 4th register
230 output is shaping envelope signal.In the concrete realization, third logic unit 220 may include first or non-to the present embodiment
Door and the second nor gate, the input of the first nor gate include the output of second signal and the 4th register 230, the second nor gate
Input includes the output of effective failing edge signal and the first nor gate, and the output of the second nor gate is third logic unit 220
Output.Low level recovery device 200 provided in this embodiment can be in first effective failing edge, by the 4th register 230
Output valve drag down, continue 0.25etu after the output valve of the 4th register 230 is drawn high, thus complete envelope recovery.
In the present embodiment, the second counter 210 is identical with the working principle of above-mentioned first counter 121 shown in Fig. 3,
I.e. when each low level arrives, after the counting that preset quantity is carried out to carrier clock, the second count signal is exported, wherein this
The gate time of the carrier clock of preset quantity is 0.25etu in embodiment；Equally with enhance in rate common 212kbps and
It is explained for 424kbps, under 212kbps rate, 0.25etu=16clk；Under 424kbps rate, 0.25etu=
The compatibility counted to 48clk and 24clk may be implemented using 4bit counter in the case by 8clk.It is arranged in the present embodiment
0.25etu be low level duration under normal conditions.
As shown in fig. 6, the signal schematic representation of the digital shaping circuit provided for embodiment illustrated in fig. 1.Fig. 6 is with data flow
The timing of digital shaping circuit 10 is described, from fig. 6, it can be seen that regardless of low level is broadened or presses for 0100 to 1101
Contracting, digital shaping circuit 10 can accurately be reduced to ideal situation, that is, restore original envelope signal, while under filtering out effectively
Pseudo- low level of the drop after in 0.75etu time range, so as to provide standard for subsequent digital decoding circuit 30
The envelope signal of change.
It should be noted that above-mentioned Fig. 1 is into digital shaping circuit 10 shown in fig. 5, the first register 111 to the 4th is posted
The input of storage 230 and the first counter 121 and the second counter 210 further includes power-on reset signal, in card reader
The data of reading non-contact type IC card, the i.e. non-contact IC card carry out reset setting when powering on.
The digital shaping circuit 10 that each embodiment provides shown in above-mentioned Fig. 1 to Fig. 5, input value includes analog demodulation circuit
20 carrier clocks restored, however, the clock quality between low period does not ensure in basal rate 106kbps, it cannot
The envelope signal for wishing to export is obtained using above-mentioned digital shaping circuit 10.In view of the above-mentioned problems, the present invention also provides a kind of numbers
Word shaping circuit 10, as shown in fig. 7, for the structural schematic diagram of another digital shaping circuit provided in an embodiment of the present invention.?
In the structure basis for the digital shaping circuit 10 that the various embodiments described above provide, number shaping circuit 10 provided in this embodiment is also wrapped
Rate selection device 300 is included, the input of rate selection device 300 includes shaping envelope signal, demodulated envelope signal and rate choosing
Signal is selected, digital shaping circuit 10 is used to select shaping packet according to the rate selecting signal being input in rate selection device 300
Network signal or demodulated envelope signal, and through-rate selection device 300 exports selected envelope signal.Fig. 7 is in the base of Fig. 1
It is shown on plinth.
In the concrete realization, above-mentioned rate selection device 300 can be a selector, shaping envelope signal therein, solution
Adjusting envelope signal is the input signal of data input pin in selector, and rate selecting signal can be " 1 " or " 0 ", for example,
When rate selecting signal is " 1 ", enhancing rate is represented, which selects in rate
When signal is " 0 ", basal rate is represented, which exports demodulated envelope signal.It should be noted that this hair
Bright embodiment does not limit the demodulated envelope signal for inputting the rate selection device 300, can be analog demodulation circuit in above-mentioned Fig. 2
The demodulated envelope signals of 20 outputs, can also be and carry out treated demodulated envelope signal by the prior art.
It is provided in this embodiment number shaping circuit 10, to enhancing rate under by being standardized to demodulated envelope signal
Shaping reaches identical purpose, and the circuit logic is simple, and anti-interference ability is very strong, and the number shaping circuit 10 passes through setting
Rate selection device 300 realizes the target of universality.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (8)
1. a kind of number shaping circuit characterized by comprising effective failing edge detection device and low level recovery device；
Effective failing edge detection device is used for the demodulated envelope signal and carrier clock pair exported according to analog demodulation circuit
The demodulated envelope signal carries out shaping, carries out pseudo- low level to the failing edge signal obtained after shaping and filters out processing, output has
Failing edge signal is imitated, and effective failing edge signal is transferred to the low level recovery device；
The low level recovery device is used to generate shaping envelope letter according to effective failing edge signal and the carrier clock
Number；
Wherein, effective failing edge detection device includes that failing edge detection unit, pseudo- low level filter out unit and the first logic
Unit；
Wherein, the failing edge detection unit includes the first register, the second register and the second logic unit, and described first posts
The input of storage includes the carrier clock and the demodulated envelope signal, and the input of second register includes the carrier wave
First time delayed signal of clock and first register output, the input of second logic unit include first delay
Second time delayed signal of signal and second register output, the output of second logic unit are to the demodulated envelope
Signal carries out the failing edge signal after shaping；
It includes the first counter and third register that the puppet low level, which filters out unit, and the input of first counter includes institute
State the output of carrier clock and first logic unit, the input of the third register includes the carrier clock and described
First count signal of the first counter output, the output of the third register are to filter pseudo- low level signal；
First logic unit is first and door, the input of first logic unit include the pseudo- low level signal of the filter with
The failing edge signal exports as effective failing edge signal；
The low level recovery device includes the second counter, third logic unit and the 4th register；
Wherein, the input of second counter includes effective failing edge signal and the carrier clock, and the third is patrolled
The input for collecting unit includes the second count signal and the described 4th of effective failing edge signal, second counter output
The output of register, the input of the 4th register include the output of the carrier clock and the third logic unit, institute
The output for stating the 4th register is the shaping envelope signal.
2. number shaping circuit according to claim 1, which is characterized in that second logic unit includes or door and the
Two and door, described or door input is first postpones signal, and described first and the input of door are second time delayed signal
It with the output of door is the failing edge signal with described or door output, described second.
3. number shaping circuit according to claim 1, which is characterized in that first counter is used for each effective
When failing edge signal arrives, after the counting that preset quantity is carried out to the carrier clock, first count signal is exported.
4. number shaping circuit according to claim 1, which is characterized in that first counter is 6 bit counters.
5. number shaping circuit according to claim 1, which is characterized in that the third logic unit includes first or non-
Door and the second nor gate, the input of first nor gate include the defeated of second count signal and the 4th register
Out, second nor gate input include effective failing edge signal and first nor gate output, described second
The output of nor gate is the output of the third logic unit.
6. number shaping circuit according to claim 1, which is characterized in that second counter is used for each effective
When failing edge signal arrives, after the counting that preset quantity is carried out to the carrier clock, second count signal is exported,
In, the gate time of the carrier clock of the preset quantity is 0.25 bit transfer duration.
7. number shaping circuit according to claim 1, which is characterized in that second counter is 4 bit counters.
8. number shaping circuit according to any one of claims 1 to 7, which is characterized in that the number shaping circuit
Further include rate selection device, the input of the rate selection device include the shaping envelope signal, demodulated envelope signal and
Rate selecting signal, the number shaping circuit are used for according to the rate selecting signal being input in the rate selection device,
The shaping envelope signal or the demodulated envelope signal are selected, and selected envelope is exported by the rate selection device
Signal.
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| CN201610024018.4A CN105718835B (en) | 2016-01-14 | 2016-01-14 | A kind of number shaping circuit |
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| CN201610024018.4A CN105718835B (en) | 2016-01-14 | 2016-01-14 | A kind of number shaping circuit |
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| CN105718835B true CN105718835B (en) | 2018-12-28 |
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| CN109412757B (en) * | 2018-12-07 | 2021-01-22 | 上海爱信诺航芯电子科技有限公司 | Modified Miller self-adaptive decoding method and device |
| CN110135548A (en) * | 2019-05-21 | 2019-08-16 | 上海明矽微电子有限公司 | A kind of digital means of high-frequency radio frequency identification chip demodulation blind area processing |
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| CN101873124A (en) * | 2010-05-24 | 2010-10-27 | 哈尔滨工程大学 | Self-adaptive threshold pulse amplified shaping circuit |
| CN101997557A (en) * | 2009-08-25 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Superregenerative receiving device and method |
| EP2352269A1 (en) * | 2008-12-30 | 2011-08-03 | State Grid Corporation of China | Service access method and system |
| CN105224894A (en) * | 2014-05-28 | 2016-01-06 | 上海华虹集成电路有限责任公司 | The circuit of the type A signal that card reader sends in decoding ISO/IEC14443 agreement |
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| EP2352269A1 (en) * | 2008-12-30 | 2011-08-03 | State Grid Corporation of China | Service access method and system |
| CN101997557A (en) * | 2009-08-25 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Superregenerative receiving device and method |
| CN101873124A (en) * | 2010-05-24 | 2010-10-27 | 哈尔滨工程大学 | Self-adaptive threshold pulse amplified shaping circuit |
| CN105224894A (en) * | 2014-05-28 | 2016-01-06 | 上海华虹集成电路有限责任公司 | The circuit of the type A signal that card reader sends in decoding ISO/IEC14443 agreement |
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