CN114189314A - BMC signal receiving method and device, USB power supply and readable storage medium - Google Patents
BMC signal receiving method and device, USB power supply and readable storage medium Download PDFInfo
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Abstract
A BMC signal receiving method, a device, a USB power supply and a readable storage medium are provided. The method comprises the following steps: sequentially carrying out analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal; performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal; sampling the second-stage digital filtering result signal to obtain a sampling result signal; decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal; if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting from the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level; the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal. By applying the scheme, the reliability of BMC signal transmission can be improved.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a BMC signal receiving method, a device, a USB power supply and a readable storage medium.
Background
The Power Delivery (PD) protocol of the Type-C (Universal Serial Bus, USB) is a Power Delivery protocol based on the Type-C interface. The USB PD protocol supports various voltage and current combinations, can support 100W (20V/5A) power transmission to the maximum extent, and simultaneously supports power supply role conversion, thereby meeting the power supply requirements of most electronic equipment.
In the USB Type-C interface, a Configuration Channel (CC) line is used as a dedicated plug detection and PD communication Channel. It adopts half-duplex communication mechanism, uses two-way Mark Coding (BMC) to transmit data. The BMC coding belongs to a coding technology of phase modulation, and is a coding method for mixing a clock and data together for transmission. The signal encoded using the BMS is referred to as a BMS signal. The PD protocol allows for a certain frequency offset of the code.
However, in practical applications, since baud rate deviation exists between the transmitting end and the receiving end and the local clock precision is different, the communication channel is easily affected by the load of the transmission medium itself, high voltage and large current of the power supply and the ground wire, noise and the like. The communication channel is affected, which may cause the BMC signal to be interfered, causing the BMC signal to be distorted, eventually resulting in a communication failure.
Disclosure of Invention
The invention aims to solve the problems that: and the reliability of BMC signal transmission is improved.
In order to solve the above problem, an embodiment of the present invention provides a BMC signal receiving method, where the method includes: sequentially carrying out analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal; performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal; sampling the second-stage digital filtering result signal to obtain a sampling result signal; decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal; if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level; i is a positive integer; and when i is larger than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
The embodiment of the invention also provides a BMC signal receiving device, which comprises: the analog filter circuit is suitable for sequentially carrying out analog filtering on the received BMC signals; the first-stage digital filter circuit is suitable for performing first-stage digital filtering on the BMC signal after analog filtering to obtain a first-stage digital filtering result signal; the second-stage digital filter circuit is suitable for carrying out second-stage digital filtering on the first-stage digital filter signal to obtain a second-stage digital filter result signal; the sampling circuit is suitable for sampling the second-stage digital filtering result signal to obtain a sampling result signal; the decoding circuit is suitable for decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal; if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level; i is a positive integer; and when i is larger than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
The embodiment of the invention also provides a USB power supply, and the USB power supply comprises any one of the BMC signal receiving devices.
Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the steps of any one of the methods described above.
The embodiment of the present invention further provides a USB power source, which includes a memory and a processor, where the memory stores a computer program capable of running on the processor, and the processor executes any of the steps of the method when running the computer program.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
by applying the scheme of the invention, when the middle position of the ith bit time of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, the ith bit of the second-stage digital filtering result signal is set, otherwise, the ith bit is kept at a low level, so that the influence of interference pulses in the first-stage digital filtering result signal on the second-stage digital filtering can be reduced as much as possible, and the reliability of BMC signal transmission is improved. In addition, the middle position of the ith bit of the first-stage digital filtering result signal is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal, so that the second-stage digital filtering result of the current bit can be dynamically adjusted based on the baud rate and the duty ratio of the previous bit, communication failure caused by imbalance of the baud rates or the duty ratios of the sending end and the receiving end is avoided, and the reliability of BMC signal transmission is further improved.
Drawings
Fig. 1 is a flowchart of a BMC signal receiving method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a portion of the bit length of the BMC signal;
FIG. 3 is a schematic diagram of a normal waveform of the BMC signals without interference;
FIG. 4 is a waveform diagram of the BMC signal with interference;
fig. 5 is a schematic structural diagram of a BMC signal receiving apparatus 50 according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a USB power supply according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a BMC signal reception according to an embodiment of the present invention.
Detailed Description
The BMC coding belongs to a coding technology of phase modulation, and is a coding method for mixing a clock and data together for transmission. The characteristics of BMC coding are as follows: at the beginning of each bit, the level jumps. Within a bit, a level change is used to indicate logic, which indicates a logic "1" if the level jumps in the middle of the bit, and a logic "0" otherwise. By using BMC coding, the transmitting end and the receiving end can correctly transmit and receive data only by one data line, and good synchronism is kept at the transmitting end and the receiving end.
The PD protocol specifies a BMC signaling frequency of 300K, i.e., 3.33us per bit. The PD protocol allows the code to have a frequency deviation of +/-10%.
However, in practical application, the BMC signal may be interfered, and the interfered BMC signal may have a duty ratio imbalance and a baud rate imbalance, so that the rising time and the falling time of the BMC signal do not meet the system requirements, and finally the BMC signal is distorted and distorted, and communication fails.
In the method, the middle position of each bit of a first-stage digital filtering result signal can be dynamically adjusted according to the baud rate and the duty ratio of the previous bit, so that the middle position of the current bit is dynamically adjusted based on the baud rate and the duty ratio of the previous bit, the influence of interference pulses in the first-stage digital filtering result signal on second-stage digital filtering can be reduced to the greatest extent, and the reliability is effectively improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, an embodiment of the present invention provides a BMC signal receiving method, which may include the following steps:
and step 11, sequentially carrying out analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal.
In a specific implementation, the BMC signal is an analog signal. When analog filtering is performed on the BMC signal, low-pass filtering of less than 30ns may be performed, so that the BMC signal of less than 30ns passes through.
In some embodiments, after the low-pass filtering is performed on the BMC signal, a DC Offset (DC Offset) removal process may be performed on the low-pass filtered BMC signal, that is, a DC Offset in the ac signal is eliminated, so as to filter an interference signal generated by the BMC signal due to the DC Offset.
In a specific implementation, a first stage of digital filtering may be performed on the dc-offset-removed BMC signal. After the BMC signal subjected to the direct current offset removal processing is subjected to first-stage digital filtering, burr pulses within the range of 100 ns-1000 ns are filtered. After the first stage of digital filtering, the overall delay (Latency) is several bits, which can be determined according to the filter depth set by programming. For example, a 4-level depth flip-flop may be used to perform the first-level digital filtering, and the BMC signal after dc offset removal may be delayed by 1-16 programmable bits as a whole. After the first-stage digital filtering, the obtained first-stage digital filtering result signal is a digital signal.
And step 12, performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal.
If the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the first-stage digital filtering result signal, starting from the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level. i is a positive integer; and when i is larger than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
In the current USB communication standard protocol, the allowed baud rate of the BMC signal ranges from 270Kbps to 330 Kbps. Baud (Baud), the modulation rate, refers to the rate at which the effective data signal modulates the carrier, i.e., the number of times the modulation state of the carrier changes per unit time. The baud rate is a measure of the transmission rate of the symbol, which is expressed by the number of times the modulation state of the carrier changes in a unit time, and means the number of symbols transmitted in a unit time. Symbols, such as binary symbols, hexadecimal symbols, and the like. In a digital signal, a symbol is a pulse signal.
In a specific implementation, the preset middle position of the ith bit of the first-stage digital filtering result signal is not the middle position of the ith bit in an actual transmission process, but the middle position is estimated according to the baud rate of the (i-1) th bit.
In an embodiment of the present invention, performing second-stage digital filtering on the first-stage digital filtered signal to obtain a second-stage digital filtered result signal, may include: detecting the edge of the ith bit of the first-stage digital filtering result signal to obtain an edge detection result signal; and judging whether the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the ith bit of the edge detection result signal, if so, starting the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level.
In a specific implementation, the preset middle position of the ith bit of the first-stage digital filtering result signal can be determined by various methods, which are not limited herein.
In an embodiment of the present invention, a preset middle position of an ith bit of the first-stage digital filtering result signal may be determined according to a baud rate and a duty ratio of a previous bit of the first-stage digital filtering result signal.
In a particular implementation, each bit of the received first stage digital filter result signal may be counted separately. Based on the individual count results for each bit, the bit for that bit, and thus the baud rate for that bit, may be determined.
For the ith bit, whether the baud rate of the ith bit of the first-stage digital filtering result signal needs to be adjusted or not can be judged according to the bit of the ith-1 bit of the first-stage digital filtering result signal and the baud rate of the ith-1 bit of the first-stage digital filtering result signal, then the duty ratio of the previous bit of the first-stage digital filtering result signal is judged, finally the counting length of the ith bit of the first-stage digital filtering result signal is determined according to the judgment result, and the preset middle position of the ith bit of the first-stage digital filtering signal is obtained.
Typically, the duty cycle of each bit of the first stage digital filter result signal should be equal to 1. Therefore, after the baud rate of the i-1 th bit is determined, if the duty cycle of the previous bit of the first-stage digital filtering result signal is smaller than 1, it indicates that the count length of the previous bit is larger than the actual length, and at this time, the count length of the ith bit of the first-stage digital filtering result signal should be reduced. If the duty ratio of the previous bit of the first-stage digital filtering result signal is greater than 1, the counting length of the previous bit is smaller than the actual length, and at this time, the counting length of the ith bit of the first-stage digital filtering result signal is increased. If the duty ratio of the previous bit of the first-stage digital filtering result signal is equal to 1, the counting length is equal to the actual length, and at this time, the counting length of the previous bit is taken as the counting length of the ith bit.
For example, when the duty ratio of the i-1 th bit of the first-stage digital filtering result signal is smaller than 1, if the count length of the i-1 th bit is 8, the count length of the i-th bit should be smaller than 8.
In a specific implementation, when counting each bit of the first-stage digital filtering result signal, according to the determined baud rate, a preset time length required by each bit of the first-stage digital filtering signal is estimated, and then the step length of the counter is adjusted based on the preset time length, so that the counting length of each bit of the first-stage digital filtering signal is an even number of counter step lengths. For example, the preset duration is 80ns, the counter step size can be set to 10ns, and the count length corresponding to each bit of the first-stage digital filtering signal is 8 counter steps.
In a specific implementation, for each bit of the first stage digitally filtered signal, a separate count is performed, for example, in the first bit, the counter starts counting from 0, and in the second bit, the counter starts counting from 0 again. Thus, each bit corresponds to the middle of the count length, i.e., the predetermined middle of each bit of the first stage digitally filtered signal.
The method comprises the steps of determining a preset intermediate position of a current bit based on the baud rate and the duty ratio of a previous bit of a first-stage digital filtering result signal, and carrying out second-stage digital filtering on the first-stage digital filtering result signal according to the determined preset intermediate position to filter out interference pulses which do not meet the baud rate requirement, so that the obtained second-stage digital filtering result signal can meet the baud rate requirement, and BCM signal distortion caused by baud rate maladjustment and duty ratio maladjustment is avoided.
In a specific implementation, for any bit of the first-stage digital filtering result signal, the second-stage digital filtering result signal keeps low level when the preset middle position of the bit is not reached. When the preset middle position of the bit is reached, if the preset middle position just corresponds to the edge of the first-stage digital filtering result signal, the second-stage digital filtering result signal is set up, namely, the low level is converted into the high level and is kept until the bit is ended.
In a specific implementation, the determination of whether a certain time corresponds to the edge of the first-stage digital filtering result signal may be determined by performing edge detection on the first-stage digital filtering result signal. Specifically, the edge of the first-stage digital filtering result signal may be detected to obtain an edge detection result signal, and then whether a preset middle position of each bit of the first-stage digital filtering signal corresponds to an edge pulse of the edge detection result signal is determined, if yes, the second-stage digital filtering result signal is set, otherwise, the second-stage digital filtering result signal is kept at a low level.
In one embodiment, the edge detection result signal is maintained at a low level when the edge of the first-stage digital filtering result signal is not detected, and is converted from a low level to a high level when the edge of the first-stage digital filtering result signal is detected, and the edge detection result signal is represented as an edge pulse. When the preset middle position of each bit of the first-stage digital filtering signal is reached, if the preset middle position simultaneously corresponds to the edge pulse of the edge detection result signal, the second-stage digital filtering result signal is set, otherwise, the preset middle position is kept at a low level.
In practical applications, a receiving end generally receives a preamble corresponding to a frame of BMC signal first in a process of receiving the frame of BMC signal, where the preamble includes first bits of the BMC signal. When receiving the preamble, it can be determined whether the baud rate of each bit of the preamble is within the allowed baud rate range. And if the baud rate is within the allowed baud rate range, receiving a corresponding BMC signal after receiving the lead code, and otherwise, stopping receiving a subsequent BMC signal.
In practical applications, due to factors such as high impedance existing at a receiving end, the duty ratio of a first bit in the first-stage digital filtering signal is inconsistent with the duty ratios of other bits. Specifically, referring to fig. 2, it is assumed that the length of other bits of the first-stage digitally filtered signal is 1UI, but the presence of high impedance makes the actual high level duration tStartDrive when the receiving end receives the first bit of the first-stage digitally filtered signal. And tStartDrive is present such that the length of the first bit of the first stage digitally filtered signal is larger than 1UI, i.e. practically inconsistent with the bits of the other bits, i.e. the duty cycle is off-set.
In view of the above, in order to avoid that the first bit of the first-stage digitally filtered signal is filtered due to being mistaken for an interference pulse, in an embodiment of the present invention, special consideration is given to the first bit of the first-stage digitally filtered signal, so that the first bit of the first-stage digitally filtered signal can be decoded and output, and thus, data information carried by the first bit is obtained.
Specifically, a second count length corresponding to a first bit of the first-stage digitally filtered signal may be set to be greater than a first count length of other bits of the first-stage digitally filtered signal, thereby causing the second-stage digitally filtered result signal to include the first bit of the first-stage digitally filtered signal. For example, when the first count length is 8 count steps, the second count length may be set to 10 count steps.
In a specific implementation, when i is equal to 1, the preset middle position of the first bit of the first-stage digital filtering result signal may be determined according to a baud rate range (i.e., 270Kbps to 330 Kbps) allowed by the BMC signal.
In an embodiment of the present invention, the preset middle position of the first bit of the first-stage digital filtering result signal may be determined according to the maximum baud rate allowed by the BMC signal, so that the second-stage filtering result signal maximally includes the information of the first bit. For example, when the maximum baud rate allowed by the BMC signal is 330Kbps, the first bit length of the first-stage digital filtering result signal is 1/330K ≈ 3.3 us. Accordingly, the preset middle position of the first bit is 151.5 ns.
In another embodiment of the present invention, a certain clock accuracy tolerance may be added based on the allowed baud rate range of the BMC signal. For example, the tolerance of clock precision can be increased by 3% -5%, and the total error range can be expanded to 15%. At this time, the baud rate range is 270 × Kbps (1-15%) to 330(1+ 15%) Kbps.
And step 13, sampling the second-stage digital filtering result signal to obtain a sampling result signal.
In a specific implementation, it may be determined whether the preset end position of each bit of the first-stage digital filtering result signal corresponds to an edge of the first-stage digital filtering result signal, if so, the second-stage digital filtering result signal is sampled, otherwise, the second-stage digital filtering result signal is not sampled. The preset ending position of each bit of the first-stage digital filtering result signal is preset according to the baud rate range allowed by the BMC signal.
A preset middle position of each bit of the first-stage digital filtering result signal, that is, a middle position between a preset starting position and a preset ending position of each bit of the first-stage digital filtering result signal. Similar to the preset middle position of each bit of the first-stage digital filtering result signal, the preset end position of each bit of the first-stage digital filtering result signal is also determined according to the baud rate of the previous bit. In other words, after determining the baud rate of the current bit based on the baud rate of the previous bit, the preset middle position and the preset end position of the current bit are determined.
In a specific implementation, if a preset end position of an ith bit of the first-stage digital filtering result signal corresponds to an edge of the ith bit of the first-stage digital filtering result signal, sampling the ith bit of the second-stage digital filtering result signal, otherwise, not sampling the ith bit of the second-stage digital filtering result signal. The obtained sampling result signal has a certain delay relative to the second stage digital filtering result signal.
Sampling dislocation caused by the imbalance of the baud rate and the imbalance of the duty ratio of the first-stage digital filtering result signal can be avoided by setting the preset end position of each bit of the first-stage digital filtering result signal and sampling the second-stage digital filtering result signal.
And step 14, decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal.
In a specific implementation, if the level of the sampling result signal jumps in the middle of each bit of the first-stage digital filtering result signal, a logic "1" is decoded and output, otherwise, a logic "0" is decoded and output.
As can be seen from the above, the BMC signal receiving method in the embodiment of the present invention dynamically monitors the baud rate and the duty ratio, and then sets a reasonable sampling point, thereby ensuring the reliability of communication.
The following is described in detail with reference to fig. 3 and 4:
referring to fig. 3 and 4, clk is a local clock signal. bmc _ in _ cursor is a first-stage digital filtering result signal, edge _ box is an edge detection result signal, bmc _ bitwd _ cnt is a counting signal, bitone _ keep is a second-stage digital filtering result signal, rx _ bit is a sampling trigger signal, and rx _ bit _ dec is a sampling result signal.
FIG. 3 is a diagram illustrating normal waveforms of the BMC signals without interference. And detecting the edge of the first-level digital filtering result signal bmc _ in _ notch to obtain an edge detection result signal add _ box. The position of the edge detection result signal edge _ box corresponding to the edge of the first-stage digital filtering result signal bmc _ in _ notch is represented as an edge pulse.
When the edge of the first-stage digital filtering result signal bmc _ in _ marker is detected, each bit of the first-stage digital filtering result signal bmc _ in _ marker is counted, as shown by a count signal bmc _ bitwd _ cnt. Each bit of the first-stage digital filtering result signal bmc _ in _ glove corresponds to a count length of 8, and the count value is 0-7. The preset middle position of each bit of the first-stage digital filtering result signal bmc _ in _ glove, i.e. the end position of the count value 3.
The second-stage digital filtering result signal bitone _ keep is maintained at a low level until the end position of the count value 3. After the end of the count value 3, if an edge pulse of the edge detection result signal add _ both is encountered, the second-stage digital filtering result signal bitone _ keep is set up until the end of the bit.
At the end position of the counting of each bit of the first-stage digital filtering result signal bmc _ in _ glove, the sampling trigger signal rx _ sample is at a high level to trigger the sampling of the second-stage digital filtering result signal bitone _ keep.
When the sampling trigger signal rx _ bit _ sample is at a high level, if an edge pulse of the edge detection result signal add _ box is encountered, the sampling result signal rx _ bit _ dec is at a high level, otherwise, it is at a low level.
For example, at time t1, the sampling trigger signal rx _ bit is at a high level, and at this time, an edge pulse of the edge detection result signal add _ box is just encountered, and if the second-stage digital filtering result signal bitone _ keep is at a high level, the sampling result signal rx _ bit _ dec delays to output a sampling result at a high level. At time t2, the sampling trigger signal rx _ bit is at a high level, and at this time, an edge pulse of the edge detection result signal add _ box is just encountered, and if the second-stage digital filtering result signal bitone _ keep is at a low level, the sampling result signal rx _ bit _ dec delays to output a sampling result at a low level.
FIG. 4 is a waveform diagram of each signal when there is interference in the BMC signal. Referring to fig. 4, since the BMC signal has interference, the first-stage digital filtering result signal BMC _ in _ glitch has a low-level interference pulse at time t2 and a high-level interference pulse at time t 3.
When the BMC receiving method in the embodiment of the invention is applied to receive the BMC signal, the edge of the first-stage digital filtering result signal BMC _ in _ cursor is detected to obtain an edge detection result signal add _ booth. When the edge of the first-stage digital filtering result signal bmc _ in _ marker is detected, each bit of the first-stage digital filtering result signal bmc _ in _ marker is counted, as shown by a count signal bmc _ bitwd _ cnt. The preset middle position of each bit of the first-stage digital filtering result signal bmc _ in _ glove is still the end position of the count value 3.
The second-stage digital filtering result signal bitone _ keep is maintained at a low level until the end position of the count value 3. At this time, even if there is an interference pulse of a low level at time t2, the second-stage digital filtering result signal bitone _ keep is still kept at a low level, and the second-stage digital filtering result signal bitone _ keep is not affected by the interference pulse, that is, the interference pulse is filtered.
Until the end position of the count value 3, and simultaneously when encountering the edge pulse of the edge detection result signal add _ both, the second-stage digital filtering result signal bitone _ keep is set until the end of the bit.
Similarly, at the time t3, the second-stage digital filtering result signal bitone _ keep remains at the low level because no edge pulse of the edge detection result signal edge _ box is encountered. Since the time t3 is not the predetermined end position of the bit, the sampling result signal rx _ bit _ dec is also low.
Therefore, by adopting the method for receiving the BMC signal in the embodiment of the invention, even if interference exists in front and back bits, the interference can be effectively filtered, and the communication failure caused by sampling dislocation and communication baud rate imbalance caused by duty ratio imbalance is avoided.
In order to make those skilled in the art better understand and implement the present invention, the user terminal and the computer readable storage medium corresponding to the above method are described in detail below.
Referring to fig. 5, an embodiment of the present invention provides a BMC signal receiving apparatus 50, where the apparatus 50 may include: an analog filter circuit 51, a first stage digital filter circuit 52, a second stage digital filter circuit 53, a sampling circuit 54, and a decoding circuit 55. Wherein:
the analog filter circuit 51 is suitable for sequentially performing analog filtering on the received BMC signals;
the first stage digital filter circuit 52 is adapted to perform first stage digital filtering on the analog-filtered BMC signal to obtain a first stage digital filtering result signal;
the second-stage digital filtering circuit 53 is adapted to perform second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal;
the sampling circuit 54 is adapted to sample the second-stage digital filtering result signal to obtain a sampling result signal;
the decoding circuit 55 is adapted to decode the sampling result signal to obtain a decoding signal corresponding to the BMC signal;
if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level; i is a positive integer; and when i is larger than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
In an embodiment of the present invention, the second stage digital filtering circuit 53 may include: an edge detection module 531, a determination module 532, and an output module 533. Wherein:
the edge detection module 531 is adapted to detect an edge of an ith bit of the first-stage digital filtering result signal to obtain an edge detection result signal;
the judging module 532 is adapted to judge whether a preset middle position of an ith bit of the first-stage digital filtering signal corresponds to an edge pulse of the ith bit of the edge detection result signal;
the output module 533 is adapted to start the ith bit of the output second-stage digital filtering result signal when the judging module judges that the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the edge detection result signal, and otherwise, keep the ith bit at a low level.
In an embodiment of the present invention, the second stage digital filtering circuit 53 may further include: a first count storage module (not shown) and a second count storage module (not shown). Wherein:
the first count storage module is suitable for storing first count lengths corresponding to other bits except the first bit in the first-stage digital filtering signal;
the second counting storage module is suitable for storing a preset counting difference value; and the sum of the preset counting difference value and the first counting length is a second counting length corresponding to a first bit in the first-stage digital filtering signal.
In a specific implementation, the apparatus 50 may further be provided with a counter (not shown), and the counter may count bits of the first-stage digital filtering result signal according to the determined counting length of each bit. The counter can be connected with the first counting storage module and the second counting storage module, and when the first bit of the first-stage digital filtering result signal is counted, the second counting length is obtained from the second counting storage module, and the counting operation is executed. When counting other bits of the first-stage digital filtering result signal, obtaining a corresponding first counting length from the first counting storage module, and executing counting operation.
In an embodiment of the invention, a second count length corresponding to a first bit of the first-stage digitally filtered signal is greater than a first count length of other bits of the first-stage digitally filtered signal, so that the second-stage digitally filtered result signal includes the first bit of the first-stage digitally filtered signal.
In an embodiment of the present invention, when i is equal to 1, the preset middle position of the first bit of the first-stage digital filtering result signal is determined according to the maximum baud rate allowed by the BMC signal.
In an embodiment of the present invention, the sampling circuit 54 is adapted to sample the ith bit of the second-stage digital filtering result signal when the preset end position of the ith bit time of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, otherwise, not sample the ith bit of the second-stage digital filtering result signal.
The BMC signal receiving device 50 in the embodiment of the invention avoids the problem that the filtering of a complex analog circuit is not easy to adjust, and the BMC communication robustness is adjusted in a digital programmable mode. From a cost perspective, the first stage digital filter circuit 52 may be a 4-stage depth flip-flop. The counting part in the second stage digital filter circuit 53 can count by adopting a 6-bit adjustable width counter and a 2-bit baud rate preset tolerance range on hardware. The device 50 receives the single bit inversion, clears the end counter of each bit, and decodes and outputs the corresponding 0 or 1. The receiving of the noise signals can be completed within 20 integral triggers, and the Power output certainty Test (Power Delivery decision Test) of a USB protocol organization can be met without simulating and assisting actual measurement on a Field-Programmable Gate Array (FPGA).
The embodiment of the present invention further provides a USB power source, where the USB power source includes the BMC signal receiving apparatus 50.
Specifically, referring to fig. 6, the USB power source 61, as a power supply end, may perform BMC communication with a device end (i.e., a transmitting end) 62 through a configuration channel.
After the BMC signal sent by the device end 62 is received by the USB power source 61 through the configuration channel, the BMC signal receiving device 50 decodes the received BMC signal, the decoded data is transmitted to the protocol layer (PRL) and the policy management layer device (PE)63, and the protocol layer and policy management layer device 63 removes the header and the trailer of the decoded data according to the transmission protocol, so as to obtain the effective information carried in the BMC signal. The valid information carried in the BMC signal is stored in a corresponding memory 65, such as ROM, RAM, etc., via a data selection BUS MUX under the control of an MCU Core (Core) 64.
In the embodiment of the present invention, referring to fig. 7, in the BMC signal receiving device 50, after analog filtering and DC removal, the BMC signal sequentially performs first-stage digital filtering and second-stage digital filtering, and then decodes and outputs the BMC signal to the protocol layer and policy management layer device 63 of the USB power source 61.
In some embodiments, when performing the first stage digital filtering on the BMC signal, the MCU core 64 may send the depth of the first stage digital filtering circuit 52 to the first stage digital filtering circuit 52 via the data selector BUS MUX by way of digital programming to control the depth of the first stage digital filtering circuit 52. When the BMC signal is subjected to the second-stage digital filtering, the MCU core 64 may also transmit the baud rate of the second-stage digital filter circuit 53 to the second-stage digital filter circuit 53 through the data selector BUS MUX in a digital programming manner, so as to control the baud rate at which the second-stage digital filter circuit 53 filters the current bit. Therefore, the first-stage digital filter circuit 52 can perform first-stage digital filtering on the BMC signal under the control of the MCU core 64, and the second-stage digital filter circuit 53 can perform second-stage digital filtering on the BMC signal under the control of the MCU core 64.
In the embodiment of the present invention, the MCU core 64 may adaptively determine the baud rate of the current bit according to the baud rate of the previous bit, and control the second stage digital filter circuit 53 to perform decoding.
The USB power supply 61 may further include: and other processing modules, such as Analog-to-Digital conversion (ADC) circuits, Digital-to-Analog conversion (DAC) circuits, Digital processing modules (Digital Blocks), Analog processing modules (Analog Blocks), and the like. The MCU core 64 may control the other processing modules to perform other processing on the data via the data selector.
The USB power supply 61 may further include: a Direct Memory Access (DMA) controller 66. Under the control of the DMA controller 66, the USB power supply 61 can realize direct data transfer between the internal memory and the external device without the involvement of the MCU core 64.
The BMC signal receiving device 50 in the embodiment of the invention can be applied to the USB power supply 61 with a digital-analog mixed chip, so that BMC communication faults caused by deviation of a device end and a power supply end can be avoided.
The embodiment of the present invention further provides another computer-readable storage medium, where a computer instruction is stored, and when the computer instruction runs, any step of the BMC signal receiving method in the foregoing embodiments is executed, which is not described herein again.
In particular implementations, the computer-readable storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
The embodiment of the present invention further provides a USB power source, where the USB power source may include a memory and a processor, where the memory stores a computer program capable of running on the processor, and when the processor runs the computer program, the step of executing the control method of any electronic device in the foregoing embodiments is performed, which is not described again.
Each module/unit included in each apparatus and product described in the above embodiments may be a software module/unit, or may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit. For example, for each device and product applied to or integrated in a chip, each module/unit included in the device and product may be implemented by hardware such as a circuit, or at least a part of the modules/units may be implemented by a software program running on a processor integrated in the chip, and the rest of the modules/units may be implemented by hardware such as a circuit; for each device and product applied to or integrated with the chip module, each module/unit included in the device and product may be implemented in a hardware manner such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least a part of the modules/units may be implemented in a software program running on a processor integrated inside the chip module, and the remaining part of the modules/units may be implemented in a hardware manner such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program running on a processor integrated in the terminal, and the rest of the modules/units may be implemented by using hardware such as a circuit.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. A BMC signal receiving method, comprising:
sequentially carrying out analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal;
performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal;
sampling the second-stage digital filtering result signal to obtain a sampling result signal;
decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal;
if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level; i is a positive integer; and when i is larger than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
2. The BMC signal receiving method of claim 1, wherein the performing a second stage digital filtering on the first stage digitally filtered signal to obtain a second stage digital filtering result signal comprises:
detecting the edge of the ith bit of the first-stage digital filtering result signal to obtain an edge detection result signal;
and judging whether the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the ith bit of the edge detection result signal, if so, starting the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level.
3. The BMC signal receiving method of claim 2, wherein the preset middle position of the ith bit of the first-stage digital filtering result signal is determined by a method comprising: determining the baud rate of the previous bit of the first-stage digital filtering result signal according to the bit time of the previous bit of the first-stage digital filtering result signal; judging whether to adjust the baud rate of the ith bit of the first-stage digital filtering result signal or not according to the duty ratio of the previous bit of the first-stage digital filtering result signal; and determining the counting length of the ith bit of the first-stage digital filtering result signal according to the judgment result, and obtaining the preset middle position of the ith bit time of the first-stage digital filtering result signal.
4. The method for receiving a BMC signal according to claim 3, wherein the determining whether to adjust the count length of the ith bit of the first stage digital filtering result signal according to the duty ratio of the previous bit of the first stage digital filtering result signal includes:
and when the duty ratio of the previous bit of the first-stage digital filtering result signal is less than 1, reducing the counting length of the ith bit of the first-stage digital filtering result signal, otherwise, increasing the counting length of the ith bit of the first-stage digital filtering result signal.
5. The method for receiving a BMC signal according to claim 3, wherein an i-th bit of the first-stage digitally filtered signal corresponds to a middle position of a count length, which is a preset middle position of an i-th bit time of the first-stage digitally filtered signal.
6. The BMC signal receiving method of claim 3, wherein a second count length corresponding to a first bit of the first stage digital filtering result signal is greater than a first count length corresponding to other bits of the first stage digital filtering result signal, such that the second stage digital filtering result signal comprises the first bit of the first stage digital filtering signal.
7. The BMC signal receiving method of claim 1, wherein when i is equal to 1, a preset middle position of a first bit of the first stage digital filtering result signal is determined according to a baud rate allowed by the BMC signal.
8. The BMC signal receiving method of claim 7, wherein the predetermined middle position of the first bit of the first-stage digital filtering result signal is determined according to a maximum baud rate allowed by the BMC signal.
9. The BMC signal receiving method of claim 1, wherein the sampling the second stage digital filtering result signal to obtain a sampling result signal comprises:
and if the preset end position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, sampling the ith bit of the second-stage digital filtering result signal, otherwise, not sampling the ith bit of the second-stage digital filtering result signal.
10. A BMC signal receiving apparatus, comprising:
the analog filter circuit is suitable for sequentially carrying out analog filtering on the received BMC signals;
the first-stage digital filter circuit is suitable for performing first-stage digital filtering on the BMC signal after analog filtering to obtain a first-stage digital filtering result signal;
the second-stage digital filter circuit is suitable for carrying out second-stage digital filtering on the first-stage digital filter signal to obtain a second-stage digital filter result signal;
the sampling circuit is suitable for sampling the second-stage digital filtering result signal to obtain a sampling result signal;
the decoding circuit is suitable for decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal;
if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, and otherwise, keeping the ith bit at a low level; i is a positive integer; and when i is larger than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
11. The BMC signal receiving device of claim 10, wherein the second stage digital filter circuit comprises:
the edge detection module is suitable for detecting the edge of the ith bit of the first-stage digital filtering result signal to obtain an edge detection result signal;
the judging module is suitable for judging whether the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the ith bit of the edge detection result signal;
and the output module is suitable for setting the ith bit of the output second-stage digital filtering result signal when the judgment module judges that the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the edge detection result signal, and otherwise, keeping the ith bit at a low level.
12. The BMC signal receiving apparatus of claim 11, wherein the second stage digital filter circuit further comprises:
the first counting storage module is suitable for storing first counting lengths corresponding to other bits except the first bit in the first-stage digital filtering signal;
the second counting storage module is suitable for storing a preset counting difference value; the sum of the preset counting difference value and the first counting length is a second counting length corresponding to a first bit in the first-stage digital filtering signal;
and the counting module is suitable for acquiring corresponding counting lengths from the first counting storage module and the second counting storage module and executing counting operation.
13. The BMC signal receiving apparatus of claim 12, wherein the second count length corresponding to the first bit of the first stage digitally filtered signal is greater than the first count length corresponding to the other bits of the first stage digitally filtered signal, such that the second stage digitally filtered result signal includes the first bit of the first stage digitally filtered signal.
14. A USB power supply comprising the BMC signal receiving apparatus of any one of claims 10 to 13.
15. A computer-readable storage medium, on which a computer program is stored, which computer program is executable by a processor for carrying out the steps of the method according to any one of claims 1 to 9.
16. A USB power supply comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor, when executing the computer program, performs the steps of the method of any of claims 1 to 9.
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