CN204790677U - Anti-interference clock and data recovery integrated circuit design - Google Patents
Anti-interference clock and data recovery integrated circuit design Download PDFInfo
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- CN204790677U CN204790677U CN201520542222.6U CN201520542222U CN204790677U CN 204790677 U CN204790677 U CN 204790677U CN 201520542222 U CN201520542222 U CN 201520542222U CN 204790677 U CN204790677 U CN 204790677U
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- 238000011084 recovery Methods 0.000 title claims abstract description 15
- 230000000630 rising effect Effects 0.000 claims abstract description 52
- 230000001960 triggered effect Effects 0.000 claims description 64
- 230000008030 elimination Effects 0.000 abstract description 6
- 238000003379 elimination reaction Methods 0.000 abstract description 6
- 238000004891 communication Methods 0.000 abstract description 5
- 230000001360 synchronised effect Effects 0.000 abstract 1
- 238000005070 sampling Methods 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Abstract
The utility model discloses an anti-interference clock and data recovery integrated circuit design belongs to the electron field. The structure comprises a CDR circuit module used for recovering clock and data; the first-level cache module is used for performing first-level cache on data by using the rising edge and the falling edge of a clock; the second-level cache module is used for performing second-level caching on the data cached in the first level by using the rising edge and the falling edge of the clock; the combinational logic circuit module is used for carrying out logic operation on the data of the first-level cache and the data of the second-level cache and eliminating positive pulse burrs or negative pulse burrs introduced by the data of the logic operation; the third rising edge triggers the D flip-flop to sample the output recovered data from the rising edge of the clock. The utility model has the advantages that: three logic gates and six D triggers are connected to the CDR circuit module, so that synchronous wireless communication data decoding and elimination of data positive pulse burrs or negative pulse burrs are realized, the implementation is simple and convenient, and the application prospect is wide.
Description
Technical field
The utility model relates to electronic applications, particularly the jamproof clock and data recovery integrated circuit (IC) design of one.
Background technology
Due to can only transmitting serial data on radio communication (return-to-zero) channel, can not transmit clock signal, so after data receiver reception serial data, be called for short ce circuit by clockanddatarecovery circuit and realize clock and data recovery.The clock C that CDR exports
sambe 2 times of original data bits rate, be equivalent to the over-sampling clock of 2 times; Data are RZ data D
rZ, send code 1 and reverted to high level by CDR, during whole code element, only continue for some time (at least half C
samcycle), all the other times return the form of zero level.Due to the existence of intersymbol interference and various noise, cause D
rZpositive/negative pulse burr may be introduced.Therefore, to the accurate recovery of serial data be the prerequisite of correctly carrying out subsequent treatment.
Summary of the invention
In order to solve the problem of prior art, the utility model embodiment provides a kind of jamproof clock and data recovery integrated circuit (IC) design.
Described technical scheme is as follows:
A kind of jamproof clock and data recovery integrated circuit (IC) design, comprises ce circuit module, and described ce circuit module is used for recovered clock and data;
Also comprise level cache module, L2 cache module, combinational logic circuit module, the 3rd rising edge triggered D flip flop; Described level cache module carries out level cache for the rising edge and negative edge utilizing clock to data, comprises the first rising edge triggered D flip flop, the first negative edge triggered D flip flop; Described L2 cache module carries out L2 cache for the rising edge and negative edge utilizing clock to the data of level cache, comprises the second rising edge triggered D flip flop, the second negative edge triggered D flip flop; Described combinational logic circuit module is used for carrying out logical operation to the data of level cache and the data of L2 cache, and the positive pulse burr introduced of the data eliminating logical operation or negative pulse burr, comprise first or door, second or door, second level logic gate; Described 3rd rising edge triggered D flip flop is used for being sampled to export by the rising edge of clock recovering data;
Wherein, an input end incoming clock of described first rising edge triggered D flip flop, another input end access data, output terminal respectively with an input end of described second rising edge triggered D flip flop and described first or an input end of door be connected; Another input end incoming clock of described second rising edge triggered D flip flop, output terminal is connected with another input end of described first or door; Described first or the output terminal of door be connected with an input end of described second level logic gate; An input end incoming clock of described first negative edge triggered D flip flop, another input end access data, output terminal respectively with an input end of described second negative edge triggered D flip flop and described second or an input end of door be connected; Another input end incoming clock of described second negative edge triggered D flip flop, output terminal is connected with another input end of described second or door; Described second or the output terminal of door be connected with another input end of described second level logic gate; The output terminal of described second level logic gate is connected with an input end of described 3rd rising edge triggered D flip flop; Another input end incoming clock of described 3rd rising edge triggered D flip flop, output terminal exports and recovers data.
Further, described second level logic gate be or door or with door, the negative pulse burr that described or door is introduced for the data eliminating logical operation, the described positive pulse burr introduced for the data eliminating logical operation with door.
Further, also comprise clock judging module, described clock judging module is used for carrying out two divided-frequency to clock, comprises d type flip flop;
Wherein, the input end incoming clock of described d type flip flop, output terminal exports recovered clock.
The beneficial effect that the technical scheme that the utility model embodiment provides is brought is:
By connecting three logic gates and six d type flip flops in ce circuit module, composition level cache module, L2 cache module, combinational logic circuit module, 3rd rising edge triggered D flip flop, clock judging module, the rising edge of the clock utilizing ce circuit module to export and negative edge carry out level cache to the data that ce circuit module exports, L2 cache, then logical operation is carried out, finally sampled to export by the rising edge of clock and recover data, achieve and synchronously carry out wireless communication data decoding and elimination and be less than the positive pulse burr or negative pulse burr that the data in half clock period of over-sampling clock introduce, not being only radio communication in communication system provides reliable data to transmit, the reliability that equipment receiving end receives data can also be improved, be easy to implement, have broad application prospects.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is structural representation of the present utility model;
Fig. 2 is jamproof clock and data recovery integrated circuit (IC) design to the elimination sequential chart of positive pulse burr being less than half clock period of over-sampling clock;
Fig. 3 is jamproof clock and data recovery integrated circuit (IC) design to the elimination sequential chart of negative pulse burr being less than half clock period of over-sampling clock.
Wherein, the 1, first rising edge triggered D flip flop, the 2, first negative edge triggered D flip flop, the 3, second rising edge triggered D flip flop, 4, the second negative edge triggered D flip flop, the 5, the 3rd rising edge triggered D flip flop, 6, first or door, 7, second or door, 8, second level logic gate, C
sam, clock, D
rZ, data, C
rec, recovered clock, D
rec, recover data.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearly, below in conjunction with accompanying drawing, the utility model embodiment is described in further detail.
Embodiment one
As shown in Figure 1, a kind of jamproof clock and data recovery integrated circuit (IC) design, comprises ce circuit module, and described ce circuit module is used for recovered clock and data.
Also comprise level cache module, L2 cache module, combinational logic circuit module, the 3rd rising edge triggered D flip flop 5; Described level cache module is used for utilizing clock C
samrising edge and negative edge to data D
rZcarry out level cache, comprise the first rising edge triggered D flip flop 1, first negative edge triggered D flip flop 2; Described L2 cache module is used for utilizing clock C
samrising edge and negative edge L2 cache is carried out to the data of level cache, comprise the second rising edge triggered D flip flop 3, second negative edge triggered D flip flop 4; Described combinational logic circuit module is used for carrying out logical operation to the data of level cache and the data of L2 cache, and the positive pulse burr introduced of the data eliminating logical operation or negative pulse burr, comprise first or door 6, second or door 7, second level logic gate 8; Described second level logic gate 8 be or door or with door, the negative pulse burr that described or door is introduced for the data eliminating logical operation, the described positive pulse burr introduced for the data eliminating logical operation with door; Described 3rd rising edge triggered D flip flop 5 is for by clock C
samrising edge sampling export recover data D
rec.Also comprise clock judging module, described clock judging module is used for clock C
samcarry out two divided-frequency, comprise d type flip flop (not shown).
Wherein, an input end incoming clock C of described first rising edge triggered D flip flop 1
sam, another input end access data D
rZ, output terminal respectively with an input end of described second rising edge triggered D flip flop 3 and described first or an input end of door 6 be connected; Another input end incoming clock C of described second rising edge triggered D flip flop 3
sam, output terminal is connected with another input end of described first or door 6; Described first or the output terminal of door 6 be connected with an input end of described second level logic gate 8; An input end incoming clock C of described first negative edge triggered D flip flop 2
sam, another input end access data D
rZ, output terminal respectively with an input end of described second negative edge triggered D flip flop 4 and described second or an input end of door 7 be connected; Another input end incoming clock C of described second negative edge triggered D flip flop 4
sam, output terminal is connected with another input end of described second or door 7; Described second or the output terminal of door 7 be connected with another input end of described second level logic gate 8; The output terminal of described second level logic gate 8 is connected with an input end of described 3rd rising edge triggered D flip flop 5; Another input end incoming clock C of described 3rd rising edge triggered D flip flop 5
sam, output terminal exports and recovers data D
rec.The input end incoming clock C of described d type flip flop
sam, output terminal exports recovered clock C
rec.
In use, after ce circuit module recovery clock and data, output clock C
samwith data D
rZ.
An input end incoming clock C of the first rising edge triggered D flip flop 1 in level cache module
sam, another input end access data D
rZwith the first negative edge triggered D flip flop 2 one input end incoming clock C
sam, another input end access data D
rZ, utilize clock C respectively
samrising edge and negative edge to data D
rZcarry out level cache, and export level cache data D respectively by the output terminal of the first rising edge triggered D flip flop 1 and the output terminal of the first negative edge triggered D flip flop 2
11and D
12.
An input end incoming clock C of the second rising edge triggered D flip flop 3 in L2 cache module
sam, another input end access first rising edge triggered D flip flop 1 export level cache data D
11with the second negative edge triggered D flip flop 4 one input end incoming clock C
sam, another input end access first negative edge triggered D flip flop 2 export level cache data D
12, utilize clock C respectively
samrising edge and negative edge to level cache data D
11and D
12carry out L2 cache, and export L2 cache data D respectively by the output terminal of the second rising edge triggered D flip flop 3 and the output terminal of the second negative edge triggered D flip flop 4
21and D
22.
First or door 6 level cache data D that first rising edge triggered D flip flop 1 is exported
11with the L2 cache data D that the second rising edge triggered D flip flop 3 exports
21carry out logical OR operation, export first or door 6 logical operation data D
31; Second or door 7 level cache data D that first negative edge triggered D flip flop 2 is exported
12with the L2 cache data D that the second negative edge triggered D flip flop 4 exports
22carry out logical OR operation, export second or door 7 logical operation data D
32.First or door 6 logical operation data D
31with second or door 7 logical operation data D
32after input second level logic gate 8, if introducing is positive pulse burr, then select logical and, by Output rusults and clock C
saminput the 3rd rising edge triggered D flip flop 5, by clock C
samrising edge sampling export recover data D
rec, to be less than half clock period of over-sampling clock positive pulse burr elimination sequential chart as shown in Figure 2; If what introduce is negative pulse burr, then select logical OR, equally by Output rusults and clock C
saminput the 3rd rising edge triggered D flip flop 5, by clock C
samrising edge sampling export recover data D
rec, to be less than half clock period of over-sampling clock negative pulse burr elimination sequential chart as shown in Figure 3.
Clock judging module utilizes d type flip flop (not shown) to clock C
samcarry out two divided-frequency, be restored clock C
rec.
The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.
Claims (3)
1. a jamproof clock and data recovery integrated circuit (IC) design, comprises ce circuit module, and described ce circuit module is used for recovered clock and data;
It is characterized in that, also comprise level cache module, L2 cache module, combinational logic circuit module, the 3rd rising edge triggered D flip flop; Described level cache module carries out level cache for the rising edge and negative edge utilizing clock to data, comprises the first rising edge triggered D flip flop, the first negative edge triggered D flip flop; Described L2 cache module carries out L2 cache for the rising edge and negative edge utilizing clock to the data of level cache, comprises the second rising edge triggered D flip flop, the second negative edge triggered D flip flop; Described combinational logic circuit module is used for carrying out logical operation to the data of level cache and the data of L2 cache, and the positive pulse burr introduced of the data eliminating logical operation or negative pulse burr, comprise first or door, second or door, second level logic gate; Described 3rd rising edge triggered D flip flop is used for being sampled to export by the rising edge of clock recovering data;
Wherein, an input end incoming clock of described first rising edge triggered D flip flop, another input end access data, output terminal respectively with an input end of described second rising edge triggered D flip flop and described first or an input end of door be connected; Another input end incoming clock of described second rising edge triggered D flip flop, output terminal is connected with another input end of described first or door; Described first or the output terminal of door be connected with an input end of described second level logic gate; An input end incoming clock of described first negative edge triggered D flip flop, another input end access data, output terminal respectively with an input end of described second negative edge triggered D flip flop and described second or an input end of door be connected; Another input end incoming clock of described second negative edge triggered D flip flop, output terminal is connected with another input end of described second or door; Described second or the output terminal of door be connected with another input end of described second level logic gate; The output terminal of described second level logic gate is connected with an input end of described 3rd rising edge triggered D flip flop; Another input end incoming clock of described 3rd rising edge triggered D flip flop, output terminal exports and recovers data.
2. the jamproof clock and data recovery integrated circuit (IC) design of one according to claim 1, it is characterized in that, described second level logic gate be or door or with door, the negative pulse burr that described or door is introduced for the data eliminating logical operation, the described positive pulse burr introduced for the data eliminating logical operation with door.
3. the jamproof clock and data recovery integrated circuit (IC) design of one according to claim 1, is characterized in that, also comprise clock judging module, and described clock judging module is used for carrying out two divided-frequency to clock, comprises d type flip flop;
Wherein, the input end incoming clock of described d type flip flop, output terminal exports recovered clock.
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| CN201520542222.6U CN204790677U (en) | 2015-07-24 | 2015-07-24 | Anti-interference clock and data recovery integrated circuit design |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107665033A (en) * | 2017-08-28 | 2018-02-06 | 上海集成电路研发中心有限公司 | It is a kind of that there is the Digital Logical Circuits module for resetting deburring function |
| CN111477149A (en) * | 2020-04-22 | 2020-07-31 | 京东方科技集团股份有限公司 | Data output circuit, data output method and display device |
-
2015
- 2015-07-24 CN CN201520542222.6U patent/CN204790677U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107665033A (en) * | 2017-08-28 | 2018-02-06 | 上海集成电路研发中心有限公司 | It is a kind of that there is the Digital Logical Circuits module for resetting deburring function |
| CN107665033B (en) * | 2017-08-28 | 2020-06-09 | 上海集成电路研发中心有限公司 | Digital logic circuit module with reset deburring function |
| CN111477149A (en) * | 2020-04-22 | 2020-07-31 | 京东方科技集团股份有限公司 | Data output circuit, data output method and display device |
| CN111477149B (en) * | 2020-04-22 | 2023-06-20 | 京东方科技集团股份有限公司 | Data output circuit, data output method and display device |
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