CN113615088A - Clock domain crossing synchronization circuit and method - Google Patents

Clock domain crossing synchronization circuit and method Download PDF

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Publication number
CN113615088A
CN113615088A CN201980094534.6A CN201980094534A CN113615088A CN 113615088 A CN113615088 A CN 113615088A CN 201980094534 A CN201980094534 A CN 201980094534A CN 113615088 A CN113615088 A CN 113615088A
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clock
signal
read
sampling
write
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CN113615088B (en
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白玉晶
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Synchronisation In Digital Transmission Systems (AREA)
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Abstract

The embodiment of the application discloses a clock domain crossing synchronization circuit, which comprises a clock domain channel circuit, a write address generating circuit, a read address generating circuit and a data cache circuit, wherein the write address generating circuit is used for obtaining a write address according to a write enable signal, the write address is used for controlling the data cache circuit to receive input data, and the input data is in a write clock domain; the clock domain channel circuit is used for sampling the write enable signal to obtain a plurality of sampling results, selecting one sampling result from the plurality of sampling results as a read enable signal according to a clock phase difference, wherein the clock phase difference is the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain; the read address generating circuit is used for obtaining a read address according to the read enable signal, the read address is used for controlling the data cache circuit to generate output data, and the output data is in a read clock domain; the data buffer circuit is used for buffering input data and generating output data according to the write address and the read address.

Description

Clock domain crossing synchronization circuit and method Technical Field
The present application relates to the field of circuits, and in particular, to a clock domain crossing synchronization circuit and a related method thereof.
Background
A system-on-chip (SOC) refers to a complete system integrated on a single chip, and as the functions carried on the chip are more and more, more and more clocks are also provided inside the chip, and the operating frequencies of the clocks are different, which results in that a plurality of clock domains are provided inside the chip, and when the plurality of clock domains communicate with each other, synchronization of the clock domains is required to complete data interaction across the clock domains, and an asynchronous circuit processing technology can complete the process.
A typical asynchronous circuit processing technique is the asynchronous first-in-first-out (FIFO) technique, and referring to fig. 1, first, the write address generation logic 101 in the write clock domain generates a binary write pointer to write data into the FIFO memory circuit 104, and the read address generation logic 103 in the read clock domain generates a binary read pointer to read data from the FIFO memory circuit 104, and for each read or write operation, the corresponding pointer is incremented to point to the next memory address. When the full/empty flag generation logic circuit 102 generates a read empty flag, no read operation is performed but a write operation is possible, and when the full/empty flag generation logic circuit 102 generates a write full flag, no write operation is performed but a read operation is possible. In the process, because the register registers data and needs to ensure the establishing time and the holding time of the data, the establishing time refers to that before the rising edge of the clock signal comes, the data needs to be input into the register in advance, the holding time refers to that after the rising edge comes, the data needs to be kept unchanged, the register needs to wait for one-beat processing to reach one clock period, then the register is used for executing the two-beat processing, or when the two-time multiprocessing is executed by utilizing a plurality of registers, the delay of two or more clock cycles is correspondingly generated, and the process of synchronizing the write pointer from the write clock domain to the read clock domain needs the delay of at least two clock cycles. Similarly, the generation of the write full flag requires synchronizing the read pointer of the read clock domain to the write clock domain, and the synchronization process requires the register to perform two-beat or multi-beat processing, and also has a delay of at least two clock cycles.
It can be seen that the write pointer of the write clock domain is synchronized to the read clock domain to obtain a read empty signal, which will generate a delay of at least two clock cycles, and the read pointer of the same read clock domain is synchronized to the write clock domain to obtain a write full signal, which will also generate a delay of at least two clock cycles. The full-write identifier controls the increase of the write pointer, the empty-read identifier controls the increase of the read pointer, and the read-write pointer controls the write and read of data, so that the data of the write clock domain is controlled to be synchronized to the read clock domain, and the synchronization of the data between the two clock domains also has the delay of at least two clock periods. Due to the above factors, the asynchronous FIFO shown in fig. 1 has a large delay in performing clock domain crossing processing, and thus the efficiency of data clock domain crossing processing is reduced.
Disclosure of Invention
A first aspect of the present disclosure provides a clock domain crossing synchronization circuit, which can synchronize input data from a write clock domain to a read clock domain, and includes a clock domain channel circuit, a write address generation circuit, a read address generation circuit, and a data cache circuit; the write address generating circuit can obtain a write address according to the write enable signal under the drive of the write clock signal, the write address can control the data cache circuit to receive input data, and the input data is data of a write clock domain; the two input ends of the clock domain channel circuit respectively input a write enable signal and a clock phase difference, the clock phase difference refers to the phase difference between a write clock signal in a write clock domain and a read clock signal in a read clock domain, the clock domain channel circuit can sample the write enable signal to obtain a sampling signal set, and the clock domain channel circuit selects a sampling signal from the sampling signal set as the read enable signal according to the clock phase difference; the read address generating circuit can obtain a read address according to the read enable signal under the drive of the read clock signal, the read address can control the data buffer circuit to generate output data, and the output data is in a read clock domain, so that the cross-clock domain synchronizing circuit completes the process of synchronizing the input data from the write clock domain to the read clock domain. The data cache circuit receives input data according to the write address and then caches the input data, and then the data cache circuit generates output data according to the read address.
The embodiment of the application has the following advantages: the write address generating circuit obtains a write address according to the write enable signal, the write address is used for controlling the data cache circuit to receive data, the data cache circuit caches the input data after receiving the input data, and therefore the process of writing the data into the data cache circuit is completed. The clock domain channel circuit can sample the write enable signal to obtain a plurality of sampling results, part or all of the obtained plurality of sampling results are delayed within two clock cycles relative to the write enable signal, a clock phase difference exists between the write clock signal of the write clock domain and the read clock signal of the read clock domain, one read enable signal is selected from the plurality of sampling results according to the clock phase difference, and the delay of the selected read enable signal and the selected write enable signal can be controlled within two clock cycles. Then, the read address generating circuit can obtain a read address according to the read enable signal, and the read address is used for controlling the data cache circuit to generate output data, so that the data reading process is completed.
In an optional implementation manner of the present application, the clock domain channel circuit specifically includes a plurality of flip-flops, where the plurality of flip-flops may respectively sample the write enable signal at a rising edge and a falling edge of the read clock signal to obtain a sampling signal set, where the sampling signal set includes at least one sampling signal, and the clock domain channel circuit further includes a multi-path signal selector, where the multi-path signal selector may select a target mapping relationship from a preset mapping relationship between a clock phase difference and the write enable signal according to the clock phase difference, and then determine the sampling signal from the sampling signal set according to the target mapping relationship, and use the determined sampling signal as the read enable signal. In this embodiment, a plurality of flip-flop groups may sample to obtain a sampling signal set, and a mapping relationship between a clock phase difference and a read enable signal is preset, so that a read enable signal determined by a change in the clock phase difference also changes, and thus, a corresponding sampling signal may be selected from the sampling signal set as the read enable signal under conditions of different clock phase differences, clock delays of the read enable signal and the write enable signal obtained in this way may be controlled to be two clock cycles, and clock delays of the read enable signal and the write enable signal obtained at the same time may also ensure sufficient time to synchronize input data from a write clock domain to a read clock domain.
In an optional implementation manner of the present application, the clock domain crossing synchronization circuit further includes a phase detector; the phase discriminator can determine the clock phase difference of the received write clock signal and the received read clock signal according to the received write clock signal and the received read clock signal; the phase discriminator can also generate a write enable signal according to the write clock signal, and the write enable signal is valid only when the clock phase difference is in a stable state, otherwise, the write enable signal is invalid. The phase detector outputs a clock phase difference and a write enable signal to the clock domain channel circuit. In this embodiment, the phase detector may generate the clock phase difference and the write enable signal, so that the scheme structure is more complete, and the scheme implementation is facilitated.
In an optional implementation of the present application, the clock domain channel circuit includes a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; the first trigger can sample the write enable signal to obtain a first sampling signal by the falling edge of the read clock signal after receiving the write enable signal generated by the phase discriminator, and the second trigger can sample the first sampling signal by the rising edge of the read clock signal to obtain a second sampling signal; the third trigger is used for sampling the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal after receiving the write enable signal generated by the phase discriminator; the fourth flip-flop may sample the third sampling signal at a rising edge of the read clock signal to obtain a fourth sampling signal, and the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal all belong to a sampling signal set. In the embodiment, a flip-flop is used for sampling a write enable signal to obtain a sampling signal set, the sampling signal in the sampling signal set can be used as a read enable signal, and the flip-flop can sample the signal at the rising edge and the falling edge of the clock signal, so that the read enable signal obtained from the write enable signal can be controlled within two clock cycles, the corresponding data is synchronized from a write clock domain to a read clock domain and can also be controlled within two clock cycles, and the delay of data synchronization is reduced compared with the prior art.
In an optional implementation manner of the present application, the clock domain channel circuit further includes a multiplexer, and two input terminals of the multiplexer respectively input the sampling signal set and the clock phase difference and output the read enable signal. The multi-path signal selector is used for selecting a second sampling signal from the sampling signal set as a read enable signal under the condition that the value range of the clock phase difference is [0T,1/4T ], wherein T is the clock period of a write clock domain or the clock period of a read clock domain as the clock period of the write clock can be the same as the clock period of the read clock domain; or, a multiplexer for selecting the second sampling signal or the fourth sampling signal as the read enable signal from the sampling signal set when the clock phase difference is [1/4T,1/2T), where the clock period of the second sampling signal and the clock period of the fourth sampling signal delayed with respect to the write enable signal are the same, and selecting either the second sampling signal or the fourth sampling signal; or, the multi-path signal selector is used for selecting a fourth sampling signal from the sampling signal set as a read enable signal under the condition that the clock phase difference is [1/2T,3/4T ]; or, the multi-path signal selector is configured to select the second sampling signal or the third sampling signal from the sampling signal set as the read enable signal when the value of the clock phase difference is greater than or equal to 3/4 clock cycles T, where the clock cycles delayed by the second sampling signal and the third sampling signal with respect to the write enable signal are the same, and the second sampling signal or the third sampling signal may be selected. In this embodiment, a specific manner of selecting the read enable signal under four clock phase differences is introduced, which covers all possible clock phase differences, and is flexibly implemented by using an application scheme, the clock delay of the read enable signal and the write enable signal obtained by selection can be controlled to be two clock cycles, and meanwhile, the clock delay of the read enable signal and the write enable signal obtained by selection can also ensure sufficient time for synchronizing the input data from the write clock domain to the read clock domain.
In an optional embodiment of the present application, the clock domain crossing synchronization circuit further includes a write clock domain phase-locked loop and a read clock domain phase-locked loop, where the write clock domain phase-locked loop and the read clock domain phase-locked loop are connected to a same clock source; the write clock domain phase-locked loop can obtain a write clock signal according to the clock source signal, and the write clock signal is in a write clock domain; the read clock domain phase-locked loop can obtain a read clock signal according to the clock source signal, and the read clock signal is in a read clock domain. In this embodiment, the write clock domain phase-locked loop and the read clock domain phase-locked loop are connected to the same clock source, so as to ensure that the clock of the write clock domain and the clock of the read clock domain are the same source clock, and it can be ensured that the two clocks have no frequency offset, so that the obtained frequency of the write clock signal and the read clock signal is equal to each other or the frequency division ratio of the obtained write clock signal and the read clock signal is an integral multiple, and the phase difference between the two clock signals is random.
In an optional implementation manner of the present application, the data buffer circuit includes a plurality of flip-flop groups, an input multiplexer, and an output multiplexer; the input data selector comprises a plurality of output ports which are connected with a plurality of input ends of a plurality of trigger groups in a one-to-one correspondence mode, and the output multi-path data selector comprises a plurality of input ports which are connected with a plurality of output ends of a plurality of trigger groups in a one-to-one correspondence mode; the input multi-path data selector is used for outputting cache data from a certain output port according to a write address after acquiring input data, and obtaining multi-path cache data from a plurality of output ports of the input multi-path data selector by continuously changing the write address; the plurality of trigger groups are used for receiving the multi-path cache data under the drive of the write clock signal and respectively caching the multi-path cache data output from the output ports of the plurality of input multi-path data selectors in different trigger groups; and the output multi-path data selector receives the multi-path cache data output by the plurality of trigger groups, selects one path of cache data from the multi-path cache data as output data to be output according to read addresses, and the read addresses are different, and the selected output data are different. In this embodiment, since the read enable signal is changed along with the clock phase difference, the read enable signal can obtain the read address, and thus the read address is different under different clock phase differences, and the read address is used as the read address carrying address information, so that there are many possible situations of the read address, then the application obtains the multi-path cache data by inputting the multi-path data selector on the data synchronization, the multi-path cache data is cached in different flip-flop groups of the plurality of flip-flop groups, and the cache data corresponding to the flip-flop groups in the plurality of flip-flop groups can be selected as the output data when the read address is changed. Therefore, the scheme of the application can meet the requirement of data synchronization under different clock phase difference conditions.
In an optional implementation manner of the present application, the clock domain crossing synchronization circuit further includes a fifth D flip-flop; and the fifth D flip-flop is used for receiving the output data selected by the output multi-path data selector, buffering and outputting the output data under the drive of the read clock signal. In this embodiment, the output data selected by the output multiplexer is buffered and output by using the fifth D flip-flop, and the fifth D flip-flop can prevent the influence of external interference on the correctness of data transmission in the data transmission process.
A second aspect of the present application provides a cross-clock domain synchronization method, including: obtaining a write address according to a write enable signal, wherein the write address carries address information, and can receive input data according to the control of the write address and buffer the input data so as to complete the data write process, the input data is in a write clock domain, meanwhile, the write enable signal can be sampled so as to obtain a plurality of sampling results, and one sampling result is selected from the plurality of sampling results as a read enable signal according to a clock phase difference, wherein the clock phase difference is the phase difference between a write clock signal in the write clock domain and a read clock signal in the read clock domain; and obtaining a read address according to the read enable signal, and outputting the cached input data according to the control of the read address so as to generate output data to finish the reading process of the data, wherein the output data is in a read clock domain.
The embodiment has the following advantages: and obtaining a write address according to the write enable signal, and receiving and buffering input data according to the control of the write address so as to complete the data writing process. The method comprises the steps of obtaining a plurality of sampling results by sampling a write enable signal, wherein partial or all of the obtained plurality of sampling results have a delay of two clock cycles relative to the write enable signal, secondly, a clock phase difference exists between a write clock signal of a write clock domain and a read clock signal of a read clock domain, selecting one read enable signal from the plurality of sampling results according to the clock phase difference, and the delay of the selected read enable signal and the selected write enable signal can be controlled within the two clock cycles. And then, a read address is obtained according to the read enable signal, the cached input data is output according to the control of the read address to generate output data, and the data reading process is completed.
In an optional implementation manner of the present application, the sampling the write enable signal to obtain a plurality of sampling results includes: the write enable signal is sampled at the rising edge of the read clock signal, while the write enable signal is sampled at the falling edge of the read clock signal, resulting in a plurality of sampling results. In this embodiment, compared to the prior art that a register is used to perform write pointer or read pointer synchronization, and the register needs to guarantee the setup time and the hold time of data, at least two clock cycles need to be waited, in this embodiment, both the rising edge and the falling edge of the read clock signal may sample the signal, the sampled signal may be controlled within two clock cycles, and the corresponding data is synchronized from the write clock domain to the read clock domain and may also be controlled within two clock cycles, which reduces the delay of data synchronization compared to the prior art.
In an optional implementation manner of the present application, the sampling the write enable signal at a rising edge and a falling edge of the read clock signal respectively to obtain a plurality of sampling results specifically includes: sampling the write enable signal at the falling edge of the read clock signal to obtain a first sampling signal; sampling the first sampling signal at the rising edge of the read clock signal to obtain a second sampling signal; sampling the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal; the third sampling signal is sampled at a rising edge of the read clock signal, so that a fourth sampling signal can be obtained, and the plurality of sampling results are specifically the obtained first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal. In this embodiment, compared to the prior art that a register is used to perform write pointer or read pointer synchronization, and the register needs to guarantee the setup time and the hold time of data, at least two clock cycles need to be waited, in this embodiment, both the rising edge and the falling edge of the read clock signal may sample the signal, the sampled signal may be controlled within two clock cycles, and the corresponding data is synchronized from the write clock domain to the read clock domain and may also be controlled within two clock cycles, which reduces the delay of data synchronization compared to the prior art.
In an alternative embodiment of the present application, selecting one of the plurality of sampling results as the read enable signal according to the clock phase difference includes: under the condition that the value range of the clock phase difference is [0T,1/4T), selecting a second sampling signal from a plurality of sampling results as a read enable signal, wherein, as the clock signal of the write clock domain and the clock signal of the read clock domain are generated by the same clock source, the clock period of the write clock domain or the clock period of the read clock domain are the same, and T can be the clock period of the write clock domain or the clock period of the read clock domain; or, when the value range of the clock phase difference is [1/4T,1/2T), selecting the second sampling signal or the fourth sampling signal from the plurality of sampling results as the read enable signal; or, under the condition that the value range of the clock phase difference is [1/2T,3/4T), selecting a fourth sampling signal from a plurality of sampling results as a read enable signal; or, in the case that the value of the clock phase difference is greater than or equal to 3/4 clock cycles T, selecting the second sampling signal or the third sampling signal from the plurality of sampling results as the read enable signal. In this embodiment, a specific manner of selecting the read enable signal under four clock phase differences is introduced, which covers all possible clock phase differences, and is flexibly implemented by using an application scheme, the clock delay of the read enable signal and the write enable signal obtained by selection can be controlled to be two clock cycles, and meanwhile, the clock delay of the read enable signal and the write enable signal obtained by selection can also ensure sufficient time for synchronizing the input data from the write clock domain to the read clock domain.
In an optional embodiment of the present application, the method further comprises: determining a clock phase difference between the two clock signals according to the write clock signal and the read clock signal of the read clock domain; and generating a write enable signal according to the write clock signal, wherein the write enable signal is valid when a clock phase difference between the write clock signal and the read clock signal is in a stable state, and the write enable signal is invalid when the clock phase difference between the write clock signal and the read clock signal is not in the stable state. In this embodiment, a clock phase difference and a write enable signal obtaining manner may be introduced, where the write enable signal may be used in the data synchronization process of this application, and the write enable signal is valid only when the clock phase difference is stable, so as to avoid data synchronization errors when the clock phase difference is unstable.
A third aspect of the present application provides a chip including the clock domain crossing synchronization circuit according to the first aspect of the present application and any implementation manner thereof.
The embodiment of the application has the following advantages: the write address generating circuit obtains a write address according to the write enable signal, the write address is used for controlling the data cache circuit to receive data, the data cache circuit caches the input data after receiving the input data, and therefore the process of writing the data into the data cache circuit is completed. The clock domain channel circuit can sample the write enable signal to obtain a plurality of sampling results, part or all of the obtained plurality of sampling results are delayed within two clock cycles relative to the write enable signal, a clock phase difference exists between the write clock signal of the write clock domain and the read clock signal of the read clock domain, one read enable signal is selected from the plurality of sampling results according to the clock phase difference, and the delay of the selected read enable signal and the selected write enable signal can be controlled within two clock cycles. Then, the read address generating circuit can obtain a read address according to the read enable signal, and the read address is used for controlling the data cache circuit to generate output data, so that the data reading process is completed.
Drawings
FIG. 1 is a diagram of a conventional asynchronous FIFO;
FIG. 2 is a block diagram of a cross-clock domain synchronization circuit according to the present application;
FIG. 3 is a block diagram of a clock domain channel circuit according to the present application;
FIG. 4(a) is a phase relationship of the read/write clock domains of the present application;
FIG. 4(b) is another phase relationship of the read/write clock domains of the present application;
FIG. 4(c) is another phase relationship of the read/write clock domains of the present application;
FIG. 4(d) is another phase relationship of the read/write clock domains of the present application;
FIG. 5(a) is a signal sampling result of the present application;
FIG. 5(b) is another signal sampling result of the present application;
FIG. 5(c) is another signal sampling result of the present application;
fig. 5(d) shows another signal sampling result of the present application.
Detailed Description
The present application provides a clock domain crossing synchronization circuit, which may be applied to a field-programmable gate array (FPGA), an Application Specific Integrated Circuit (ASIC), or other devices, and is not limited herein.
Referring to fig. 2, the clock domain crossing synchronization circuit of the present application includes a write address generation circuit 01, a read address generation circuit 02, and a data buffer circuit, where the data buffer circuit includes a plurality of flip-flop sets 05, an input multiplexer 06 (MUX), and an output multiplexer 07, and the clock domain crossing synchronization circuit further includes a fifth D flip-flop 08, a phase detector 03, a clock domain channel circuit 04, a write clock domain phase locked loop 09 (PLL), and a read clock domain phase locked loop 010.
Firstly, the write clock domain phase-locked loop 09 can generate a write clock signal of a write clock domain, the read clock domain phase-locked loop 010 can generate a read clock signal of a read clock domain, and an input end of the write clock domain phase-locked loop 09 and an input end of the read clock domain phase-locked loop 010 are connected with the same clock source to ensure that a clock of the write clock domain and a clock of the read clock domain are homologous clocks.
Write address generation circuit 01: the write pointer may be continuously generated when the write enable signal is active, driven by a write clock signal of the write clock domain, and the write address may be used as a write address, wherein the write enable signal may be generated by the phase detector 03. One input port of the write address generating circuit 01 is connected with an output port of the write clock domain phase-locked loop 09 and can receive a write clock signal, the other input port of the write address generating circuit 01 is connected with a first output port of the phase discriminator 03 and can receive a write enable signal, and the output port of the write address generating circuit 01 is connected with an input port of the input multiplexer 06 and can output a write address.
The data buffer circuit comprises an input multi-path data selector 06, a plurality of trigger groups 05 and an output multi-path data selector 07, the data buffer circuit can receive input data according to a write address and then buffer the input data, the data buffer circuit can also generate output data according to a read address, and the specific process is as follows:
the write address is input to the input multiplexer 06, and after the input multiplexer 06 obtains the input data, the buffer data may be output from a certain output port of the input multiplexer 06 according to address information indicated by the write address, so that the buffer data is written into a certain flip-flop group of the plurality of flip-flop groups 05, and the address information indicated by the write address may indicate that the buffer data is written into a specific flip-flop group of the plurality of flip-flop groups 05, where the certain flip-flop group corresponds to the certain output port. If the address information indicated by the write address is variable, the input multiplexer 06 may output the buffered data from the plurality of ports of the input multiplexer 06, respectively, according to the indication of the write address, and the buffered data output from the plurality of ports respectively and correspondingly enter the plurality of flip-flop groups 05. Two data ends of the input multi-path data selector 06 respectively receive input data and a write address generated by the write address generating circuit 01, a plurality of input ports of a plurality of flip-flop groups 05 are connected with a plurality of output ports of the input data multi-path selector 06 in a one-to-one correspondence manner and can receive cache data, and a plurality of output ports of the plurality of flip-flop groups 05 are connected with a plurality of input ports of the output multi-path data selector 07 in a one-to-one correspondence manner and can output the cache data.
Further, regarding the plurality of flip-flop groups 05, fig. 2 illustrates 4D flip-flop groups as an example, the number of D flip-flops in each flip-flop group is determined by the bit width of the input data, the trigger input ports of the four D flip-flop groups are connected to the write clock signal, and the four ways of cache data processed by the input multi-way data selector 06 are respectively input to the four D flip-flop groups under the drive of the write clock signal.
The multiple flip-flop groups 05 buffer the multi-path cache data, then output the multi-path cache data to the output multi-path data selector 07, and the output multi-path data selector 07 may select one path of cache data from the multi-path cache data as output data to be output according to an indication of a read pointer, where the specific read pointer may be used as a read address, the read address carries address information, the address information indicated by the read address may indicate the output multi-path data selector 07 to output cache data acquired from a specific D flip-flop group of the multiple flip-flop groups 05, and the read addresses are different, and the output multi-path data selector 07 selects different output cache data. One input port of the output multiplexer 07 is connected to the output ports of the plurality of flip-flop groups 05 and can receive the buffer data, and the other input port of the output multiplexer 07 is connected to the output port of the read address generating circuit 02 and can receive the read address.
The output data generated by the output multiplexer 07 is input to the fifth D flip-flop 08, and under the drive of the read clock signal, the fifth D flip-flop 08 may buffer and output the output data generated by the data buffer circuit, and the fifth D flip-flop 08 may prevent the influence of external interference on the correctness of data transmission during the data transmission process.
The phase detector 03 (PD) can calculate a clock phase difference between a write clock signal of a write clock domain and a read clock signal of a read clock domain, and after the write clock domain and the read clock domain are stable, the phase detector 03 enters a working state, and after a plurality of clock cycles, the phase detector 03 generates a stable clock phase difference and outputs the stable clock phase difference to the clock domain channel circuit 04. Meanwhile, the phase discriminator 03 can process a write clock signal of a write clock domain to obtain a write enable signal, and outputs the write enable signal to the write address generating circuit 01 and the clock domain channel circuit 04, the write enable signal serves as a state indication that the phase discriminator 03 stably outputs a clock phase difference, the write enable signal is valid when the clock phase difference is in a stable state, and otherwise the write enable signal is invalid. One input end of the phase detector 03 is connected to the write clock domain phase-locked loop 09 so as to receive a write clock signal, the other input end of the phase detector 03 is connected to the read-while-write clock domain phase-locked loop 010 so as to receive a read clock signal, a first output port of the phase detector 03 is connected to the other input port of the write address generating circuit 01 and the first input port of the clock domain channel circuit 04, a write enable signal can be output, and a second output port of the phase detector 03 is connected to the second input port of the clock domain channel circuit 04, so that a clock phase difference can be output.
Clock domain channel circuit 04 circuit: the clock domain channel circuit 04 may synchronize the write enable from the write clock domain to the read clock domain according to the four states of the clock phase difference to obtain a read enable signal, and then the read enable signal is output to the read address generating circuit 02, and the read address generating circuit 02 may continuously generate the read pointer as the read address to be output to the multiplexer 07 when the read enable signal is valid under the driving of the read clock signal of the read clock domain. An output port of the clock domain channel circuit 04 is connected to one input port of the read address generating circuit 02 and can output a read enable signal, another input port of the read address generating circuit 02 is connected to an output port of the read clock domain phase-locked loop 010 and can receive a read clock signal, and an output port of the read address generating circuit 02 is connected to another input port of the output multiplexer 07 and can output a read address.
Based on the above structure, the write address generating circuit 01 generates a write address to write data into the data buffer circuit, the clock domain channel circuit 04 can obtain a read enable signal according to the write enable signal and the clock phase difference, so as to synchronize the write enable signal from the write clock domain to the read clock domain, and the read address generating circuit 02 obtains a read address according to the read enable signal to read data from the data buffer circuit, so as to synchronize the input data from the write clock domain to the read clock domain.
Meanwhile, because the read enable signal is changed along with the clock phase difference, the read enable signal can obtain a read pointer, so that the read pointer is different under different clock phase difference conditions, the read address is changed, and the output data selected by the output multi-path data selector 07 is also changed, so that the scheme of the application can meet the requirement of data synchronization under different clock phase difference conditions by setting four paths of cache data.
Based on the function of the clock domain channel circuit 04, the generation process of the read address is described in detail as follows:
fig. 3 shows a specific structure of a clock domain channel circuit 04 of the present application, where the clock domain channel circuit 04 includes a first flip-flop 041, a second flip-flop 042, a third flip-flop 043, a fourth flip-flop 044, and a multi-way signal selector 045, a first output port of the phase detector 03 is specifically connected to an input port of the first flip-flop 041, an output port of the first flip-flop 041 is connected to an input port of the second flip-flop 042, a first output port of the phase detector 03 is also specifically connected to an input port of the third flip-flop 043, an output port of the third flip-flop 043 is connected to an input port of the fourth flip-flop 044, an output port of the first flip-flop 041, an output port of the second flip-flop 042, an output port of the third flip-flop 043, and an output port of the fourth flip-flop 044 are connected to another input port of the multi-way data selector, an output port of the multi-way signal selector 045 is connected to an input port of the read address generation circuit 02, referring to fig. 3, taking an example that a write clock domain and a read clock domain are homologous common-frequency asynchronous clocks, frequencies of a write clock signal and a read clock signal are the same, and a clock phase difference is random, a specific process of synchronizing a write enable signal from the write clock domain to the read clock domain by a clock domain channel circuit 04 of the present application is as follows:
as described above, the phase detector 03 generates a write enable signal, the write enable signal enters the write address generating circuit 01, and the write enable signal also enters the clock domain channel circuit 04, specifically:
the write enable signal enters the first flip-flop 041, the read clock signal is used as a sampling pulse, the first flip-flop 041 samples the write enable signal at the falling edge of the read clock signal to obtain a first sampling signal, and then, the first sampling signal enters the second flip-flop 042, also reading the clock signal as a sampling pulse, the first sampling signal is sampled at the rising edge of the read clock signal to obtain a second sampling signal, the write enable signal of the write clock domain also enters the third flip-flop 043, the read clock signal is used as a sampling pulse, the third flip-flop 043 samples the write enable signal at the falling edge of the read clock signal to obtain a third sampling signal, and then, the third sample signal enters a fourth flip-flop 044, also reading the clock signal as a sample pulse, and sampling the third sampling signal at the rising edge of the read clock signal to obtain a fourth sampling signal. The first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal belong to a sampling signal set, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal are respectively output to a multi-path signal selector 045, a clock phase difference obtained by phase discrimination of the phase discriminator 03 is also input to the multi-path signal selector 045, the multi-path signal selector 045 selects one path of sampling signal as a write enable signal to be output to a read address generating circuit 02 so as to generate a read address according to the clock phase difference obtained by the phase discrimination of the phase discriminator 03.
In the embodiment, a flip-flop is used for sampling a write enable signal to obtain a sampling signal set, a sampling signal in the sampling signal set can be used as a read enable signal, and the flip-flop can sample the signal on both the rising edge and the falling edge of the clock signal, so that the sampling signal obtained by the write enable signal to obtain all or part of the sampling signal set can be controlled in two clock cycles, the corresponding data is synchronized from a write clock domain to a read clock domain and can also be controlled in two clock cycles, and the delay of data synchronization is reduced compared with the prior art.
The phase difference of the clock of the phase discriminator 03 has four possible situations, the read enable signal obtained by selection also has four possible situations, the general idea of selection is to ensure that the write enable signal does not have a metastable state, and the following four situations are explained:
first, the clock phase difference refers to the phase difference between the write clock domain write clock signal and the read clock domain read clock signal. The application presets the mapping relation between the clock phase difference and the read enable signal, the clock phase difference is different, the read enable signal is different, and the method comprises the following specific steps:
firstly, the phase difference of the clock obtained by phase discrimination of the phase discriminator 03 is as follows: the clock skew belongs to [0T,1/4T), T is the clock period of the write clock domain, as shown in fig. 4(a), taking the clock skew between the write clock signal and the read clock signal as 1/8T as an example, corresponding to the clock skew of fig. 4(a), as shown in fig. 5(a), the write enable signal is sampled by the read clock signal according to the manner described above, the sampled third sampling signal may have a metastable state, the fourth sampling signal may also have a metastable state, but the first sampling signal and the second sampling signal may not have a metastable state, in order to ensure a certain data synchronization delay, thereby ensuring sufficient time to read data, but the data synchronization delay may not be too large, generally within 2 clock periods, the multi-path signal selector 045 selects the second sampling signal as the read enable signal and generates the read address, the read address is about 1.25 clock cycles later than the write address, and the data synchronization delay from the read clock domain to the write clock domain is about 1.25 clock cycles.
Secondly, the phase difference of the clock obtained by phase discrimination of the phase discriminator 03 is as follows: the clock phase difference between the write clock domain and the read clock domain belongs to [1/4T,1/2T), T is the clock period of the write clock domain, as shown in fig. 4(b), taking the clock phase difference between the write clock signal and the read clock signal as 3/8T as an example, corresponding to the clock phase difference of fig. 4(b), as shown in fig. 5(b), the read clock signal is used to sample the write enable signal in the manner described above, the first sampled signal, the second sampled signal, the third sampled signal and the fourth sampled signal obtained by sampling do not have a metastable state, in order to ensure a certain data synchronization delay, thereby ensuring that there is enough time to read data, but the data synchronization delay cannot be too large, generally within 2 clock periods, the multi-path signal selector 045 selects the second sampled signal or the fourth sampled signal as the read enable signal and generates the read address, where the clock cycles of the second and fourth sampling signals delayed with respect to the write enable signal are the same and the read address is about 1.5 clock cycles later than the write address, then the data synchronization delay from the read clock domain to the write clock domain is about 1.5 clock cycles.
Thirdly, the phase difference of the clock obtained by phase discrimination of the phase discriminator 03 is as follows: the clock phase difference between the write clock domain and the read clock domain belongs to [1/2T,3/4T), T is the clock period of the write clock domain, as shown in fig. 4(c), taking the clock phase difference between the write clock signal and the read clock signal as 5/8T as an example, corresponding to the clock phase difference of fig. 4(c), as shown in fig. 5(c), the read clock signal is used to sample the write enable signal according to the above-described manner, the first sampled signal and the second sampled signal obtained by sampling are metastable, the third sampled signal and the fourth sampled signal are not metastable, in order to ensure a certain data synchronization delay, thereby ensuring sufficient time to read data, but the data synchronization delay cannot be too large, generally within 2 clock periods, the multipath signal selector 045 selects the fourth sampled signal as the read enable signal and generates the read address, the read address is about 1.5 clock cycles later than the write address, and the data synchronization delay from the read clock domain to the write clock domain is about 1.5 clock cycles.
Fourthly, the phase discriminator 03 discriminates the phase difference of the clock to obtain: the value of the phase difference between the write clock domain and the read clock domain is greater than or equal to 3/4 clock cycles T, where T is the clock cycle of the write clock domain, as shown in fig. 4(d), and the clock phase difference between the write clock signal and the read clock signal is 7/8T, which corresponds to the clock phase difference in fig. 4(d), as shown in fig. 5(d), the read clock signal is used to sample the write enable signal in the manner described above, and the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal obtained by sampling do not exhibit a metastable state, in order to ensure a certain data synchronization delay, thereby ensuring that there is enough time to read data, but the data synchronization delay cannot be too large, generally within 2 clock cycles, the multi-path signal selector 045 selects the second sampling signal or the third sampling signal as the read enable signal and generates the read address, where the clock cycles of the second and third sampling signals delayed with respect to the write enable signal are the same and the read address is about 1 clock cycle later than the write address, then the data synchronization delay from the read clock domain to the write clock domain is about 1 clock cycle.
Based on the clock domain crossing synchronization circuit, the clock domain channel circuit 04 may sample the write enable signal to obtain a plurality of sampling results, where a delay of a part or all of the obtained sampling results with respect to the write enable signal is within two clock cycles, and then a clock phase difference exists between the write clock signal of the write clock domain and the read clock signal of the read clock domain, and according to the clock phase difference, a read enable signal is selected from the plurality of sampling results, and the delay of the selected read enable signal and the selected write enable signal may be controlled within two clock cycles. The data synchronization between the two clock domains is also within two clock cycles, so that compared with the existing scheme that the data synchronization between the two clock domains has the delay of at least two clock cycles, the data synchronization is realized with smaller delay.
The application also provides a clock domain crossing synchronization method which can be applied to the clock domain crossing synchronization circuit to realize the function of the clock domain crossing synchronization circuit.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present application can be implemented by software plus necessary general-purpose hardware, and certainly can also be implemented by special-purpose hardware including special-purpose integrated circuits, special-purpose CPUs, special-purpose memories, special-purpose components and the like. Generally, functions performed by computer programs can be easily implemented by corresponding hardware, and specific hardware structures for implementing the same functions may be various, such as analog circuits, digital circuits, or dedicated circuits. However, for the present application, the implementation of a software program is more preferable. Based on such understanding, the technical solutions of the present application may be substantially embodied in or contributed to by the prior art, and the computer software product may be stored in a readable storage medium, such as a floppy disk, a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk of a computer, and includes instructions for causing a computer device (which may be a personal computer or a server) to execute the method according to the embodiments of the present application.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.
The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

Claims (13)

  1. A clock domain crossing synchronization circuit, comprising a clock domain channel circuit, a write address generation circuit, a read address generation circuit, and a data buffer circuit, wherein:
    the write address generating circuit is used for obtaining a write address according to a write enable signal, the write address is used for controlling the data cache circuit to receive the input data, and the input data is in a write clock domain;
    the clock domain channel circuit is used for sampling the write enable signal to obtain a plurality of sampling results, and selecting one sampling result from the plurality of sampling results as a read enable signal according to a clock phase difference, wherein the clock phase difference is the phase difference between a write clock signal in the write clock domain and a read clock signal in the read clock domain;
    the read address generating circuit is used for obtaining a read address according to the read enable signal, the read address is used for controlling the data cache circuit to generate output data, and the output data is in the read clock domain;
    the data cache circuit is used for caching the input data and generating the output data according to the write address and the read address.
  2. The cross-clock domain synchronization circuit of claim 1, wherein the clock domain channel circuit comprises: a plurality of flip-flops, configured to sample the write enable signal on a rising edge and a falling edge of the read clock signal, respectively, so as to obtain a plurality of sampling results;
    and the multi-path signal selector is used for selecting one sampling result from the plurality of sampling results according to the clock phase difference to serve as the read enabling signal.
  3. The cross-clock domain synchronization circuit of claim 2, wherein the plurality of flip-flops comprises a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop;
    the first flip-flop is configured to sample the write enable signal at a falling edge of the read clock signal to obtain a first sampling signal;
    the second flip-flop is configured to sample the first sampling signal at a rising edge of the read clock signal to obtain a second sampling signal;
    the third flip-flop is configured to sample the write enable signal at a rising edge of the read clock signal to obtain a third sampling signal;
    the fourth flip-flop is configured to sample the third sampling signal at a rising edge of the read clock signal to obtain a fourth sampling signal, where the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal are the multiple sampling results.
  4. The cross-clock-domain synchronization circuit of claim 2 or 3, wherein the multi-way signal selector is specifically configured to:
    selecting the second sampling signal from the plurality of sampling results as the read enable signal if the clock phase difference is [0T,1/4T), where T is a clock period of the write clock domain or a clock period of the read clock domain;
    or the like, or, alternatively,
    select the second sampling signal or the fourth sampling signal as the read enable signal from the plurality of sampling results in a case where the clock phase difference is [1/4T,1/2T ];
    or the like, or, alternatively,
    select the fourth sampling signal as the read enable signal from the plurality of sampling results in a case where the clock phase difference is [1/2T,3/4T ];
    or the like, or, alternatively,
    and selecting the second sampling signal or the third sampling signal from the plurality of sampling results as the read enable signal when the value of the clock phase difference is greater than or equal to 3/4 clock cycles T.
  5. The cross-clock-domain synchronization circuit of any of claims 1 to 4, further comprising a phase detector;
    the phase discriminator is used for determining the clock phase difference according to the write clock signal and the read clock signal;
    the phase detector is further configured to generate the write enable signal according to the write clock signal, where the write enable signal is asserted when the clock phase difference between the write clock signal and the read clock signal is in a stable state.
  6. The cross-clock-domain synchronization circuit of any of claims 1 to 5, further comprising a fifth D flip-flop;
    and the fifth D flip-flop is configured to buffer and output the output data generated by the data buffer circuit under the driving of the read clock signal.
  7. The cross-clock domain synchronization circuit of any of claims 1 to 6, further comprising a write clock domain phase locked loop and a read clock domain phase locked loop;
    the write clock domain phase-locked loop is used for obtaining the write clock signal according to a clock source signal;
    and the read clock domain phase-locked loop is used for obtaining the read clock signal according to the clock source signal.
  8. The cross-clock-domain synchronization circuit of any one of claims 1 to 7, wherein the data cache circuit comprises a plurality of flip-flop groups, an input multiplexer comprising a plurality of output ports connected in a one-to-one correspondence with a plurality of input terminals of the plurality of flip-flop groups, and an output multiplexer comprising a plurality of input ports connected in a one-to-one correspondence with a plurality of output terminals of the plurality of flip-flop groups;
    the input multi-path data selector is used for receiving the input data and selecting one output port from the plurality of output ports of the input multi-path data selector to output cache data according to the write address, wherein the cache data is obtained by the input data;
    the plurality of trigger groups are used for caching the cache data under the driving of the write clock signal;
    the output multi-path data selector is configured to receive the plurality of cache data output by the plurality of flip-flop groups, and select one path of cache data from the plurality of cache data according to the read address to output the selected cache data as the output data.
  9. A method of synchronizing across clock domains, the method comprising:
    obtaining a write address according to a write enable signal, and receiving and caching input data according to the control of the write address, wherein the input data is in a write clock domain;
    sampling the write enable signal to obtain a plurality of sampling results, and selecting one sampling result from the plurality of sampling results as a read enable signal according to a clock phase difference, wherein the clock phase difference is the phase difference between a write clock signal in the write clock domain and a read clock signal in the read clock domain;
    and obtaining a read address according to the read enable signal, and outputting the cached input data according to the control of the read address to generate output data, wherein the output data is in the read clock domain.
  10. The method of claim 9, wherein sampling the write enable signal to obtain a plurality of sampling results comprises:
    and sampling the write enable signal at the rising edge and the falling edge of the read clock signal respectively to obtain a plurality of sampling results.
  11. The method of claim 10, wherein sampling the write enable signal on a rising edge and a falling edge of the read clock signal, respectively, to obtain the plurality of sampling results comprises:
    sampling the write enable signal at the falling edge of the read clock signal to obtain a first sampling signal;
    sampling the first sampling signal at the rising edge of the read clock signal to obtain a second sampling signal;
    sampling the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal;
    sampling the third sampling signal at a rising edge of the read clock signal to obtain a fourth sampling signal, wherein the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal are the multiple sampling results.
  12. The method according to any one of claims 9 to 11, wherein the selecting one of the plurality of sampling results as the read enable signal according to the clock phase difference comprises:
    selecting the second sampling signal from the plurality of sampling results as the read enable signal if the clock phase difference is [0T,1/4T), where T is a clock period of the write clock domain or a clock period of the read clock domain;
    or the like, or, alternatively,
    select the second sampling signal or the fourth sampling signal as the read enable signal from the plurality of sampling results in a case where the clock phase difference is [1/4T,1/2T ];
    or the like, or, alternatively,
    select the fourth sampling signal as the read enable signal from the plurality of sampling results in a case where the clock phase difference is [1/2T,3/4T ];
    or the like, or, alternatively,
    and selecting the second sampling signal or the third sampling signal from the plurality of sampling results as the read enable signal when the value of the clock phase difference is greater than or equal to 3/4 clock cycles T.
  13. The method according to any one of claims 9 to 12, further comprising:
    determining the clock phase difference according to the write clock signal and the read clock signal;
    generating the write enable signal according to the write clock signal, wherein the write enable signal is asserted when the clock phase difference between the write clock signal and the read clock signal is in a steady state.
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