CN114326515A - Synchronous acquisition method, system and equipment based on FPGA and readable storage medium - Google Patents
Synchronous acquisition method, system and equipment based on FPGA and readable storage medium Download PDFInfo
- Publication number
- CN114326515A CN114326515A CN202111652709.6A CN202111652709A CN114326515A CN 114326515 A CN114326515 A CN 114326515A CN 202111652709 A CN202111652709 A CN 202111652709A CN 114326515 A CN114326515 A CN 114326515A
- Authority
- CN
- China
- Prior art keywords
- acquisition
- data
- synchronous
- synchronization
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 134
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000005070 sampling Methods 0.000 claims abstract description 40
- 238000006243 chemical reaction Methods 0.000 claims description 103
- 230000015654 memory Effects 0.000 claims description 30
- 238000004891 communication Methods 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 9
- 238000001514 detection method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 10
- 239000013078 crystal Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101100478715 Drosophila melanogaster Start1 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention relates to the technical field of data detection, and discloses a synchronous sampling method, a system, equipment and a readable storage medium based on an FPGA. Wherein, the method comprises the following steps: acquiring data to be acquired and a synchronous acquisition strategy corresponding to each acquisition module; and performing multilevel synchronization on the data to be acquired based on the synchronization strategy to obtain synchronous acquisition data. By implementing the invention, the problem of real-time high-speed data acquisition and accurate synchronization of the multi-channel ADC is solved by adopting multi-stage synchronization, thereby realizing data synchronous acquisition and data real-time acquisition based on the FPGA.
Description
Technical Field
The invention relates to the technical field of data detection, in particular to a synchronous acquisition method, a system and equipment based on an FPGA and a readable storage medium.
Background
The FPGA-based data acquisition system is widely applied to the fields of military application, national defense construction, aerospace, industrial control and the like, and along with the rapid development of sensor technology and communication technology, the FPGA-based data acquisition system has the characteristics of high speed, high precision, real-time processing, good system stability, multiple channels and the like. In the prior art, most of the existing technologies are based on an Advanced RISC Machine (ARM) or a Digital Signal Processor (DSP) as a control core to achieve data acquisition. However, due to the wiring difference, clock error and the like of each analog-to-digital conversion (ADC) channel in the sampling circuit, there is a problem of data asynchronization between ADC channels, and particularly when multiple ADC chips work in parallel, two different channel differences occur: one is the difference between two acquisition circuits of the same ADC, and the other is the difference between acquisition circuits of different ADCs. Therefore, the existing data acquisition system is difficult to realize high-speed data acquisition processing real-time performance and synchronism.
Disclosure of Invention
In view of this, embodiments of the present invention provide a synchronous acquisition method, system, device and readable storage medium for an FPGA, so as to solve the problem that the existing data acquisition system is difficult to implement high-speed data acquisition and processing real-time performance and synchronization.
According to a first aspect, an embodiment of the present invention provides a synchronous acquisition method based on an FPGA, including: acquiring data to be acquired and a synchronous acquisition strategy corresponding to each acquisition module; and performing multilevel synchronization on the data to be acquired based on the synchronization strategy to obtain synchronous acquisition data.
According to the synchronous acquisition method based on the FPGA, the data to be acquired and the synchronous acquisition strategy corresponding to each acquisition module are acquired, and the data to be acquired are subjected to multilevel synchronization based on the synchronous strategy, so that the synchronous acquisition data are obtained. The method solves the problem of real-time high-speed data acquisition and accurate synchronization of a multi-channel ADC through multi-stage synchronization, thereby realizing data synchronous acquisition and data real-time acquisition based on the FPGA.
With reference to the first aspect, in a first implementation manner of the first aspect, performing multi-level synchronization on the data to be acquired based on the synchronization policy to obtain synchronized acquisition data includes: sequentially carrying out source clock synchronization, source reset synchronization, conversion start synchronization, conversion time synchronization and logic acquisition synchronization on the data to be acquired; and when the logic acquisition synchronization is finished, the synchronous acquisition data is obtained.
With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, the source clock synchronization of the data to be acquired includes: acquiring an input clock source; performing frequency multiplication processing on the input clock source to obtain a target clock; and performing time sequence control on the data to be acquired based on the target clock to obtain a first-stage acquisition signal with synchronous time sequence.
With reference to the first implementation manner of the first aspect, in a third implementation manner of the first aspect, the performing source reset synchronization on the data to be acquired includes: acquiring a reset signal; determining the acquisition time of the data to be acquired based on the reset signal; and controlling a plurality of acquisition modules to start acquisition of the data to be acquired simultaneously according to the acquisition time to obtain a second-stage acquisition signal with synchronous source resetting.
With reference to the first implementation manner of the first aspect, in a fourth implementation manner of the first aspect, the performing conversion and start synchronization on the data to be acquired includes: acquiring a data sampling rate; generating a data conversion start signal based on the data sampling rate; and controlling each acquisition module to simultaneously perform data conversion based on the data conversion signal to obtain a third-stage acquisition signal with synchronous conversion starting.
With reference to the first implementation manner of the first aspect, in a fifth implementation manner of the first aspect, the performing conversion time synchronization on the data to be acquired includes: acquiring data conversion time difference among the acquisition modules; and performing time compensation on the data conversion starting signals of all the acquisition modules based on the data conversion time difference to obtain fourth-stage acquisition signals with synchronous conversion time.
With reference to the first implementation manner of the first aspect, in a sixth implementation manner of the first aspect, the performing logic acquisition synchronization on the data to be acquired includes: acquiring a logic sampling time difference; and performing time compensation on the data conversion signals of all the acquisition modules based on the logic sampling time difference to obtain a fifth-level acquisition signal with synchronous logic acquisition.
According to the synchronous acquisition method based on the FPGA provided by the embodiment of the invention, the source clock synchronization, the source reset synchronization, the conversion start synchronization, the conversion time synchronization and the logic acquisition synchronization are sequentially carried out on the data to be acquired, and when the logic acquisition synchronization is completed, the acquisition signals subjected to multi-stage synchronization are obtained, so that the synchronization precision of the acquired data is improved, and the multi-channel data acquisition synchronization is realized.
With reference to the first aspect, in a seventh implementation of the first aspect, the method further includes: generating an acquisition result of the synchronous acquisition data; and sending the acquisition result to a display terminal, wherein the display terminal is used for displaying the synchronous acquisition data.
According to the synchronous acquisition method based on the FPGA provided by the embodiment of the invention, the acquisition result of the synchronous acquisition data is generated and is sent to the display terminal to be displayed, so that technicians can adjust related acquisition parameters in time when the data acquisition is asynchronous, and the synchronism of the data acquisition is ensured.
According to a second aspect, an embodiment of the present invention provides a synchronous acquisition system based on an FPGA, including: the FPGA is used for executing the FPGA-based synchronous acquisition method of the first aspect or any embodiment of the first aspect; and the display terminal is in communication connection with the FPGA and is used for displaying the synchronously acquired data.
The synchronous acquisition system based on the FPGA obtains the data to be acquired and the synchronous acquisition strategy corresponding to each acquisition module, and performs multi-level synchronization on the data to be acquired based on the synchronous strategy to obtain the synchronous acquisition data. The system solves the problem of real-time high-speed data acquisition and accurate synchronization of the multichannel ADC through multistage synchronization, thereby realizing data synchronous acquisition and data real-time acquisition based on the FPGA.
According to a third aspect, an embodiment of the present invention provides an electronic device, including: the FPGA-based synchronous acquisition method comprises a memory and a processor, wherein the memory and the processor are mutually connected in a communication manner, computer instructions are stored in the memory, and the processor executes the computer instructions so as to execute the FPGA-based synchronous acquisition method of the first aspect or any embodiment of the first aspect.
According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where computer instructions are stored, and the computer instructions are configured to cause a computer to execute the FPGA-based synchronous acquisition method according to the first aspect or any implementation manner of the first aspect.
It should be noted that, for corresponding beneficial effects of the electronic device and the computer-readable storage medium according to the embodiments of the present invention, please refer to the description of corresponding contents in the synchronous acquisition method based on the FPGA, which is not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for FPGA-based synchronous acquisition according to an embodiment of the present invention;
FIG. 2 is another flow chart of an FPGA-based synchronous acquisition method according to an embodiment of the present invention;
FIG. 3 is another flow chart of a method for FPGA-based synchronous acquisition according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an FPGA-based data acquisition system according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the completion of analog-to-digital conversion by each acquisition module according to an embodiment of the present invention;
FIG. 6 is a timing diagram illustrating synchronization of analog-to-digital conversion of various acquisition modules according to an embodiment of the present invention;
FIG. 7 is a timing diagram illustrating sampling asynchrony at the completion of analog-to-digital conversion, according to an embodiment of the present invention;
FIG. 8 is a timing diagram illustrating sample synchronization upon completion of analog-to-digital conversion according to an embodiment of the present invention;
fig. 9 is a schematic diagram of synchronous acquisition among the acquisition board cards according to the embodiment of the present invention;
FIG. 10 is a block diagram of an FPGA-based synchronous acquisition system according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The existing data acquisition system usually comprises a plurality of sampling circuits, and because of wiring difference, clock error and the like of each ADC channel in each sampling circuit, the problem of data asynchronism exists between the ADC channels, and particularly when a plurality of ADC chips work in parallel, two different channel differences can occur: one is the difference between two acquisition circuits of the same ADC, and the other is the difference between acquisition circuits of different ADCs. Therefore, the existing data acquisition system is difficult to realize high-speed data acquisition processing real-time performance and synchronism.
Based on the technical scheme, the synchronous acquisition strategy is arranged in the FPGA, and the data to be acquired are subjected to multi-stage synchronization through the synchronous acquisition strategy, so that the synchronous data acquisition and the real-time data acquisition based on the FPGA are realized.
In accordance with an embodiment of the present invention, there is provided an embodiment of an FPGA-based synchronous acquisition method, it is noted that the steps illustrated in the flowchart of the figures may be performed in a computer system such as a set of computer-executable instructions, and that while a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
In this embodiment, a synchronous acquisition method based on an FPGA is provided, which can be used for electronic devices, such as an FPGA, a ZYNQ FPGA, and a data acquisition device based on an FPGA, and fig. 1 is a flowchart of synchronous acquisition based on an FPGA according to an embodiment of the present invention, and as shown in fig. 1, the flowchart includes the following steps:
and S11, acquiring the data to be acquired and the synchronous acquisition strategy corresponding to each acquisition module.
The data to be acquired is acquired through each acquisition module, specifically, in the data acquisition system based on the FPGA, the FPGA performs data acquisition through an IO pin connection of an AD chip, and the AD chip can perform analog-to-digital conversion on the data received by the AD chip to obtain a data signal, and sends the data signal to the FPGA for data acquisition.
And S12, performing multilevel synchronization on the data to be acquired based on the synchronization strategy to obtain synchronous acquisition data.
The electronic equipment can operate a synchronization strategy when data acquisition is carried out, and multi-stage synchronous processing is carried out on data to be acquired, so that data signals of all ADC channels acquired by the electronic equipment in real time are synchronous, and synchronous acquisition data are obtained. Taking the data acquisition system based on the FPGA as an example as shown in fig. 4, the data acquisition system includes 3 ADC acquisition boards, the data acquisition system mainly depends on the pins of the FPGA and the ADC acquisition boards to be connected to realize data acquisition, and the IO pins related to synchronous acquisition include: a RESET pin (RESET), an analog-to-digital conversion starting pin (CONVST A/B) and an analog-to-digital conversion completion pin (BUSY). If each ADC acquisition board card can perform 8-channel data synchronous conversion, 3 ADC acquisition board cards of the data acquisition system are synchronous, and therefore synchronous acquisition of 24 ADC channels can be achieved, and synchronous acquisition data can be obtained.
According to the synchronous acquisition method based on the FPGA, the data to be acquired and the synchronous acquisition strategy corresponding to each acquisition module are acquired, and the data to be acquired are subjected to multilevel synchronization based on the synchronous strategy, so that the synchronous acquisition data are obtained. The method solves the problem of real-time high-speed data acquisition and accurate synchronization of a multi-channel ADC through multi-stage synchronization, thereby realizing data synchronous acquisition and data real-time acquisition based on the FPGA.
In this embodiment, a synchronous acquisition method based on an FPGA is provided, which can be used for electronic devices, such as an FPGA, a ZYNQ FPGA, and a data acquisition device based on an FPGA, and fig. 2 is a flowchart of synchronous acquisition based on an FPGA according to an embodiment of the present invention, and as shown in fig. 2, the flowchart includes the following steps:
and S21, acquiring the data to be acquired and the synchronous acquisition strategy corresponding to each acquisition module. For a detailed description, refer to the related description of step S11 corresponding to the above embodiment, and the detailed description is omitted here.
And S22, performing multilevel synchronization on the data to be acquired based on the synchronization strategy to obtain synchronous acquisition data.
Specifically, the step S22 may include:
and S221, sequentially carrying out source clock synchronization, source reset synchronization, conversion start synchronization, conversion time synchronization and logic acquisition synchronization on the data to be acquired based on the synchronization strategy.
The electronic equipment performs source clock synchronization on data to be acquired to realize first-level synchronization; then, source reset synchronization is carried out on the data to be acquired, and second-level synchronization is realized; then, converting and synchronizing the data to be acquired to realize third-level synchronization; then, the conversion time synchronization is carried out on the data to be acquired, and the fourth-level synchronization is realized; and then, carrying out logic acquisition synchronization on data to be acquired to realize fifth-level synchronization.
And S222, when the logic acquisition synchronization is completed, acquiring synchronous acquisition data.
The electronic equipment can monitor the completion state of the logic acquisition synchronization, when the logic acquisition synchronization is completed, the multi-stage synchronization of the data to be acquired is shown, and the electronic equipment can obtain the synchronous acquisition data of a plurality of acquisition channels.
Specifically, the source clock synchronization of the data to be collected in step S221 may include:
(1) an input clock source is obtained.
The input clock source is a crystal oscillator or a crystal 25MHz clock source, taking FPGA as an example, the FPGA is used as a hardware chip on which the crystal oscillator or the crystal is disposed, and the input clock source can be used as the input clock source of the FPGA depending on the precise crystal oscillator or the crystal 25MHz clock source provided by hardware.
(2) And carrying out frequency multiplication on the input clock source to obtain a target clock.
The target clock is a clock signal for driving the acquisition board, and the electronic device can perform frequency multiplication operation on an input clock source by using a clock resource to generate the target clock for driving the acquisition board. For example, the FPGA performs frequency multiplication on a 25MHz input clock source by using an FPGA clock resource phase-locked loop PLL to generate a 50MHz system clock, and uses the system clock as a target clock.
(3) And performing time sequence control on the data to be acquired based on the target clock to obtain a first-stage acquisition signal with synchronous time sequence.
The electronic equipment drives the plurality of acquisition board cards connected with the electronic equipment according to the target clock so as to perform time sequence control on the plurality of acquisition board cards and obtain a first-stage acquisition signal subjected to time sequence synchronization. Specifically, the FPGA drives the acquisition board card by using a target clock, as shown in fig. 4, the FPGA can drive IO pins (a reset pin, an analog-to-digital conversion start pin, an analog-to-digital conversion end pin, and the like) of 3 acquisition board cards by using the same target clock (50MHz), so that the IO pins of the 3 acquisition board cards can perform timing control by using the same clock, that is, timing synchronization of the IO pins of the 3 acquisition board cards connected to the FPGA is controlled, and first-stage synchronization between the acquisition board cards is realized.
Specifically, the source reset synchronization of the data to be collected in step S221 may include:
(4) a reset signal is acquired.
The reset signal is generated after the electronic device is powered on, taking the FPGA as an example, when the FPGA is powered on, the processor of the FPGA is correspondingly powered on, and at the moment, the reset signal is generated to realize the reset operation of the FPGA.
(5) The acquisition time of the data to be acquired is determined based on the reset signal.
The acquisition time is the starting time of the electronic equipment for controlling the acquisition board card to acquire data. Taking the data acquisition system shown in fig. 4 as an example, after the processor of the FPGA is powered on, a reset signal is generated, the reset signal may be connected to the reset pins of the 3 acquisition boards, and after the connection from the reset signal to the reset pins is completed, the completion time of connecting the reset signal to the reset pins is taken as the acquisition time.
(6) And controlling a plurality of acquisition modules according to the acquisition time to start acquisition of data to be acquired simultaneously to obtain a second-stage acquisition signal with synchronous source resetting.
The acquisition module is an acquisition board card, an acquisition chip and the like for data acquisition, and can be other acquisition circuits, and the acquisition module is not particularly limited and can be determined by a person skilled in the art according to actual needs. Specifically, the electronic device can control each acquisition board card to start data acquisition operation simultaneously based on acquisition time, so that each acquisition board card starts acquisition at the same time point, and second-level synchronization between the acquisition board cards is realized.
Specifically, the converting and starting synchronization of the data to be collected in step S221 may include:
(7) a data sampling rate is obtained.
The data sampling rate is used to represent a sampling speed or a sampling frequency of the acquisition board for data sampling, and the data sampling rate may be determined according to a sampling rate requirement of a technician, for example, the data sampling rate may be 12.8KSPS, and may also be other values, which is not specifically limited herein.
(8) A data transition start signal is generated based on the data sampling rate.
The data conversion starting signal is a signal for starting data conversion of the acquisition board card, and the electronic equipment can generate the data conversion starting signal according to the data sampling rate so as to control the acquisition board card to start data conversion. For example, the FPGA may generate an analog-to-digital conversion start signal according to the data sampling rate.
(9) And controlling each acquisition module to simultaneously perform data conversion based on the data conversion signal to obtain a third-stage acquisition signal with synchronous conversion starting.
The electronic equipment can connect the data conversion signal to the data conversion starting signal pin of each acquisition module to control each acquisition module to start data conversion simultaneously, so as to obtain a third-stage acquisition signal with synchronous conversion starting. For example, the data conversion start signal may be an analog-to-digital conversion start signal, the FPGA connects the analog-to-digital conversion start signal to analog-to-digital conversion start signal pins of the 3 acquisition boards, and controls the 3 acquisition boards to start analog-to-digital conversion at the same time, so as to implement third-level synchronization between the acquisition boards. It should be noted that synchronous data acquisition between the acquisition board cards is based on the consistency of the sampling rates of all channels.
Specifically, the converting time synchronization of the data to be collected in step S221 may include:
(10) and acquiring data conversion time difference among the acquisition modules.
The data conversion time difference is the time difference of finishing data conversion by each acquisition module. When the electronic device receives a signal that data conversion is started to be completed synchronously, the electronic device can acquire the data conversion completion time of each acquisition module, and calculate the data conversion time difference between the acquisition modules according to the data conversion completion time of each acquisition module.
Taking FPGA as an example, FPGA can determine whether analog-to-digital conversion is completed by monitoring the BUSY pin of the acquisition board, specifically, FPGA can detect the falling edge (analog-to-digital conversion) of the BUSY pin in real time, and when receiving analog-to-digital conversion completion signals of 3 acquisition boards, the FPGA records timestamps T1, T2, and T3 of the 3 acquisition boards (acquisition board 1, acquisition board 2, and acquisition board 3) completing analog-to-digital conversion, respectively, as shown in fig. 5. The FPGA sequences T1, T2, and T3, and if the sequence from small to large is T3, T1, and T2, based on the minimum time T3, calculates a difference Δ T1 between T1 and T3 (Δ T1 is T1-T3), and a difference Δ T2 between T2 and T3 (Δ T2 is T2-T3), where Δ T1>0, Δ T2>0, Δ T1, and Δ T2 are used to characterize the data conversion time difference between the acquisition cards and the pin wiring delay, where the wiring delay is the line delay caused by layout wiring when the digital-to-analog conversion start pins of the 3 acquisition cards arrive at three pins of the FPGA.
(11) And performing time compensation on the data conversion starting signals of all the acquisition modules based on the data conversion time difference to obtain fourth-stage acquisition signals with synchronous conversion time.
And the electronic equipment performs time compensation on the data conversion starting signals of the acquisition modules according to the data conversion time difference so that the data conversion of the acquisition boards can be completed synchronously, and fourth-stage acquisition signals synchronized by conversion time are obtained.
Specifically, the electronic device delays and controls analog-to-digital conversion starting signals among the 3 acquisition board cards to achieve accurate synchronization among the acquisition board cards. Since Δ t2 is greater than Δ t1, the time for the acquisition board card 2 to complete analog-to-digital conversion is longest, and then the time for the acquisition board card 1 to complete analog-to-digital conversion is shortest, and the time for the acquisition board card 3 to complete analog-to-digital conversion is shortest. With the acquisition board card 3 as a reference, the FPGA first sends an analog-to-digital conversion START signal START2 to the analog-to-digital conversion pin of the acquisition board card 2, sends an analog-to-digital conversion START signal START1 to the analog-to-digital conversion pin of the acquisition board card 1 after the time of Δ T2- Δ T1, and sends an analog-to-digital conversion START signal START3 to the analog-to-digital conversion pin of the acquisition board card 3 after the time of Δ T1, so that the FPGA can perform accurate compensation of the START of analog-to-digital conversion on 3 acquisition board cards respectively, so that the time for completing analog-to-digital conversion of the 3 acquisition board cards is equal, that is, T1 is T2 is T3, thereby realizing fourth-level synchronization between the acquisition board cards, as shown in fig. 6.
Specifically, the logic acquisition synchronization of the data to be acquired in step S221 may include:
(12) a logical sample time difference is obtained.
The logical sampling time difference is a logical sampling time difference between the respective acquisition modules, and the logical sampling time difference can be determined based on a relationship between the setup time and the hold time corresponding to the sampling system. The establishment time is the minimum time for data to be stable before a clock trigger event comes, so that the data is accurate when sampled by a clock signal; the hold time is the minimum time that the data needs to be held stable after the clock trigger event comes, so that the data can be accurately sampled.
The synchronous circuit used by the electronic device for data synchronous acquisition is a circuit composed of a sequential circuit (a register and various triggers) and a combinational logic circuit, all operations of the synchronous circuit are completed under strict clock control, the sequential circuit shares the same clock CLK, and all state changes are completed on the rising edge (or the falling edge) of the clock.
Because the data sampling of the FPGA is realized by using sequential logic, the sequential logic sampling has two basic conditions which are respectively: the sampling must be done on the rising (or falling) edge of the clock and the sampling must meet the setup and hold times. The FPGA detects an analog-to-digital conversion completion signal BUSY between 3 acquisition board cards by using a 50MHz clock, and if two basic conditions of sequential logic sampling cannot be met at the same moment, the analog-to-digital conversion completion signal BUSY between the acquisition board cards has the condition of asynchronous data sampling, as shown in FIG. 7, the asynchronous data sampling is nanosecond, the clock frequency is 50MHz, and the clock period is 20 ns.
(13) And performing time compensation on the data conversion signals of all the acquisition modules based on the logic sampling time difference to obtain a fifth-level acquisition signal with synchronous logic acquisition.
The electronic equipment performs time compensation on the data conversion signals of all the acquisition modules according to the logic sampling time difference, so that the data conversion of all the acquisition boards can be logically synchronized, and a fifth-level acquisition signal synchronized with logic acquisition is obtained.
Specifically, as shown in fig. 8, when the FPGA samples an analog-to-digital conversion completion signal (BUSY pin) between 3 acquisition boards, when the FPGA logically samples that the analog-to-digital conversion of any acquisition board is completed, the first analog-to-digital conversion completion signal (BUSY1) is used as a reference signal to delay, that is, the FPGA can sample the first conversion completion BUSY1 at a time T1, after delaying for 2 clock cycles, after a time T2, the analog-to-digital conversion of 3 acquisition boards is completed, and from a time T2, the FPGA can read all channel data at the same time (T2), so that accurate synchronous sampling between three acquisition boards is ensured, and fifth-level synchronization between the acquisition boards is realized.
As shown in fig. 9, a schematic diagram of synchronous acquisition among 3 acquisition cards, where logic sampling is delayed by 2 clock cycles, the clock cycle is 20ns, that is, the actual data acquisition synchronization accuracy can reach 40ns, the inter-board synchronization accuracy mainly depends on the system working clock, if the clock frequency is 100MHz, the clock cycle is 10ns, the inter-board synchronization accuracy can reach 20ns, that is, the higher the clock frequency, the higher the inter-board synchronization accuracy.
According to the synchronous acquisition method based on the FPGA, source clock synchronization, source reset synchronization, conversion start synchronization, conversion time synchronization and logic acquisition synchronization are sequentially performed on data to be acquired, and when the logic acquisition synchronization is completed, multi-stage synchronous acquisition signals are obtained, so that the synchronization precision of the acquired data is improved, and multi-channel data acquisition synchronization is realized.
In this embodiment, a synchronous acquisition method based on an FPGA is provided, which can be used for electronic devices, such as an FPGA, a ZYNQ FPGA, and a data acquisition device based on an FPGA, and fig. 3 is a flowchart of synchronous acquisition based on an FPGA according to an embodiment of the present invention, and as shown in fig. 3, the flowchart includes the following steps:
in this embodiment, a synchronous acquisition method based on an FPGA is provided, which can be used for electronic devices, such as an FPGA, a ZYNQ FPGA, and a data acquisition device based on an FPGA, and fig. 3 is a flowchart of synchronous acquisition based on an FPGA according to an embodiment of the present invention, and as shown in fig. 3, the flowchart includes the following steps:
and S31, acquiring the data to be acquired and the synchronous acquisition strategy corresponding to each acquisition module. For a detailed description, refer to the related description of step S11 corresponding to the above embodiment, and the detailed description is omitted here.
And S32, performing multilevel synchronization on the data to be acquired based on the synchronization strategy to obtain synchronous acquisition data. For a detailed description, refer to the related description of step S12 corresponding to the above embodiment, and the detailed description is omitted here.
And S33, generating an acquisition result of the synchronous acquisition data.
The acquisition result is an acquisition synchronization result when the electronic equipment performs data acquisition, and whether the data acquisition is synchronous or not can be determined according to the acquisition result. Specifically, when the data acquisition system based on the FPGA acquires data, the acquired data can be synchronously processed, and an acquisition result corresponding to the synchronously acquired data is generated and output to the display terminal.
And S34, sending the acquisition result to a display terminal, wherein the display terminal is used for displaying the acquisition result of the synchronously acquired data.
The electronic equipment can send the acquisition result to the display terminal to make the display terminal display the acquisition result, and the technical staff can check the acquisition result of the data acquisition system and determine whether the data acquisition is synchronous according to the acquisition result. Specifically, the FPGA can perform synchronous data acquisition on the digital signals of each ADC acquisition board, generate an acquisition result of the synchronous acquisition data after stopping the data acquisition, and send the acquisition result of the synchronous acquisition data to the display terminal through the ethernet interface, so that the display terminal displays the acquisition result of the synchronous acquisition data.
According to the synchronous acquisition method based on the FPGA, the acquisition result of the generated synchronous acquisition data is sent to the display terminal to be displayed, so that technicians can adjust related acquisition parameters in time when the data acquisition is asynchronous, and the synchronism of the data acquisition is ensured.
The embodiment also provides a synchronous acquisition system based on an FPGA, and the system is used to implement the above embodiments and preferred embodiments, and the description of the system already made is omitted. While the system described in the embodiments below is preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.
The present embodiment provides a synchronous acquisition system based on FPGA, as shown in fig. 10, including:
and the FPGA41 is used for executing the FPGA-based synchronous acquisition method in the embodiment. The FPGA may include: the acquisition module is used for acquiring the data to be acquired and the synchronous acquisition strategies corresponding to the acquisition modules; and the synchronization module is used for performing multilevel synchronization on the data to be acquired based on the synchronization strategy to obtain synchronous acquisition data. For a detailed description, reference is made to the description of the above method embodiments, which are not repeated herein.
And the display terminal 42 is in communication connection with the FPGA and is used for displaying the synchronously acquired data. The display terminal can be used as an upper computer (PC) and connected with the FPGA through an Ethernet interface, a serial port interface and other interactive interfaces so as to display an acquisition result obtained by the FPGA for synchronous data acquisition.
The FPGA in this embodiment is presented in the form of functional units, where a unit refers to an ASIC circuit, a processor and memory that execute one or more software or fixed programs, and/or other devices that can provide the above functionality.
Further functional descriptions of the modules are the same as those of the corresponding embodiments, and are not repeated herein.
The synchronous acquisition system based on the FPGA obtains the data to be acquired and the synchronous acquisition policy corresponding to each acquisition module, and performs multi-level synchronization on the data to be acquired based on the synchronous acquisition policy to obtain the synchronous acquisition data. The system solves the problem of real-time high-speed data acquisition and accurate synchronization of the multichannel ADC through multistage synchronization, thereby realizing data synchronous acquisition and data real-time acquisition based on the FPGA.
An embodiment of the present invention further provides an electronic device, which has the FPGA-based synchronous acquisition system shown in fig. 10.
Referring to fig. 11, fig. 11 is a schematic structural diagram of an electronic device according to an alternative embodiment of the present invention, and as shown in fig. 11, the electronic device may include: at least one processor 501, such as a CPU (Central Processing Unit), at least one communication interface 503, memory 504, and at least one communication bus 502. Wherein a communication bus 502 is used to enable connective communication between these components. The communication interface 503 may include a Display (Display) and a Keyboard (Keyboard), and the optional communication interface 503 may also include a standard wired interface and a standard wireless interface. The Memory 504 may be a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The memory 504 may optionally be at least one storage device located remotely from the processor 501. Wherein the processor 501 may be combined with the FPGA-based synchronous acquisition system described in fig. 10, the memory 504 stores an application program, and the processor 501 calls a program code stored in the memory 504 to perform any of the above method steps.
The communication bus 502 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 502 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 11, but this is not intended to represent only one bus or type of bus.
The memory 504 may include a volatile memory (RAM), such as a random-access memory (RAM); the memory may also include a non-volatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviated: HDD) or a solid-state drive (english: SSD); the memory 504 may also comprise a combination of the above types of memory.
The processor 501 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of CPU and NP.
The processor 501 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.
Optionally, the memory 504 is also used to store program instructions. The processor 501 may call a program instruction to implement the FPGA-based synchronous acquisition method as shown in the embodiments of fig. 1 to 3 of the present application.
The embodiment of the invention also provides a non-transitory computer storage medium, wherein the computer storage medium stores computer executable instructions which can execute the processing method of the synchronous acquisition method based on the FPGA in any method embodiment. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (11)
1. A synchronous acquisition method based on FPGA is characterized by comprising the following steps:
acquiring data to be acquired and a synchronous acquisition strategy corresponding to each acquisition module;
and performing multilevel synchronization on the data to be acquired based on the synchronization strategy to obtain synchronous acquisition data.
2. The method of claim 1, wherein performing multi-level synchronization on the data to be collected based on the synchronization policy to obtain synchronized collected data comprises:
sequentially carrying out source clock synchronization, source reset synchronization, conversion start synchronization, conversion time synchronization and logic acquisition synchronization on the data to be acquired;
and when the logic acquisition synchronization is finished, the synchronous acquisition data is obtained.
3. The method of claim 2, wherein source clock synchronizing the data to be collected comprises:
acquiring an input clock source;
performing frequency multiplication processing on the input clock source to obtain a target clock;
and performing time sequence control on the data to be acquired based on the target clock to obtain a first-stage acquisition signal with synchronous time sequence.
4. The method of claim 2, wherein source reset synchronization of the data to be collected comprises:
acquiring a reset signal;
determining the acquisition time of the data to be acquired based on the reset signal;
and controlling a plurality of acquisition modules to start acquisition of the data to be acquired simultaneously according to the acquisition time to obtain a second-stage acquisition signal with synchronous source resetting.
5. The method of claim 2, wherein synchronizing the start of conversion of the data to be collected comprises:
acquiring a data sampling rate;
generating a data conversion start signal based on the data sampling rate;
and controlling each acquisition module to simultaneously perform data conversion based on the data conversion signal to obtain a third-stage acquisition signal with synchronous conversion starting.
6. The method of claim 2, wherein synchronizing the time of conversion of the data to be collected comprises:
acquiring data conversion time difference among the acquisition modules;
and performing time compensation on the data conversion starting signals of all the acquisition modules based on the data conversion time difference to obtain fourth-stage acquisition signals with synchronous conversion time.
7. The method of claim 2, wherein synchronizing the logical acquisition of the data to be acquired comprises:
acquiring a logic sampling time difference;
and performing time compensation on the data conversion signals of all the acquisition modules based on the logic sampling time difference to obtain a fifth-level acquisition signal with synchronous logic acquisition.
8. The method of any one of claims 1-7, further comprising:
generating an acquisition result of the synchronous acquisition data;
and sending the acquisition result to a display terminal, wherein the display terminal is used for displaying the synchronous acquisition data.
9. The utility model provides a synchronous collection system based on FPGA which characterized in that includes:
an FPGA for performing the FPGA-based synchronous acquisition method of any one of claims 1-8;
and the display terminal is in communication connection with the FPGA and is used for displaying the synchronously acquired data.
10. An electronic device, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the FPGA-based synchronous acquisition method of any one of claims 1-8.
11. A computer-readable storage medium storing computer instructions for causing a computer to perform the FPGA-based synchronous acquisition method of any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111652709.6A CN114326515A (en) | 2021-12-30 | 2021-12-30 | Synchronous acquisition method, system and equipment based on FPGA and readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111652709.6A CN114326515A (en) | 2021-12-30 | 2021-12-30 | Synchronous acquisition method, system and equipment based on FPGA and readable storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114326515A true CN114326515A (en) | 2022-04-12 |
Family
ID=81018622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111652709.6A Pending CN114326515A (en) | 2021-12-30 | 2021-12-30 | Synchronous acquisition method, system and equipment based on FPGA and readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114326515A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4983969A (en) * | 1987-12-23 | 1991-01-08 | Kabushiki Kaisha Toshiba | Successive approximation analog to digital converter |
| CN105915241A (en) * | 2016-04-13 | 2016-08-31 | 信阳师范学院 | Method and system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in FPGA |
| CN109617552A (en) * | 2019-01-04 | 2019-04-12 | 南京华讯方舟通信设备有限公司 | Multichannel A/D conversion system and its conversion method |
| CN110321316A (en) * | 2019-06-19 | 2019-10-11 | 西安思丹德信息技术有限公司 | A kind of multi-channel synchronous data acquisition adaptive training control device and method |
| US20200005840A1 (en) * | 2018-06-28 | 2020-01-02 | Micron Technology, Inc. | Data strobe calibration |
| CN113535620A (en) * | 2021-06-29 | 2021-10-22 | 电子科技大学 | Multichannel synchronous high-speed data acquisition device |
| CN113615088A (en) * | 2019-03-26 | 2021-11-05 | 华为技术有限公司 | Clock domain crossing synchronization circuit and method |
-
2021
- 2021-12-30 CN CN202111652709.6A patent/CN114326515A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4983969A (en) * | 1987-12-23 | 1991-01-08 | Kabushiki Kaisha Toshiba | Successive approximation analog to digital converter |
| CN105915241A (en) * | 2016-04-13 | 2016-08-31 | 信阳师范学院 | Method and system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in FPGA |
| US20200005840A1 (en) * | 2018-06-28 | 2020-01-02 | Micron Technology, Inc. | Data strobe calibration |
| CN109617552A (en) * | 2019-01-04 | 2019-04-12 | 南京华讯方舟通信设备有限公司 | Multichannel A/D conversion system and its conversion method |
| CN113615088A (en) * | 2019-03-26 | 2021-11-05 | 华为技术有限公司 | Clock domain crossing synchronization circuit and method |
| CN110321316A (en) * | 2019-06-19 | 2019-10-11 | 西安思丹德信息技术有限公司 | A kind of multi-channel synchronous data acquisition adaptive training control device and method |
| CN113535620A (en) * | 2021-06-29 | 2021-10-22 | 电子科技大学 | Multichannel synchronous high-speed data acquisition device |
Non-Patent Citations (3)
| Title |
|---|
| 叶忠辉;蒋志迪;汪鹏君;: "基于FPGA的自适应TIADC数据采集", 数学的实践与认识, no. 08 * |
| 常宗杰，等: "基于锁相环的水听器阵列多传感器高精度同步技术", 计算机应用研究, pages 1140 - 1142 * |
| 杨会伟，马书香，周先飞: "十六通道高精度同步数据采集系统设计", 兰州文理学院学报(自然科学版), pages 62 - 66 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104714871B (en) | Programmable parallel port sequence testing circuit based on FPGA | |
| JP2008510967A (en) | Time measurement using a phase-shifted periodic waveform | |
| US10083137B2 (en) | Peripheral interface circuit for serial memory | |
| CN101834715A (en) | Data processing method, data processing system and data processing device | |
| TW201710701A (en) | Integrated circuit with scanning test and test method of integrated circuit achieving the purpose of reducing the manufacturing cost and the circuit area | |
| CN107562163B (en) | Digital logic circuit with stable reset control | |
| CN115238619A (en) | Sub-module post-simulation method and system of digital chip | |
| CN104283531A (en) | Clock jitter and power supply noise analysis | |
| US8144828B2 (en) | Counter/timer functionality in data acquisition systems | |
| CN113985251A (en) | Delay deviation measuring method and device of digital channel and electronic device | |
| CN116301268B (en) | Reset signal preprocessing device and method and programmable logic device | |
| CN107132469B (en) | Multipath signal detection method, circuit and control chip | |
| CN114326515A (en) | Synchronous acquisition method, system and equipment based on FPGA and readable storage medium | |
| CN103675383B (en) | A kind of circuit measuring waveform | |
| CN112989758A (en) | Method for synchronously resetting multiple prototype verification boards, verification system and storage medium | |
| CN104866640A (en) | Full FIFO (first in, first out) circuit design method and universal test bench of method | |
| EP4012423A1 (en) | Detection circuit and detection method | |
| CN102163967B (en) | Method for sampling pulse data | |
| CN105718402B (en) | Programmable timing generator | |
| CN113961137A (en) | Data acquisition method and device and electronic equipment | |
| CN107741919B (en) | Data communication device applied to control system | |
| CN112886951A (en) | Multi-clock-source seamless switching circuit and method of high-precision time keeping equipment | |
| CN101303710B (en) | Simulation control method and system for programmable logic device | |
| CN114924614A (en) | Multi-board output signal synchronization method and device | |
| RU2806240C1 (en) | Detection scheme and detection method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |