CN102789262A

CN102789262A - Clock zone spanning asynchronous signal synchronization circuit

Info

Publication number: CN102789262A
Application number: CN2012102510442A
Authority: CN
Inventors: 余志军; 杨博
Original assignee: 771 Research Institute of 9th Academy of CASC
Current assignee: 771 Research Institute of 9th Academy of CASC
Priority date: 2012-07-19
Filing date: 2012-07-19
Publication date: 2012-11-21

Abstract

A clock zone spanning asynchronous signal synchronization circuit includes a clock zone 1 and a clock zone 2, wherein a pulse signal is transmitted to the clock zone 2 from the clock zone 1; the clock zone 1 includes a pulse holding register and an inverting circuit that are connected sequentially; the clock zone 2 includes a synchronous circuit, a register Q3 and an XOR circuit; the pulse signal sequentially passes by the pulse holding register for holding, the inverting circuit for inversion and the two-stage register in the synchronous circuit for removing the metastable state and then the register Q3 for outputting a signal subjected to XOR operation with the output signal of the two-stage register through the XOR circuit, and the final clock zone asynchronous signal is obtained.

Description

A kind of cross clock domain asynchronous signal synchronizing circuit

Technical field:

The invention belongs to integrated circuit fields, be specifically related to a kind of cross clock domain asynchronous signal synchronizing circuit that is.

Background technology:

Technical indicators such as high integration, multifunctionality, low-power consumption, miniaturization are paid attention in the design of current chip day by day, and it directly affects entire chip design industry.And along with the continuous innovation of the technology of chip industry; And the simplification of system applies design and the diversified requirement appearance of design function; Brought the non-linear raising of the functional complexity of chip, the clock number of chip also is on the increase thereupon, and it is complicated that the signal of cross clock domain also must become alternately.

At present various to the signal processing mode of cross clock domain, do not have one can be general design circuit, and to the signal analysis of cross clock domain, be broadly divided into pulse to pulse, these two kinds of signals of pulse to level are mutual.The present invention proposes simple a, treatment circuit of the interactive signal of cross clock domain reliably, principle is simple, design ingenious, in its circuit design applicable to present cross clock domain.

Summary of the invention:

To above-mentioned defective or deficiency, the objective of the invention is to propose a kind of universalization treatment circuit of realizing the interactive signal of cross clock domain in the current complex chip design, reduce design complexities, improve chip reliability.Specific as follows:

The asynchronous signal synchronizing circuit of a kind of cross clock domain pulse to pulse comprises clock zone 1 and clock zone 2; Pulse signal is transferred to clock zone 2 from clock zone 1; Clock zone 1 comprises that the pulse that connects successively keeps register, negate circuit; Clock zone 2 comprises synchronizing circuit, register Q3 and XOR circuit; Pulse signal is through successively after extra pulse keeps register maintenance, the negate of negate circuit; Go to export a signal behind metastable state, the register Q3 through the two-stage register in the synchronizing circuit; This signal passes through XOR circuit XOR mutually with the output signal of said two-stage register, obtains final clock zone synchronizing signal.

The asynchronous signal synchronizing circuit of a kind of cross clock domain pulse to level comprises clock zone 1 and clock zone 2; Pulse signal is transferred to clock zone 2 from clock zone 1 and obtains level signal; Clock zone 1 comprises that the pulse that connects successively keeps register, negate circuit; Clock zone 2 comprises synchronizing circuit, register Q3 and XOR circuit; Pulse signal is through successively after extra pulse keeps register maintenance, the negate of negate circuit; Go to export a signal behind metastable state, the register Q3 through the two-stage register in the synchronizing circuit; This signal passes through XOR circuit XOR mutually with the output signal of said two-stage register, obtains final level signal.Said register Q3 is the register of band Enable Pin.

The invention has the beneficial effects as follows:

The design's circuit is the General design method of the particular phenomenon of microelectronic chip in designing; Be mainly used in the circuit design of multi-clock zone, and the low power consumption design method in the present chip design improves the low power capabilities index with regard to relating to through the method for designing of clock for a long time in learning.Send bright its highly versatile elsewhere, characteristic that reliability is high is applicable to the microelectronic chip design, particularly in the chip design of low-power consumption multi-clock zone.

This circuit satisfies the low-power consumption of space requirement, requirement such as highly reliable, and in the SiP of the great special project of 11th Five-Year chip design, has been applied.

Description of drawings:

Fig. 1 is the structural drawing of pulse to pulse.

Fig. 2 is that pulse sequence figure is changeed in pulse.

The structural drawing of Fig. 3 pulse to level.

The level sequential chart is changeed in Fig. 4 pulse.

Embodiment:

Below in conjunction with accompanying drawing the present invention is done detailed description.

1) as shown in Figure 1: pulse to pulsing circuit designs

Pulse signal in clock zone CLK1 need be transferred to clock zone CLK2, and is the conversion of pulse to pulse.Use the CLK1 pulse signals to keep earlier and cross the negate circuit and generate pulse_tgo_s; Go metastable state through Sync circuit CLK2 two-stage register Q1, Q2; After the signal of CLK2 second level register is deposited Q3 again; And get the second level register Q2 of CLK2 and the output valve of register Q3 is done XOR, thereby realize the conversion of the pulse of CLK1 to the pulse in CLK2 territory; When CLK1 had another one pulse signal, the signal that then kept pulse last time was then got into clock zone CLK2 by negate, and the circuit in CLK2 territory is constant, realized the transmission of pulse signal, and circuit structure diagram and sequential chart are seen accompanying drawing 1 and accompanying drawing 2.This circuit is applicable to fast clock zone to slow clock zone, and slow clock zone is to fast clock zone.

2) pulse to level circuit designs

At the pulse signal of clock zone CLK1, be transferred to the CLK2 clock zone, and be level signal, by the CLK2 decision level retention time.Pulse signal keeps register after the negate circuit generates pulse_tgo_s and to the Sync synchronizing circuit through pulse; Sync circuit two-stage is gone metastable state synchronously; Then through the register output signal of band Enable Pin, the second level register output signal of this signal and Sync circuit is done the XOR outputs level signals; The cancellation of level signal is by the clear_i signal deciding in CLK2 territory; This clear_i signal is a single pulse signal; Effective when the clear_i signal, the second level register signal of Sync is outputed to the Q3 register, this moment, the output signal of Q3 was identical with the output valve of the second level register of Sync circuit; The level cancellation, circuit structure diagram and sequential chart are seen accompanying drawing 3 and accompanying drawing 4.This circuit is applicable to fast clock zone to slow clock zone, and slow clock zone is to fast clock zone.

Claims

1. the asynchronous signal synchronizing circuit of cross clock domain pulse a to pulse is characterized in that: comprise clock zone 1 and clock zone 2; Pulse signal is transferred to clock zone 2 from clock zone 1; Clock zone 1 comprises that the pulse that connects successively keeps register, negate circuit; Clock zone 2 comprises synchronizing circuit, register Q3 and XOR circuit; Pulse signal is through successively after extra pulse keeps register maintenance, the negate of negate circuit; Go to export a signal behind metastable state, the register Q3 through the two-stage register in the synchronizing circuit; This signal passes through XOR circuit XOR mutually with the output signal of said two-stage register, obtains final pulse clock territory synchronizing signal.

2. the asynchronous signal synchronizing circuit of cross clock domain pulse a to level is characterized in that: comprise clock zone 1 and clock zone 2; Pulse signal is transferred to clock zone 2 from clock zone 1 and obtains level signal; Clock zone 1 comprises that the pulse that connects successively keeps register, negate circuit; Clock zone 2 comprises synchronizing circuit, register Q3 and XOR circuit; Pulse signal is through successively after extra pulse keeps register maintenance, the negate of negate circuit; Go to export a signal behind metastable state, the register Q3 through the two-stage register in the synchronizing circuit; This signal passes through XOR circuit XOR mutually with the output signal of said two-stage register, obtains final level signal.

3. according to the said circuit of claim 2, it is characterized in that: said register Q3 is the register of band Enable Pin.