CN110045782B - Data read-write synchronous circuit and data read-write method - Google Patents

Data read-write synchronous circuit and data read-write method Download PDF

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CN110045782B
CN110045782B CN201910211358.1A CN201910211358A CN110045782B CN 110045782 B CN110045782 B CN 110045782B CN 201910211358 A CN201910211358 A CN 201910211358A CN 110045782 B CN110045782 B CN 110045782B
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data
trigger
signal
clock
flip
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CN110045782A (en
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赵锋
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a data read-write synchronous circuit and a data read-write method, which are characterized in that a high REQ_T pulse signal is set for one TCLK clock signal period, so that a fifth D trigger outputs a high level signal; the high level signal outputs a REQ_R signal after being synchronized by the RCLK clock signal clock domain; the REQ_R signal is raised and the clock domain of the RCLK clock signal reads the data; after the clock domain of the RCLK clock signal finishes reading data, setting the ACK_R pulse signal high; the signal in the fifth D trigger is cleared, the ACK_T signal becomes low level, and the data reading and writing are completed. The control signal in the data read-write synchronous circuit is latched by the D trigger and the reset register, the data transmitting end sends out a request, and the receiving end is cleared, so that the data read-write synchronous circuit is particularly suitable for the data transmitting end to enter a latching mode, realizes no-waiting processing, avoids error data, and ensures reliable transmission of the data.

Description

Data read-write synchronous circuit and data read-write method
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a data read-write synchronization circuit and a data read-write method.
Background
In the field of digital circuit design, a data transmission scenario crossing clock domains often occurs, and data needs to be interacted in two or more clock domains. Because of the unavoidable transmission of data across clock domains in a multi-clock domain system, and because of the uncertainty in the relationship of the operational edges of their clocks between disparate clock domains, insufficient setup or hold time may occur when data is transmitted from one clock domain to another. When the setup time or the hold time is insufficient, metastable values are generated, and error data are generated, so that the whole system is in error.
Therefore, a new data read-write synchronization circuit needs to be proposed to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a data read-write synchronization circuit for solving the problem of metastable state of data transmission across clock domains in the prior art.
To achieve the above and other related objects, the present invention provides a data read-write synchronization circuit, at least comprising: first and second D flip-flops controlled by a TCLK clock signal; the data input end D of the first D trigger is connected with the Q output end of the second D trigger; third and fourth D flip-flops controlled by the RCLK clock signal; the Q output end of the third D trigger is connected with the data input end D of the fourth D trigger; the data input end D of the second D trigger is connected with the data input end D of the third D trigger; a fifth D flip-flop controlled by the req_t pulse signal, and a reset register controlled by the ack_r pulse signal; the Q output end of the fifth D trigger is connected with the data input ends D of the second D trigger and the third D trigger and the reset zero clearing end of the reset register; and the Q output end of the reset register is connected with the reset zero clearing end of the fifth D trigger.
Preferably, the TCLK clock signal is input to clock inputs of the first and second D flip-flops; the RCLK clock signal is input to the clock input of the third and fourth D flip-flops.
Preferably, the req_t pulse signal is input to a clock input terminal of the fifth D flip-flop; the ack_r pulse signal is input to a clock input terminal of the reset register.
Preferably, the TCLK clock signal and the RCLK clock signal are asynchronous clock signals of different clock domains.
Preferably, a buffer gate is arranged between the data input end D of the second and third D flip-flops and the reset zero clearing end of the reset register.
Preferably, the reset zero clearing end of the fifth D flip-flop is set to be valid at a high level, and the reset zero clearing end of the reset register is set to be valid at a low level.
Preferably, the data input terminal D of the fifth D flip-flop and the reset register is connected to the high level.
Preferably, after the data controlling the clock domains of the first and second D flip-flops are ready, the req_t pulse signal is set high for one TCLK clock signal period, so that the Q output terminal of the fifth D flip-flop outputs a high level signal.
Preferably, after the clock domains of the third and fourth D flip-flops are controlled to read data, the ack_r pulse signal with one clock length is set high for preparing for the next data transmission.
Preferably, a data transmitting end in the circuit is an MCU high-speed kernel bus, and a receiving end is a low-speed peripheral.
As described above, the data read-write synchronization circuit and the data read-write method of the present invention have the following beneficial effects: the control signal in the data read-write synchronous circuit is latched by the D trigger and the reset register, the data transmitting end sends out a request, and the receiving end is cleared, so that the data read-write synchronous circuit is particularly suitable for the data transmitting end to enter a latching mode, realizes no-waiting processing, avoids error data, and ensures reliable transmission of the data.
Drawings
Fig. 1 is a schematic diagram of a data read-write synchronization circuit according to the present invention.
Fig. 2 is a timing waveform diagram of signals in the data read-write synchronous circuit according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, fig. 1 is a schematic diagram of a data read-write synchronization circuit according to the present invention. The data read/write synchronization circuit of the present invention includes in this embodiment: first and second D flip-flops controlled by a TCLK clock signal; the data input end D of the first D trigger is connected with the Q output end of the second D trigger; third and fourth D flip-flops controlled by the RCLK clock signal; the Q output end of the third D trigger is connected with the data input end D of the fourth D trigger; the data input terminal D of the second D flip-flop is connected to the data input terminal D of the third D flip-flop. That is, the first D flip-flop 01 and the second D flip-flop 02 are controlled by the TCLK clock signal, and the TCLK clock signal is preferably input to the clock input terminals of the first D flip-flop 01 and the second D flip-flop 02. In this embodiment, the third D flip-flop 03 and the fourth D flip-flop 04 are controlled by the RCLK clock signal, and further, the RCLK clock signal is input to the clock input terminals of the third D flip-flop 03 and the fourth D flip-flop 04.
The connection relationship between the first D flip-flop 01 and the second D flip-flop 02 is: the data input D of the first D flip-flop 01 is connected to the Q output of the second D flip-flop 02.
Also, for the third D flip-flop and the fourth D flip-flop, the connection relationship between the third D flip-flop 03 and the fourth D flip-flop 04 is: the Q output of the third D flip-flop 03 is connected to the data input D of the fourth D flip-flop 04.
The data read-write synchronous circuit of the invention further comprises: a fifth D flip-flop T controlled by the req_t pulse signal, and a reset register R controlled by the ack_r pulse signal; referring to fig. 1, preferably, the req_t pulse signal is input to a clock input terminal of the fifth D flip-flop T; the ack_r pulse signal is input to the clock input terminal of the reset register R.
The reset register R of the invention is provided with a reset zero terminal CLR, and the Q output terminal of the fifth D trigger is connected with the data input terminals D of the second D trigger and the third D trigger and the reset zero terminal CLR of the reset register R. That is, since the data input terminal D of the second D flip-flop 02 and the data input terminal D of the third D flip-flop 03 are connected to each other, the Q output terminal of the fifth D flip-flop in the present invention is connected to a node between the data input terminal D of the second D flip-flop 02 and the data input terminal D of the third D flip-flop 03. Further, the data read-write synchronization circuit of this embodiment further includes a buffer gate M, as shown in fig. 1, where the buffer gate M is disposed between the data input ends D of the second and third D flip-flops and the reset clear end CLR of the reset register R, and the buffer gate M is output from the reset clear end CLR of the reset register R.
In the invention, the Q output end of the reset register R is connected with the reset zero clearing end CLR of the fifth D trigger T. Further, the TCLK clock signal and the RCLK clock signal are asynchronous clock signals of different clock domains. And preferably, the reset zero terminal of the fifth D flip-flop is set to be valid at a high level, the reset zero terminal of the reset register is set to be valid at a low level, and the data input terminals D of the fifth D flip-flop and the reset register are connected to be valid at a high level.
The working principle of the data read-write synchronous circuit of the invention is as follows: (referring to FIG. 2, FIG. 2 shows a timing waveform diagram of signals in the data read/write synchronization circuit of the present invention).
And the data input end D of the fifth D trigger T and the data input end D of the reset register R are connected with a high level 1, and when the data of the clock domains of the first D trigger 01 and the second D trigger 02 are controlled to be ready, the clock input end of the fifth D trigger T inputs a REQ_T pulse signal and sets the REQ_T pulse signal to be high for one TCLK clock signal period, so that the Q output end of the fifth D trigger outputs a high level signal. I.e. issues a request signal to cause the circuit in the right half to fetch data. The clock input ends of the third trigger and the fourth trigger in the right half part circuit are input with RCLK clock signals, and the input RCLK clock signals and the TCLK clock signals input by the clock input ends of the first trigger and the second trigger in the left half part circuit are asynchronous clock signals. The third D flip-flop and the fourth D flip-flop respectively receive signals from their respective data input terminals D and output signals via their respective Q output terminals, that is, the signals output by the fifth D flip-flop are output a req_r signal from the Q output terminal of the fourth D flip-flop through the third D flip-flop and the fourth D flip-flop (after being two-stage synchronized) under the control of the same clock domain, and the req_r signal is raised in the above state. Since the clock domains controlling the first and second D flip-flops and the clock domains controlling the third and fourth D flip-flops are asynchronous clock signals, the validity of the clock signals is different, and thus, in the above state, the signal transmission only considers the third and fourth D flip-flops under the control of the clock domain of the right half of the circuit (RCLK clock signal) transmitted from the fifth D flip-flop.
Thus, after the data controlling the first and second D flip-flop clock domains are ready, in the above state (the req_r signal is outputted after the signals are synchronized), the req_r signal is raised and the data is read under the TCLK clock signal controlling the clock domain of the right half of the circuit in fig. 2. When the data is read, the rising edge of the REQ_R signal is known to the next clock signal of the RCLK clock signal.
After the clock domain of the RCLK clock signal finishes reading the data, the ack_r pulse signal input to the clock input terminal of the reset register is set high (i.e. a receipt signal is generated), and is set high by one clock length. Because the Q output end in the reset register R is connected to the reset zero end of the fifth D flip-flop, at this time, the signals in the fifth D flip-flop are cleared, after two-stage TCLK clock signals are synchronized, the ack_t signal generated by the first and second D flip-flops becomes low level, that is, it is known that the data in the right half circuit is read, that is, the data transmission is completed, the next group of data can be read, and the next group of data is read, and the above steps are repeated. In this embodiment, preferably, the data transmitting end in the circuit is an MCU high-speed core bus, and the receiving end is a low-speed peripheral, so that the MCU core time can be saved.
The invention also discloses a data read-write method based on the data read-write synchronous circuit, which comprises the following steps:
step one, setting high REQ_T pulse signal for one TCLK clock signal period to make the fifth D trigger output high level signal; in this embodiment, the data to be transferred controlling the first and second D flip-flop clock domains is preferably prepared before performing step one. And the data input end D of the fifth D trigger T and the data input end D of the reset register R are connected with a high level 1, and when the data of the clock domains of the first D trigger 01 and the second D trigger 02 are controlled to be ready, the clock input end of the fifth D trigger T inputs a REQ_T pulse signal and sets the REQ_T pulse signal to be high for one TCLK clock signal period, so that the Q output end of the fifth D trigger outputs a high level signal.
Step two, the high level signal outputs a REQ_R signal after being subjected to clock domain synchronization by the RCLK clock signal; that is, after the Q output terminal of the fifth D flip-flop outputs the high level signal, the high level signal is synchronized through the third and fourth D flip-flops controlled by the RCLK clock signal clock domain, and the req_r signal is output.
Step three, raising a REQ_R signal, wherein a clock domain of the RCLK clock signal reads data; that is, the REQ_R signal output in the second step is raised to read data under the control of the TCLK clock signal.
Fourthly, after the clock domain of the RCLK clock signal finishes reading data, setting the ACK_R pulse signal to be high; when the data is read, the rising edge of the REQ_R signal is known to the next clock signal of the RCLK clock signal. In this embodiment, preferably, after the clock domains of the third and fourth D flip-flops are controlled to read data, the ack_r pulse signal with one clock length is set higher in the fourth step for preparing for the next data transmission.
And step five, the signal in the fifth D trigger is cleared, and the ACK_T signal becomes low level. Because the Q output end in the reset register R is connected to the reset zero end of the fifth D flip-flop, at this time, the signal in the fifth D flip-flop is cleared, after the two-stage TCLK clock signal is synchronized, the ack_t signal generated by the first and second D flip-flops becomes low level, so that it is known that the data in the right half circuit is read, that is, the data transmission is completed, and the next group of data can be read.
In summary, the control signal in the data read-write synchronous circuit is latched by the D trigger and the reset register, the data transmitting end sends a request, and the receiving end clears, so that the data read-write synchronous circuit is particularly suitable for the data transmitting end to enter a latching mode, realizes no waiting processing, avoids error data, and ensures reliable transmission of the data. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (8)

1. A data read-write synchronization circuit, comprising at least:
first and second D flip-flops controlled by a TCLK clock signal; the data input end D of the first D trigger is connected with the Q output end of the second D trigger;
third and fourth D flip-flops controlled by the RCLK clock signal; the Q output end of the third D trigger is connected with the data input end D of the fourth D trigger; the data input end D of the second D trigger is connected with the data input end D of the third D trigger;
the TCLK clock signal is input to the clock input ends of the first D trigger and the second D trigger; the RCLK clock signal is input to the clock input ends of the third and fourth D flip-flops;
the TCLK clock signal and the RCLK clock signal are asynchronous clock signals of different clock domains;
a fifth D flip-flop controlled by the req_t pulse signal, and a reset register controlled by the ack_r pulse signal; the Q output end of the fifth D trigger is connected with the data input ends D of the second D trigger and the third D trigger and the reset zero clearing end of the reset register; the Q output end of the reset register is connected with the reset zero clearing end of the fifth D trigger; the REQ_T pulse signal is input to the clock input end of the fifth D trigger; the ack_r pulse signal is input to a clock input terminal of the reset register.
2. The data read-write synchronization circuit according to claim 1, wherein: and a buffer gate is arranged between the data input end D of the second trigger and the data input end D of the third trigger and the reset zero clearing end of the reset register.
3. The data read-write synchronization circuit according to claim 2, wherein: and a reset zero clearing end of the fifth D trigger is provided with a high level effective, and a reset zero clearing end of the reset register is provided with a low level effective.
4. A data read-write synchronization circuit according to claim 3, wherein: and the data input end D of the fifth D trigger and the reset register is connected with a high level.
5. The data read-write synchronization circuit according to claim 4, wherein: the data transmitting end in the circuit is an MCU high-speed kernel bus, and the receiving end is a low-speed peripheral.
6. The method for data read/write synchronization circuit according to claim 5, comprising at least the steps of:
step one, setting high REQ_T pulse signal for one TCLK clock signal period to make the fifth D trigger output high level signal;
step two, the high level signal outputs a REQ_R signal after being subjected to clock domain synchronization by the RCLK clock signal;
step three, raising a REQ_R signal, wherein a clock domain of the RCLK clock signal reads data;
step four, after the clock domain of the RCLK clock signal finishes reading data, setting the ACK_R pulse signal to be one clock length higher;
and step five, the signal in the fifth D trigger is cleared, and the ACK_T signal becomes low level.
7. The data reading and writing method according to claim 6, wherein: the method further comprises preparing data to be transferred controlling the first and second D flip-flop clock domains before performing step one.
8. The data reading and writing method according to claim 7, wherein: and after the clock domains of the third D trigger and the fourth D trigger are controlled to read data, an ACK_R pulse signal with one clock length higher in the fourth step is arranged for preparing the next data transmission.
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CN112968698A (en) * 2021-01-29 2021-06-15 北京博雅慧视智能技术研究院有限公司 Asynchronous zero clearing circuit and method
CN113009961B (en) * 2021-02-26 2023-03-24 山东英信计算机技术有限公司 Cross-clock synchronous circuit and SoC system
CN114117972B (en) * 2022-01-26 2022-06-10 之江实验室 Synchronous device and method of asynchronous circuit

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