CN112968698A - Asynchronous zero clearing circuit and method - Google Patents
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Abstract
The application discloses an asynchronous zero clearing circuit and method, comprising: a state output circuit and a state zero clearing circuit; the state output circuit is used for clearing the register and the first register in the first register sub-circuit according to the clear signal sent by the state clear circuit and outputting the clear signal to the state clear circuit; the state zero clearing circuit is used for outputting the received zero clearing signal to the state output circuit according to the received write enable signal and the zero clearing signal; and clearing the register, the second register and the third register in the second register sub-circuit according to the received clear signal sent by the state output circuit. The state of all registers in different clock thresholds in the whole circuit can be directly cleared under the condition that the state clearing circuit only sends the write enable signal once, so that the method is simple, convenient and quick, and can be widely applied to modules which are interacted in various different clock domains.
Description
Technical Field
The present application relates to the field of circuit technologies, and in particular, to an asynchronous zero clearing circuit and method.
Background
A common problem in chip design is that control information or status information needs to be exchanged between function modules running in different clock domains through register access, and taking an MCU and a hardware accelerator as an example, the MCU needs to control the hardware accelerator and query its status through register access. A typical scenario of the interaction between the MCU and the hardware accelerator is that after the hardware accelerator processes a task, a done signal is transmitted to the MCU, the done signal exists in a register, and the MCU performs a series of actions after obtaining the done signal sent by the hardware accelerator, such as reading a result and issuing a new task. However, the MCU and the hardware accelerator are often in different clock domains, and the information exchanged between them through the registers will pass through a series of synchronous circuits, and how to clean and efficiently clear the done signal sent by the hardware accelerator and clear the states of the synchronous circuits on all links by the MCU is a great challenge.
In summary, it is desirable to provide an asynchronous clear circuit and method that can be used for modules in different clock domains to interact and clear easily.
Disclosure of Invention
In order to solve the above problems, the present application provides an asynchronous zero clearing circuit and method.
In one aspect, the present application provides an asynchronous zero clearing circuit, including: a state output circuit and a state zero clearing circuit;
the state output circuit is used for clearing the register and the first register in the first register sub-circuit according to the clear signal sent by the state clear circuit and outputting the clear signal to the state clear circuit;
the state zero clearing circuit is used for outputting the received zero clearing signal to the state output circuit according to the received write enable signal and the zero clearing signal; and clearing the register, the second register and the third register in the second register sub-circuit according to the received clear signal sent by the state output circuit.
Preferably, the state output circuit includes: the first register sub-circuit, the first register, the first AND gate and the OR gate;
a first input end of the OR gate inputs an end signal, a second input end of the OR gate is connected with an output end of the first AND gate, and an output end of the OR gate is connected with a signal input end of the first register;
the non-inverting input end of the first AND gate is connected with the output end of the first register and the state zero clearing circuit, and the inverting input end of the first AND gate is connected with the output end of the first register sub-circuit;
the signal output end of the first register is connected with the state zero clearing circuit;
the signal input end of the first register sub-circuit is connected with the state zero clearing circuit;
clock signal input ends of all registers in the first register sub-circuit and clock signal input ends of the first registers input first clock signals; and the output end of the first register outputs an end signal of which the clock domain is the first clock.
Preferably, the state clearing circuit includes: the second register sub-circuit, the second register, the third register, the second AND gate, the third AND gate and the multi-channel gate;
the non-inverting input end of a third AND gate is connected with the output end of the second register, the inverting input end of the third AND gate is connected with the output end of the first register and the signal input end of the second register, and the output end of the third AND gate is connected with the inverting input end of the second AND gate;
the signal input end of the second register sub-circuit is connected with the output end of the first register;
the non-inverting input end of the second AND gate is connected with the output end of the third register and the signal input end of the first register sub-circuit, and the output end of the second AND gate is connected with the first input end of the multi-way gate;
a second input end of the multi-path gate inputs a zero clearing signal, a control end inputs a write enable signal, and an output end of the multi-path gate is connected with a signal input end of the third register;
the clock signal input ends of all registers in the second register, the third register and the second register sub-circuit input second clock signals; and the output end of the second register outputs an end signal of which the clock domain is the second clock.
Preferably, the first register sub-circuit comprises: a fourth register and a fifth register;
a signal input end of the fourth register is used as a signal input end of the first register sub-circuit, and an output end of the fifth register is used as an output end of the first register sub-circuit;
the signal input end of the fourth register is connected with the output end of the third register, and the output end of the fourth register is connected with the signal input end of the fifth register;
and the output end of the fifth register is connected with the inverted input end of the first AND gate.
Preferably, the second register sub-circuit comprises: a sixth register and a seventh register;
a signal input end of the sixth register is used as a signal input end of the second register sub-circuit, and an output end of the seventh register is used as an output end of the second register sub-circuit;
the signal input end of the sixth register is connected with the output end of the first register, and the output end of the sixth register is connected with the signal input end of the seventh register;
and the output end of the seventh register is connected with the signal input end of the second register and the inverted input end of the third AND gate.
Preferably, the state output circuit is further configured to receive an end signal, and output the end signal of which the clock domain is the first clock to the state clearing circuit.
In a second aspect, the present application provides an asynchronous clearing method, including:
the state zero clearing circuit outputs the received zero clearing signal to the state output circuit according to the received write enable signal and the zero clearing signal;
the state output circuit clears the register and the first register in the first register sub-circuit according to the clear signal and outputs the clear signal to the state clear circuit;
and the state zero clearing circuit clears the register, the second register and the third register in the second register sub-circuit according to the received zero clearing signal sent by the state output circuit.
Preferably, before the receiving the write enable signal and the clear signal, the method further includes:
the second register output clock domain in the state clearing circuit is the end signal of the second clock.
Preferably, before the state clearing circuit outputs the received clear signal to the state output circuit according to the write enable signal and the clear signal of the clear signal, the method further includes:
the state output circuit receives the end signal and outputs the end signal of which the clock domain is the first clock to the state clear circuit.
The application has the advantages that: the state zero clearing circuit can output the received zero clearing signal to the state output circuit according to the received write enable signal and the zero clearing signal; the state output circuit can directly clear the register and the first register in the first register sub-circuit according to the clear signal sent by the state clear circuit and output the clear signal to the state clear circuit; the state zero clearing circuit clears the register, the second register and the third register in the second register sub-circuit according to the received zero clearing signal sent by the state output circuit, so that the states of all registers in different clock thresholds in the whole circuit are directly cleared under the condition that the state zero clearing circuit only sends the write enable signal once, and the state zero clearing circuit is simple, convenient and quick.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to denote like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of an asynchronous zero clearing circuit provided herein;
FIG. 2 is a schematic connection diagram of an asynchronous clearing circuit provided in the present application;
FIG. 3 is a clock schematic diagram of an asynchronous clearing circuit provided herein;
fig. 4 is a schematic step diagram of an asynchronous clearing method provided in the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In a first aspect, according to an embodiment of the present application, an asynchronous clear circuit is provided, as shown in fig. 1, including: a state output circuit 100 and a state clear circuit 200. The state output circuit 100 is configured to clear the register in the first register sub-circuit 110 and the first register 10 according to the clear signal clr sent by the state clear circuit 200, and output the clear signal to the state clear circuit 200. The state clearing circuit 200 is configured to output the received clear signal clr to the state output circuit 100 according to the received write enable signal wr _ enable and clear signal clr; the registers in the second register sub-circuit 210, the second register 20, and the third register 30 are cleared according to the received clear signal clr transmitted from the state output circuit 100.
As shown in fig. 2, the state output circuit 100 includes: a first register sub-circuit 110, a first register 10, a first and gate G1, and an or gate G4. The first input terminal 1 of the or gate G4 receives the done signal done, the second input terminal 2 is connected to the output terminal of the first and gate G1, and the output terminal of the or gate G4 is connected to the signal input terminal of the first register 10. The non-inverting input terminal of the first and gate G1 is connected to the output terminal of the first register 10 and the state clearing circuit 200, and the inverting input terminal of the first and gate G1 is connected to the output terminal of the first register sub-circuit 110. The signal output terminal of the first register 10 is connected to the status clearing circuit 200. The signal input terminal of the first register sub-circuit 110 is connected to the status clearing circuit 200. The clock signal input terminals CK of all registers in the first register sub-circuit 110 and the clock signal input terminal CK of the first register 10 input the first clock signal aclk; the output of the first register 10 outputs an end signal done whose clock domain is the first clock.
The state output circuit 100 is further configured to receive an end signal done, and output the end signal done with the clock domain as the first clock to the state clear circuit 200.
The state clearing circuit 200 includes: a second register sub-circuit 210, a second register 20, a third register 30, a second and gate G2, a third and gate G3, and a multiplexer 220. The non-inverting input of the third and gate G3 is connected to the output of the second register 20, the inverting input of the third and gate G3 is connected to the output of the first register 10 and to the signal input of the second register 20, and the output of the third and gate G3 is connected to the inverting input of the second and gate G2. The signal input of the second register sub-circuit 210 is connected to the output of the first register 10. The non-inverting input of the second and gate G2 is connected to the output of the third register 30 and to the signal input of the first register sub-circuit 110, and the output of the second and gate G2 is connected to the first input of the multiplexer 220. The second input terminal of the multiplexer 220 inputs the clear signal clr, the control terminal inputs the write enable signal wr _ enable, and the output terminal is connected to the signal input terminal of the third register 30. The clock signal input terminals CK of all the registers in the second register 20, the third register 30 and the second register sub-circuit 210 all input the second clock signal pclk; the output of the second register 20 outputs an end signal done whose clock domain is the second clock.
A first register sub-circuit 110 comprising: a fourth register 40 and a fifth register 50. The signal input of the fourth register 40 serves as the signal input of the first register sub-circuit 110 and the output of the fifth register 50 serves as the output of the first register sub-circuit 110. A signal input of the fourth register 40 is connected to an output of the third register 30 and an output of the fourth register 40 is connected to a signal input of the fifth register 50. The output of the fifth register 50 is connected to the inverting input of the first and gate G1.
A second register sub-circuit 210, comprising: a sixth register 60 and a seventh register 70. The signal input of the sixth register 60 serves as the signal input of the second register sub-circuit 210, and the output of the seventh register 70 serves as the output of the second register sub-circuit 210. A signal input of the sixth register 60 is connected to an output of the first register 10 and an output of the sixth register 60 is connected to a signal input of the seventh register 70. An output of the seventh register 70 is connected to a signal input of the second register 20 and to an inverting input of the third and gate G3.
In the following, further description is made on the embodiments of the present application, it is assumed that the a block is connected to the state output circuit 100, the P block is connected to the state zero clearing circuit 200, and all initial values of the registers are zero.
The end signal done works in the aclk clock domain and is a signal which is output by the A module and is pulled up for one aclk period and then returns to 0. The clock domain aclk is a first clock aclk for driving the a module. The write enable signal wr _ enable is a signal to pull up the P-block output for one pclk cycle and then back to 0. The clear signal clr is a clear signal clk output by the P module, and the clear signal clr and the write enable signal wr _ enable are pulled up by one pclk cycle in the same cycle and then return to 0. The clock domain pclk is a second clock pclk driving the P-module. The done signal done _ sync is a signal synchronized to the pclk clock domain by the done signal done, and is continuously pulled up until the clear signal clr sent by the P module is cleared. The P module may be an MCU, and the a module may be a hardware accelerator.
As shown in fig. 3, after the module a completes the task, an end signal done lasting for one beat of aclk period is sent to notify the module P that the current task is ended. done to the state output circuit 100. The end signal done is latched by the first register 10 and maintains a high state. The sixth register 60, the seventh register 70 and the second register 20 in the second register sub-circuit 210 of the ending signal done pclk clock domain output by the first register 10 are synchronized and then output a done signal done _ sync with a time domain of pclk, and the done signal done _ sync maintains a high level state and conveniently runs in a P module collection of the pclk clock domain. The P-module collects the done signal done _ sync and performs other necessary operations such as retrieving the result and configuring the next task. Then, the P-block pulls up the write enable signal wr _ enable and the clear signal clr, and keeps a pclk cycle (this is a relatively typical bus access behavior), so that the multiplexer 220 outputs the clear signal clr to the third register 30, and the clear signal clr is stored in the third register 30 of the pclk clock domain and keeps a high level state. The high level (clear signal clr) of the third register 30 is synchronized to the aclk clock domain by the fourth register 40 and the fifth register 50 in the first register sub-circuit 110 of the aclk clock domain. The first register 10 of the aclk clock domain originally maintains a high level, and after the high level of the fifth register 50 propagates, the value of the first register 10 is cleared. The zero of the first register 10 is taken as a clear signal by the sixth register 60, the seventh register 70 and the second register 20 of the pclk clock domain, on one hand, the high level of the done signal done _ sync is cleared, and on the other hand, a high level pulse lasting one pclk period is generated to clear the third register 30. In the whole process, registers on all links in the circuit are cleared, the P module only performs one operation of writing the third register 30 (one beat by pulling up the write enable signal wr _ enable and the clear signal clr) for clearing all the registers, convenience and simplicity are realized, and no assumption is made on the period between the clock threshold aclk and the clock threshold pclk. As shown in fig. 3, the done signal done is correctly switched to the pclk clock domain, and after the done signal done _ sync is pulled high, the clear signal clr and the write enable signal wr _ enable are pulled high by the P module only for one beat, and finally all registers in the circuit are cleared.
In a second aspect, according to an embodiment of the present application, an asynchronous zeroing method is further provided, as shown in fig. 4, including:
s101, the state clear circuit outputs the received clear signal to the state output circuit according to the received write enable signal and the clear signal;
s102, the state output circuit clears the register and the first register in the first register sub-circuit according to the clear signal and outputs the clear signal to the state clear circuit;
and S103, clearing the register, the second register and the third register in the second register sub-circuit by the state clearing circuit according to the received clearing signal sent by the state output circuit.
Before the write enable signal and the clear signal are received, the method further comprises the following steps: the second register output clock domain in the state clearing circuit is the end signal of the second clock.
Before the state clear circuit outputs the received clear signal to the state output circuit according to the write enable signal and the clear signal, the method further comprises the following steps: the state output circuit receives the end signal and outputs an end signal of which the clock domain is the first clock to the state clear circuit.
In the method, the state zero clearing circuit can output the received zero clearing signal to the state output circuit according to the received write enable signal and the zero clearing signal; the state output circuit can directly clear the register and the first register in the first register sub-circuit according to the clear signal sent by the state clear circuit and output the clear signal to the state clear circuit; the state zero clearing circuit clears the register, the second register and the third register in the second register sub-circuit according to the received zero clearing signal sent by the state output circuit, so that the state of all registers in different clock thresholds in the whole circuit is directly cleared under the condition that the state zero clearing circuit only sends the write enable signal once, the circuit is simple, convenient and quick, can be widely applied to modules which interact in various different clock domains, and can enable the MCU to normally work no matter the MCU is in a fast clock domain or a slow clock domain when being applied to the MCU and a hardware accelerator.
The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. An asynchronous clear circuit, comprising: a state output circuit and a state zero clearing circuit;
the state output circuit is used for clearing the register and the first register in the first register sub-circuit according to the clear signal sent by the state clear circuit and outputting the clear signal to the state clear circuit;
the state zero clearing circuit is used for outputting the received zero clearing signal to the state output circuit according to the received write enable signal and the zero clearing signal; and clearing the register, the second register and the third register in the second register sub-circuit according to the received clear signal sent by the state output circuit.
2. The asynchronously clearing circuit of claim 1 wherein the state output circuit comprises: the first register sub-circuit, the first register, the first AND gate and the OR gate;
a first input end of the OR gate inputs an end signal, a second input end of the OR gate is connected with an output end of the first AND gate, and an output end of the OR gate is connected with a signal input end of the first register;
the non-inverting input end of the first AND gate is connected with the output end of the first register and the state zero clearing circuit, and the inverting input end of the first AND gate is connected with the output end of the first register sub-circuit;
the signal output end of the first register is connected with the state zero clearing circuit;
the signal input end of the first register sub-circuit is connected with the state zero clearing circuit;
clock signal input ends of all registers in the first register sub-circuit and clock signal input ends of the first registers input first clock signals; and the output end of the first register outputs an end signal of which the clock domain is the first clock.
3. The asynchronous clear circuit according to claim 2, wherein the state clear circuit comprises: the second register sub-circuit, the second register, the third register, the second AND gate, the third AND gate and the multi-channel gate;
the non-inverting input end of a third AND gate is connected with the output end of the second register, the inverting input end of the third AND gate is connected with the output end of the first register and the signal input end of the second register, and the output end of the third AND gate is connected with the inverting input end of the second AND gate;
the signal input end of the second register sub-circuit is connected with the output end of the first register;
the non-inverting input end of the second AND gate is connected with the output end of the third register and the signal input end of the first register sub-circuit, and the output end of the second AND gate is connected with the first input end of the multi-way gate;
a second input end of the multi-path gate inputs a zero clearing signal, a control end inputs a write enable signal, and an output end of the multi-path gate is connected with a signal input end of the third register;
the clock signal input ends of all registers in the second register, the third register and the second register sub-circuit input second clock signals; and the output end of the second register outputs an end signal of which the clock domain is the second clock.
4. The asynchronously clearing circuit of claim 2 wherein the first register subcircuit comprises: a fourth register and a fifth register;
a signal input end of the fourth register is used as a signal input end of the first register sub-circuit, and an output end of the fifth register is used as an output end of the first register sub-circuit;
the signal input end of the fourth register is connected with the output end of the third register, and the output end of the fourth register is connected with the signal input end of the fifth register;
and the output end of the fifth register is connected with the inverted input end of the first AND gate.
5. The asynchronously clearing circuit of claim 3 wherein the second register subcircuit comprises: a sixth register and a seventh register;
a signal input end of the sixth register is used as a signal input end of the second register sub-circuit, and an output end of the seventh register is used as an output end of the second register sub-circuit;
the signal input end of the sixth register is connected with the output end of the first register, and the output end of the sixth register is connected with the signal input end of the seventh register;
and the output end of the seventh register is connected with the signal input end of the second register and the inverted input end of the third AND gate.
6. The asynchronously clearing circuit of claim 1 wherein the state output circuit is further configured to receive an end signal and output the end signal having a clock domain of the first clock to the state clearing circuit.
7. An asynchronous zeroing method, comprising:
the state zero clearing circuit outputs the received zero clearing signal to the state output circuit according to the received write enable signal and the zero clearing signal;
the state output circuit clears the register and the first register in the first register sub-circuit according to the clear signal and outputs the clear signal to the state clear circuit;
and the state zero clearing circuit clears the register, the second register and the third register in the second register sub-circuit according to the received zero clearing signal sent by the state output circuit.
8. The asynchronous zeroing method of claim 7, further comprising, before the receiving a write enable signal and a zeroing signal:
the second register output clock domain in the state clearing circuit is the end signal of the second clock.
9. The asynchronous clear method according to claim 7, wherein before the state clear circuit outputs the received clear signal to the state output circuit according to the write enable signal and the clear signal, further comprising:
the state output circuit receives the end signal and outputs the end signal of which the clock domain is the first clock to the state clear circuit.
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| CN104348465A (en) * | 2013-07-26 | 2015-02-11 | 华为技术有限公司 | Control method and control circuit |
| CN108241584A (en) * | 2016-12-23 | 2018-07-03 | 德克萨斯仪器股份有限公司 | For integrated circuit, method and the interface circuit of the synchronous data transmission at a high speed between low-speed clock domain |
| CN110045782A (en) * | 2019-03-20 | 2019-07-23 | 上海华虹宏力半导体制造有限公司 | A kind of reading and writing data synchronous circuit and data read-write method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH04280135A (en) * | 1989-12-29 | 1992-10-06 | Samsung Electron Co Ltd | Synchronous protective circuit of pcm decoder |
| US8219844B1 (en) * | 2009-08-03 | 2012-07-10 | Altera Corporation | Methods and systems for emulating a synchronous clear port |
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