CN106814231B - A kind of high capture rate method of number - Google Patents

A kind of high capture rate method of number Download PDF

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Publication number
CN106814231B
CN106814231B CN201510869750.7A CN201510869750A CN106814231B CN 106814231 B CN106814231 B CN 106814231B CN 201510869750 A CN201510869750 A CN 201510869750A CN 106814231 B CN106814231 B CN 106814231B
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sampled point
home address
data stream
value
address
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CN106814231A (en
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林桐
刘家玮
胡志臣
储艳莉
黄月芳
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Beijing Aerospace Measurement and Control Technology Co Ltd
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Beijing Aerospace Measurement and Control Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/029—Software therefor

Abstract

The invention discloses a kind of high capture rate methods of number, comprising: by the converting serial data streams of the digital signal of acquisition be parallel data stream；By the value parallel memorizing of X sampled point in each clock cycle of parallel data stream in the corresponding X storage units independently read and write of three-dimensional waveform memory space.The present invention effectively improves waveform capture rate, solves the problem of reduction due to the timing margins of signal, shake, asynchronous failure and transient affair become difficult to discovery.

Description

A kind of high capture rate method of number
Technical field
The present invention relates to digital technologies, more particularly to a kind of high capture rate method of number.
Background technique
Digital three-dimensional oscillograph is that one kind can not only capture and show m- amplitude (event) information, Er Qieneng when signal Enough digital storage oscilloscopes that event probability of occurrence is shown with different luminance or color grade.It has digital storage oscilloscope Various advantages, while it can also generate display effect similar to the change that changes gradually of brightness of analog oscilloscope in digital form Learn fluorescent effect.
With the continuous improvement of system clock frequency, sharply reduce the timing margins of signal, shake, asynchronous failure and wink State problem becomes prominent and is difficult to find.If waveform capture rate deficiency will make most temporal events in waving map that can not send out Existing, signal jitter analysis, eye Diagram Analysis are not known where to begin more.
Summary of the invention
In view of the defect of the prior art, it is an object of that present invention to provide a kind of high capture rate methods of number, to improve wave Shape capture rate.
The object of the invention is mainly achieved through the following technical solutions:
The present invention provides a kind of high capture rate method of number, comprising:
It is parallel data stream by the converting serial data streams of the digital signal of acquisition；
By the value parallel memorizing of X sampled point in each clock cycle of parallel data stream in three-dimensional waveform memory space The storage units independently read and write of corresponding X.
Further, the method also includes:
Using the value of each sampled point as the home address of corresponding storage unit；
By the home address cumulative 2NFinal address as the corresponding storage unit of each sampled point；Wherein, N is number The resolution ratio of the analog-to-digital conversion module of word three-dimensional oscilloscope.
Further, the method specifically includes:
Number of sampling points K to be shown is needed according to the screen of digital three-dimensional oscillograph, determines the clock cycle for needing to store Number M；
Determine trigger position；
Judge whether the parallel data stream for being filled with M period, if not being filled with, using the value of each sampled point as corresponding The home address of storage unit；By the home address cumulative 2NFinally as the corresponding storage unit of each sampled point Location；
If being filled with, parallel data stream is moved to right according to the trigger position, using the value of each sampled point after displacement as The home address of storage unit adds 1 to be written back the home address, by the home address after reading the value of the home address Cumulative 2NFinal address as the corresponding storage unit of each sampled point.
Further, the data of trigger position are moved to the last one position of X dimension group, to guarantee trigger position Data are located at the same position in K sampled point.
Further, the number M=(K/X)+1 of clock cycle.
The present invention has the beneficial effect that: the present invention effectively improves waveform capture rate, solves the timing margins due to signal Reduction, the problem of shake, asynchronous failure and transient affair become difficult to discovery.
Detailed description of the invention
Fig. 1 is the functional block diagram of digital three-dimensional oscillograph in the embodiment of the present invention；
Fig. 2 is the corresponding storage unit signal for storing the sampled point of each clock cycle in the embodiment of the present invention and needing Figure.
Specific embodiment
Waveform capture rate has become one of the key index of evaluation waving map performance.If waveform capture rate deficiency will make Most temporal events can not find that signal jitter analysis, eye Diagram Analysis are not known where to begin more in waving map, be based on this, the present invention A kind of high capture rate method of number is provided, below in conjunction with attached drawing and embodiment, the present invention will be described in further detail. It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, the present invention is not limited.
The embodiment of the present invention provides a kind of high capture rate method of number, and this method carries out parallel three to high-speed parallel data stream Information Statistics are tieed up, and all in FPGA (Field-Programmable Gate Array, i.e. field programmable gate array) It realizes in portion, comprising:
The converting serial data streams of the digital signal of acquisition are parallel data stream by S101；
S102 deposits the value parallel memorizing of X sampled point in each clock cycle of parallel data stream in three-dimensional waveform Store up the corresponding X storage units independently read and write in space.
S103, using the value of each sampled point as the home address of corresponding storage unit；The home address is added up 2NFinal address as the corresponding storage unit of each sampled point；Wherein, N is the analog-to-digital conversion module of digital three-dimensional oscillograph Resolution ratio.
Wherein, S103 is specifically included:
Number of sampling points K to be shown is needed according to the screen of digital three-dimensional oscillograph, determines the clock cycle for needing to store Number M；
Determine trigger position；
Judge whether the parallel data stream for being filled with M period, if not being filled with, execute using the value of each sampled point as pair The home address for the storage unit answered；By the home address cumulative 2NAs the final of the corresponding storage unit of each sampled point Address；
If being filled with, parallel data stream is moved to right according to the trigger position, using the value of each sampled point after displacement as The home address of storage unit adds 1 to be written back the home address, executes the inside after reading the value of the home address Address cumulative 2NFinal address as the corresponding storage unit of each sampled point.
Sketch the realization principle of present invention method.
As shown in Figure 1, analog signal becomes digital signal after ADC (analog-to-digital conversion module) conversion, digital signal is sent Serioparallel exchange is done after entering FPGA, becomes parallel data stream, under digital dock, each cycle there are several sampled points to need Statistics Division Reason, the method difficult point that the high capture rate of number is realized mainly have two aspects, and one is that data are high-speed parallel data stream, need to locate parallel Reason is to guarantee higher capture rate, the other is the reasonable utilization to memory space.
Assuming that each period obtains X sampled point under digital dock, one acquisition needs K sampled point, needs to acquire K/ X clock cycle realizes that the first step of the high capture rate of number is X sampled point of each cycle parallel memorizing, the clock cycle of storage Number M=(K/X)+1 (more clock cycle are adjusted for trigger position), needing memory space is K+X.
Assuming that it is m that trigger position, which is located at the position in X sampled point, do not shaken to guarantee that trigger position is stablized, need by The data of trigger position are moved to the last one position of X dimension group, to guarantee that the data of trigger position are located at K sampled point In the same position.To realize high capture rate, reduce processing time and memory space, parallel data stream read after directly into Row shifting function is then fed into three-dimensional waveform statistical module, no longer stores in this step.
Assuming that the resolution ratio of ADC is N, then screen shares 2NK pixel, each pixel are counted with 16bit, table Show different brightness.The size of memory space is 2NK 16bit.Collected each sampled point, may map to three-dimensional waveform In some storage unit of memory space.When the sampled point of waveform is related to certain storage unit, read in the storage unit Numerical value writes back after adding one.To guarantee high capture rate, X sampled point of parallel processing is also needed, needs to resolve into memory space The X memory blocks that can independently read and write, the size of each memory block is 2N K 16/Xbit.Convenient for engineering practice, by sampled point It is worth the home address 0 to 2 as memory spaceN- 1, the complete X sampled point of the every parallel processing of external address cumulative 2N.Therefore, waveform Often inswept place, luminance information can be accumulated step by step in storage unit, i.e., data carry the probabilistic information that waveform occurs, that Waveform shows the effect of light and shade naturally.
Specifically as shown in Figure 2:
1 sampled point of parallel processing 40,40 be above-mentioned X, so needing 40 independent memory spaces.
The value of 2 this 40 sampled points may be some value among 0 to 255, such as the 1st sampling in 40 sampled points The value of point is 80, just using 80 as the address of first piece of storage space S RAM0；The value of the 2nd sampled point is in 40 sampled points 90, just using 90 as the address of second piece of storage space S RAM1；The value of the 40th sampled point is 100 in 40 sampled points, just 100 address as second piece of storage space S RAM39.
After this complete 40 sampled points of 3 parallel processings, next 40 points are continued with, memory space remains this 40 pieces SRAM, 0~255 storage address have given 40 points of first time to use, next will with 256~511 address, i.e., it is whole The value that body address increases the 1st sampled point in 256, such as such as 40 sampled points is 80, is just deposited using 80+256 as first piece Store up the address of space S RAM0；The value of the 2nd sampled point is 90 in 40 sampled points, just empty using 90+256 as second piece of storage Between SRAM1 address；The value of the 40th sampled point is 100 in 40 sampled points, just using 100+256 as second piece of memory space The address of SRAM39.
With a specific example application, the summary present invention.
The ADC of one 5GHz sample rate is sampled (each sampled point 8) to an analog signal, and sampled data is sent Enter FPGA processing, FPGA cannot directly be handled with the clock of 5GHz, therefore data flow dredging collateral low-voltage differential module reduction of speed is arrived It is handled under 250M clock, obtains the high-speed parallel data stream of 20 sampled points of each cycle (160).Screen needs to show 1000 Sampled point then needs the data of 51 periods (20 sampled points of each cycle) of parallel memorizing.
After being filled with 51 cycle datas, data are read, according to trigger position directly by data shift right, to guarantee each Trigger position the 25th cycle data lowest order, achieve the purpose that trigger nil shake.
Home address of the value of each sampled point of data after displacement as storage unit, after reading the numerical value in the address 1 is added to be written back the address.Every external address cumulative 256 after having handled 20 parallel sampled points.Home address is plus externally Location is final memory unit address.
Although for illustrative purposes, the preferred embodiment of the present invention has been disclosed above, but those skilled in the art will Recognize it is various improve, increase and replace be also it is possible, therefore, the scope of the present invention should be not limited to the above embodiments.

Claims (3)

1. a kind of high capture rate method of number characterized by comprising
It is parallel data stream by the converting serial data streams of the digital signal of acquisition；
By the value parallel memorizing of X sampled point in each clock cycle of parallel data stream in pair of three-dimensional waveform memory space The X storage units independently read and write answered；
The method also includes:
Number of sampling points K to be shown is needed according to the screen of digital three-dimensional oscillograph, determines for the clock cycle for needing to store Number M；
Determine trigger position；
Judge whether the parallel data stream for being filled with M period, if not being filled with, using the value of each sampled point as corresponding storage The home address of unit；By the home address cumulative 2NFinal address as the corresponding storage unit of each sampled point；
If being filled with, parallel data stream is moved to right according to the trigger position, using the value of each sampled point after displacement as storage The home address of unit adds 1 to be written back the home address, the home address is added up after reading the value of the home address 2NFinal address as the corresponding storage unit of each sampled point；
Wherein, N is the resolution ratio of the analog-to-digital conversion module of digital three-dimensional oscillograph.
2. the method as described in claim 1, which is characterized in that the data of trigger position are moved to last of X dimension group A position, to guarantee that the data of trigger position are located at the same position in K sampled point.
3. the method as described in claim 1, which is characterized in that the number M=(K/X)+1 of clock cycle.
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CN109001514B (en) * 2018-06-21 2020-07-17 电子科技大学 Parameter measuring and marking method based on three-dimensional waveform mapping image
CN109062538B (en) * 2018-07-10 2020-11-20 豪威科技(上海)有限公司 Circular first-in first-out buffer and data transmission interface, system and method

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