CN100570373C - A Digital Storage Oscilloscope with High Waveform Capture Rate - Google Patents

Abstract

The invention discloses a digital storage oscilloscope with extremely high waveform capture rate, wherein an input test signal is conditioned and then sent to an ADC (analog to digital converter) conversion module for sampling, and is sent to an acquisition memory for caching under the control of a trigger and a time-base circuit; after the waveform acquisition is completed for one time, the data acquired by the parallel coprocessor is mapped into waveform lattice data corresponding to the display screen lattice, and a new round of acquisition and mapping is restarted after the mapping is completed; and meanwhile, the microprocessor carries out management work, immediately starts a display refreshing control logic when the timing refreshing time of the display screen is reached, automatically combines the waveform dot matrix data and the dot matrix data in the display memory, and updates the display of the display screen. The invention adopts a framework of signal waveform acquisition processing and microprocessor parallel work, so that the microprocessor is separated from heavy waveform processing and display, the dead zone time is reduced, the waveform capture rate is improved, the probability of finding transient abnormal signals is increased, and the test efficiency is improved.

Description

A Digital Storage Oscilloscope with High Waveform Capture Rate

technical field

The invention relates to a digital storage oscilloscope, in particular to a digital storage oscilloscope with a very high waveform capture rate

Background technique

With the development of digital signal processing technology, the research on time-domain signal analysis technology based on high-speed sampling is getting more and more in-depth, and the digital time-domain test instrument has also been developed rapidly. As a typical time-domain test instrument, digital storage oscilloscope has obtained widely used.

The waveform capture rate is one of the important indicators for evaluating the performance of a digital storage oscilloscope. The so-called "waveform capture rate" refers to the number of waveforms captured and displayed by the digital oscilloscope per unit time. Insufficient waveform capture rate will make it impossible to find most transient and occasional signals, let alone signal jitter analysis and eye diagram analysis.

As shown in Figure 1, the traditional digital storage oscilloscope usually adopts a serial processing structure. The sampled data is transmitted from the acquisition memory to the microprocessor, processed by the microprocessor, calculates parameters, and finally sent to the display. During the period when the microprocessor is processing the waveform data, the oscilloscope cannot collect the signal waveform. This period is called "blind zone time". Typically, the oscilloscope sample capture time is only about 1% of the total observation time. Therefore, 99% of the waveform details will be missed during the blind time, and the waveform capture rate is insufficient, which greatly reduces the test efficiency. In many cases, it cannot meet the requirements of real-time test applications.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art and provide a digital storage oscilloscope with a very high waveform capture rate to improve test efficiency.

In order to realize the object of the above invention, the extremely high waveform capture rate digital storage oscilloscope of the present invention includes: a signal conditioning module, an ADC conversion module, a trigger and a time base circuit, an acquisition memory, a microprocessor, a display memory, a display screen, and a parallel cooperative processor;

The input test signal is sent to the ADC conversion module for sampling after being conditioned by the signal conditioning module, and the sampling data is sent to the acquisition memory buffer under the control of the trigger and time base circuit;

After completing a waveform acquisition, the parallel coprocessor maps the acquisition data in the acquisition memory into waveform dot matrix data corresponding to the dot matrix of the display screen, and restarts a new round of acquisition and mapping after the mapping is completed;

At the same time, the microprocessor performs menu management and man-machine interface management. When the timing refresh time of the display screen is reached, it immediately starts the display refresh control logic, and automatically converts the waveform dot matrix data in the parallel coprocessor to the The dot matrix data in the interface database related to machine interface management work is combined in the display memory, and the display on the display screen is updated.

The present invention adopts the framework of signal waveform acquisition and processing in parallel with the microprocessor, so that the microprocessor can be separated from the heavy waveform processing and display, reducing the blind time of the digital storage oscilloscope, improving the waveform capture rate, and increasing the detection rate. The probability of transient abnormal signals is reduced, which also improves the test efficiency.

Description of drawings

Figure 1 is a block diagram of a traditional digital storage oscilloscope;

Fig. 2 is a schematic block diagram of a specific embodiment of a digital storage oscilloscope with a very high waveform capture rate of the present invention;

Fig. 3 is a functional block diagram of a specific embodiment of the parallel coprocessor shown in Fig. 2;

Fig. 4 is a schematic diagram of a specific embodiment in which the sampling data in the digital storage oscilloscope with a very high waveform capture rate of the present invention is mapped into a waveform database corresponding to the dot matrix of the display screen;

Figure 5 is a capture effect diagram of a traditional serial structure digital storage oscilloscope;

Fig. 6 is a capture effect diagram of the digital storage oscilloscope of the present invention.

Detailed ways

The following describes preferred specific embodiments of the present invention in conjunction with the accompanying drawings. It is to be noted that similar components are given similar reference numerals even though they appear in different drawings. In the following description, when a detailed description of known functions and designs employed may obscure the subject matter of the present invention, these descriptions will be omitted here.

Figure 1 is a block diagram of a traditional digital storage oscilloscope. In the figure, after the input signal is conditioned by the signal conditioning module 1, the output amplitude is within a certain range and is suitable for the ADC conversion module 2 to perform data sampling. Under the control of the trigger and time base circuit 3, the waveform data sampled by the ADC conversion module 2 Send it to the cache in the acquisition memory 4.

After completing a waveform data collection, the microprocessor 5 reads the collected waveform data into processing, and finally displays the waveform of the input signal and interface data related to menu management and man-machine interface management on the display screen 7 through the display memory 6 come out.

During the period during which the microprocessor 5 is processing waveform data, the oscilloscope cannot collect signal waveforms, and the waveform capture rate is insufficient, which greatly reduces test efficiency. In many cases, it cannot meet the requirements of real-time test applications.

Fig. 2 is a functional block diagram of a specific embodiment of the digital storage oscilloscope with a very high waveform capture rate of the present invention. In this embodiment, the extremely high waveform capture rate digital storage oscilloscope of the present invention includes: a signal conditioning module 1, an ADC conversion module 2, a trigger and a time base circuit 3, an acquisition memory 4, a microprocessor 5, a display memory 6, a display Screen 7, and parallel coprocessor 8;

The input test signal is sent to the ADC conversion module 2 for sampling after being conditioned by the signal conditioning module 1, and the sampling data is sent to the acquisition memory 4 cache under the control of the trigger and time base circuit 3 and the parallel coprocessor 8;

After completing a waveform acquisition, the parallel coprocessor 8 maps the acquisition data in the acquisition memory 4 into waveform dot matrix data corresponding to the dot matrix of the display screen, and restarts a new round of acquisition and mapping after the mapping is completed;

Meanwhile, microprocessor 5 carries out menu management, man-machine interface management work, when reaching display screen 7 timing refresh time, starts display refresh control logic at once, and the waveform dot matrix data in parallel coprocessor 8 and menu The dot matrix data in the interface database related to management and man-machine interface management work are combined in the display memory 6, and the display on the display screen 7 is updated.

FIG. 3 is a functional block diagram of a specific implementation manner of the parallel coprocessor shown in FIG. 2 . The parallel coprocessor is the core of improving the fast waveform capture rate. In this embodiment, its main functions include not only the processing of waveform acquisition data and the display of waveforms, but also the acquisition control module, which is used to control the buffering of waveforms related to trigger events data, thus further reducing the computational processing burden on the microprocessor 5.

In this embodiment, the parallel coprocessor 8 includes four parts, an acquisition control module 801 , a waveform feature processing module 802 , a waveform database 803 and a database read-write control module 804 . The acquisition control module 801 is used to control and buffer waveform data related to trigger events. After completing an acquisition event, the control right of the high-speed data buffer is transferred to the waveform feature processing module 802, which performs sampling or interpolation processing on the acquired data cached in the acquisition memory 4, and then converts the acquired data point by point into the amplitude of the waveform according to the time relationship For features, two-dimensional feature data is stored in the waveform database 803 according to the relationship between time and amplitude, and waveform dot matrix data corresponding to the dot matrix of the display screen is formed in the waveform database.

After one acquisition and mapping is completed, a new round of acquisition and mapping process is started immediately. When the waveform mapping amount, that is, the number of repeated acquisitions reaches the set level, the database read-write control module 804 sends the waveform lattice data to The display memory 6 is displayed.

In this embodiment, the acquisition memory 4 is implemented by configuring the BLOCK RAM in the FPGA as a FIFO, and its working speed can generally reach 250MB/s.

The acquisition process is mainly completed under the control of the trigger and time base circuit 3 and the acquisition control module 801 . The acquisition control module 801 starts the data acquisition process, the FIFO write enable is valid, the FIFO write clock is synchronized with the sampling clock of the ADC conversion module 2, and the sampling data generated by the conversion module 2 is written into the FIFO. At the same time, start the pre-trigger counter until the count value of the pre-trigger counter reaches the preset trigger depth value. During this time, the trigger circuit in the trigger and time base circuit 3 is in a suppressed state. When the depth of data written in the FIFO is equal to the pre-trigger depth value, if the trigger signal has not arrived, the FIFO read and write will be synchronized, and the number of data in the FIFO will always be kept equal to the pre-trigger depth value; when the trigger arrives, the FIFO read enable will be invalid. At this time, the FIFO data can only be written but not read until it is full. The acquisition of waveform data belongs to the prior art. In this implementation, only the acquisition control module 801 is used to control the waveform data related to buffering and triggering events, and complete the acquisition of waveform data. In this way, the workload of microprocessor 5 is further reduced. Computational processing burden.

In this embodiment, after the FIFO is full, its control right is transferred to the waveform feature processing module 802. At this time, the control read enable is valid, and the waveform feature processing module 802 reads the data in the FIFO and performs the processing in the waveform database 803. Two-dimensional data mapping, FIFO read only but not write, until all data in FIFO is read.

The waveform database 803 is also designed in the FPGA, configured by BLOCK RAM, and its capacity is determined by the pixels of the display screen 7.

Assuming that the total number of points in the horizontal direction of a waveform is T, and the resolution of the ADC conversion module 2 is N, the maximum sampling value is 2 ^N , which will be regarded as the amplitude characteristic of the waveform, and the required waveform database capacity is: T×2 ^N bits.

When performing waveform mapping, the storage work of the waveform database is drawn from top to bottom and from left to right, that is, when T data are collected at one time, the size is represented by _Xi , where 0≤i≤T-1 , 0≤X _i ≤2 ^N , under the control of the waveform feature processing module in chronological order, draw the T data into the i-th column and X _{i -} th row storage unit of the waveform database according to the value of Xi.

It is not difficult to see that the start address of each column of dot matrix in the waveform dot matrix data in the waveform database 803 is an integer multiple of 2 ^N , that is, the start address of the i-th column is: 2 ^N ×i, then when the i-th sample When the data arrives at the waveform feature processing module 802, the corresponding storage location _Bi is:

B _i ＝2 ^N ×i+X _i Formula 1)

When the waveform feature processing module 802 controls the mapping of the collected data to the waveform database 803, the addressed storage unit is marked as 1.

After several waveform acquisitions and mappings are performed within the preset time, the traces left by the waveforms after multiple acquisitions are recorded in the waveform database 803 , that is, the waveform dot matrix data corresponding to the dot matrix of the display screen.

In order to more intuitively understand the mapping process that the collected data of the present invention is mapped into the waveform dot matrix data corresponding to the dot matrix of the display screen, as shown in Figure 4, the numbers on the left, right and top of the figure represent each The address of the pixel in the waveform database 803, the number at the bottom indicates each column in the display screen, and B _i indicates the address of the i-th collected data in this column.

In this embodiment, the number T of collected data at one time is 500, the resolution N of the ADC conversion module 2 is 8, and the size of collected data _Xi is "128, 112, 54, 33...", then a waveform database is required The size of 803 is 500×256=128000bit, where each bit corresponds to the pixel in the dot matrix of the display screen. It can be seen from formula 1),

The size of the first collected data is 128, which is mapped to the storage location:

B0=0+128=128;

The size of the second collected data is 112, which is mapped to the storage location:

B1=256+112=368;

The size of the third collection data is 54, which is mapped to the storage location:

B2=256×2+54=566;

The size of the fourth collected data is 33, which is mapped to the storage location:

B3=256×3+33=801;

……….

The storage unit addressed according to the storage location is marked as 1, so that the trace left by the waveform after one acquisition is recorded in the waveform database 803 .

In this embodiment, when the waveform feature processing module 802 completes the waveform mapping within the preset time, the database read-write control module 804 is started immediately, and the waveform database 803 sends the mapped two-dimensional waveform data into the display memory under its control. 6, and update the display.

The design of the database read-write control module is relatively simple. It only needs to generate addresses sequentially when it works, and import waveform data into the video memory. It should be noted that the moment to start its work should be coordinated to avoid screen flicker caused by updating the video memory.

A digital storage oscilloscope with a traditional serial processing structure and a digital storage oscilloscope with a very high waveform capture rate of the present invention are compared and tested with the same carrier frequency 1MHz and amplitude modulation wave signal with a modulation frequency of 1kHz.

Because the digital storage oscilloscope with the traditional serial processing structure collects, processes, and refreshes the screen, the time for acquisition and processing is about the order of us. When refreshing the screen, due to the large amount of data, it takes ms to complete a screen refresh. Processing and The waveform cannot be collected during the screen refresh period, so the capture efficiency of the traditional digital storage oscilloscope with serial structure is quite low. Therefore, in Figure 5, we can see that the traditional digital storage oscilloscope with serial architecture only acquires two waveforms during one waveform refresh process.

And a very high waveform capture rate digital storage oscilloscope under the present invention, while performing waveform processing and refreshing the screen, in the ms level time of video memory update, the parallel coprocessor can also collect and map waveforms. The blind zone time is only the us-level mapping time of the waveform, which greatly improves the waveform capture rate. Thereby, in Fig. 6, we can see that a very high waveform capture rate digital storage oscilloscope under the present invention has captured a large amount of waveforms, and the waveform capture rate can be as high as 160,000wfs/s, reflecting the real situation of the waveform, reducing The waveform loss rate in acquisition is reduced, and the test efficiency is improved.

Although the specific embodiment of the illustrative embodiment of the present invention has been described above, it should be clear that the present invention is not limited to the scope of the specific embodiment. For those of ordinary skill in the art, as long as various changes are defined in the attached claims and Within the determined spirit and scope of the present invention, these changes are obvious, and all inventions and creations using the concept of the present invention are included in the protection list.

Claims (3)

1, a kind of digital storage oscillograph with very high waveform capturing rate comprises: signal condition module, ADC modular converter, triggering and time base circuit, acquisition memory, microprocessor, display-memory, display screen, it is characterized in that, and also comprise a parallel coprocessor;

Input test signal is sent into the ADC modular converter and is sampled after the conditioning of signal condition module, under the control of triggering and time base circuit sampled data is sent into the acquisition memory buffer memory;

After finishing waveform acquisition, parallel coprocessor is mapped to the image data in the acquisition memory and the corresponding waveform dot array data of display screen dot array, begins the collection and the mapping of a new round after mapping is finished again;

Meanwhile, microprocessor carries out menu management, man-machine interface management work, when arriving the display screen periodic refreshing during time, at once start and show refresh control logic, automatically the dot array data in the relevant interface data storehouse of waveform dot array data and menu management, the man-machine interface management work in the coprocessor of will walking abreast makes up in display-memory, and the demonstration of update displayed screen;

Include an acquisition control module in the described parallel coprocessor, be used to control the buffer memory Wave data relevant with trigger event;

Described parallel coprocessor also comprises waveform character processing module and waveform database;

Described parallel coprocessor is mapped to the image data in the acquisition memory with the corresponding waveform dot array data of display screen dot array: the waveform character processing module, the image data of buffer memory in the acquisition memory is taken out a little or interpolation processing, then the image data pointwise is converted to the amplitude characteristic of waveform by the time relation, tie up to according to the pass of time and amplitude and to carry out the two dimensional character data storage in the waveform database, in waveform database, form and the corresponding waveform dot array data of display screen dot array.

2, digital storage oscillograph with very high waveform capturing rate according to claim 1, it is characterized in that, described parallel coprocessor also comprises a data base read-write control module, reach the grade of setting when the waveform map amount after, by the data base read-write control module data point battle array data in the waveform database are sent to display-memory, and show.

3, digital storage oscillograph with very high waveform capturing rate according to claim 1 and 2, it is characterized in that, described image data pointwise converts the amplitude characteristic of waveform to by time relation, ties up to according to the pass of time and amplitude and carries out the two dimensional character data storage in the waveform database and be:

Waveform always counting in the horizontal direction is that T, the resolution of ADC modular converter are N, and then maximum sampled value is 2 ^N, regard it amplitude characteristic of waveform as;

Carrying out waveform when mapping, the storage work of waveform database is by from top to bottom, and mode is from left to right drawn, the T of Cai Jiing data once, its size X _iExpression, 0≤i≤T-1 wherein, 0≤X _i≤ 2 ^N, in chronological order successively under the control of waveform character processing module, according to X _iValue with the i of T data drawing waveforms database row, X _iLine storage unit, the memory location B of correspondence in the waveform database _i,

B _i＝2 ^N×i+X _i

Storage unit promptly be marked as 1.

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