WO2021259228A1

WO2021259228A1 - Inter-module communication method and system

Info

Publication number: WO2021259228A1
Application number: PCT/CN2021/101411
Authority: WO
Inventors: 高嘉琪; 李远超; 蔡权雄; 牛昕宇
Original assignee: 深圳鲲云信息科技有限公司
Priority date: 2020-06-22
Filing date: 2021-06-22
Publication date: 2021-12-30
Also published as: CN111752875A

Abstract

Disclosed in embodiments of the present application are an inter-module communication method and system. The communication method is used for controlling data transmission among a first memory, a second memory, and a register, and the register is connected between the first memory and the second memory. The communication method comprises: the first memory receives a first permission signal sent by the register; the first memory provides a first valid signal to the register so as to write a first piece of data into the register; the register receives a second permission signal sent by the second memory; the register provides a second valid signal to the second memory to write the first piece of data into the second memory.

Description

Communication method and system between modules

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with an application number of 202010575497.5 on June 22, 2020, and the entire content of this application is incorporated into this application by reference.

Technical field

The embodiments of the present application relate to communication technology, for example, to an inter-module communication method and system.

Background technique

AXI (AdvancedeXtensibleInterface) is a bus protocol, which is the most important part of the AMBA (Advanced MicrocontrollerBusArchitecture) 3.0 protocol proposed by ARM. It is a high-performance, high-bandwidth, low-latency on-chip bus. Its address/control and data phases are separated to support unaligned data transmission. At the same time, in burst transmission, only the first address is needed, and the read and write data channels are separated at the same time, and it supports Outstanding transmission access and out-of-order access, and It is easier to perform timing closure.

However, when the AXI bus protocol is used for communication, the data is transmitted in frames or packets. There is a 4K boundary, and a large number of control signals such as addresses are required. It is impossible to flexibly suspend the communication data transmission between modules at any time.

Summary of the invention

The embodiments of the present application provide an inter-module communication method and system, so as to realize the flexibility of communication data transmission between the modules.

The embodiment of the application provides an inter-module communication method. The inter-module communication method is used to control data transmission between a first memory, a second memory, and a register, and the register is connected between the first memory and the second memory. , The communication method between modules includes:

The first memory receives the first permission signal sent by the register;

The first memory provides a first valid signal to the register to write the first piece of data into the register;

The register receives the second permission signal sent by the second memory;

The register provides a second valid signal to the second memory to write the first segment of data into the second memory.

Optionally, the receiving, by the first memory, the first permission signal sent by the register includes:

The register pulls the first permission signal of its uplink permission end high;

The first permission end of the first memory enters the readable state after receiving the high-level first permission signal sent by the uplink permission end of the register.

Optionally, the providing, by the first memory, a first valid signal to the register to write the first piece of data into the register includes:

The first memory pulls the first valid signal of the first valid end of the first memory high;

The upstream valid end of the register becomes a writable state after receiving the first valid signal of high level and stores the first segment of data.

Optionally, the register receiving the second permission signal sent by the second memory includes:

The second memory pulls the second permission signal of its second permission terminal high;

The downlink permitting end of the register receives the high-level second permitting signal sent by the second permitting end of the second memory.

Optionally, that the register providing a second valid signal to the second memory to write the first piece of data into the second memory includes:

The register pulls the second valid signal of its downstream valid end high;

The second valid end of the second memory receives a high-level second valid signal and becomes a writable state and stores the first piece of data.

On the one hand, an embodiment of the present application also provides an inter-module communication system. The inter-module communication system includes a first memory, a second memory, and a register, and the register is connected between the first memory and the second memory,

The first memory receives the first permission signal sent by the register;

The register receives the second permission signal sent by the second memory;

Optionally, the register pulls the first permission signal of its uplink permission end high;

Optionally, the first memory pulls the first valid signal of its first valid end high;

Optionally, the second memory pulls the second permission signal of its second permission terminal high;

Optionally, the register pulls the second valid signal of its downstream valid end high;

In this embodiment of the application, the first memory receives the first permission signal sent by the register; the first memory provides the first valid signal to the register to write the first segment of data into the register; the register receives the second permission signal sent by the second memory; the register Provide the second valid signal to the second memory to write the first segment of data into the second memory, which solves the problem that the communication data transmission between the modules cannot be flexibly suspended at any time, and the flexibility of the communication data transmission between the modules is realized Effect.

Description of the drawings

FIG. 1 is a schematic flowchart of an inter-module communication method provided by Embodiment 1 of the present application;

2 is a schematic flowchart of a communication method between modules provided in Embodiment 2 of the present application;

3 is a schematic diagram of the working sequence of the inter-module communication method provided in the second embodiment of the present application;

FIG. 4 is a schematic structural diagram of an inter-module communication system provided in Embodiment 3 of this application.

detailed description

The application will be described below with reference to the drawings and embodiments. It is understandable that the specific embodiments described here are used to explain the application, but not to limit the application. In addition, it should be noted that, for ease of description, the drawings only show a part of the structure related to the present application, but not all of the structure.

Some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowchart describes the steps as sequential processing, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The processing may be terminated when its operations are completed, but may also have additional steps not included in the drawings. Processing can correspond to methods, functions, procedures, subroutines, subroutines, and so on.

In addition, the terms "first", "second", etc. may be used herein to describe various directions, actions, steps or elements, etc., but these directions, actions, steps or elements are not limited by these terms. These terms are only used to distinguish a first direction, action, step or element from another direction, action, step or element. For example, without departing from the scope of the present application, the first memory may be referred to as the second memory, and similarly, the second memory may be referred to as the first memory. Both the first memory and the second memory are memories, but they are not the same memory. The terms "first", "second", etc. cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

Example one

As shown in Figure 1, the first embodiment of the present application provides an inter-module communication method. The inter-module communication method is used to control data transmission between a first memory, a second memory and a register, and the register is connected to the first memory. Between the memory and the second memory, the inter-module communication method includes:

S110. The first memory receives a first permission signal sent by the register.

S120. The first memory provides a first valid signal to the register to write the first segment of data into the register.

In this embodiment, when the first memory receives the first permission signal sent by the register, it means that the register is ready to receive the data that needs to be written in the first memory. After the first memory receives the first permission signal sent by the register , The first memory can read the first piece of data. When the first memory provides the first valid signal to the register, it means that the first memory can write the first segment data into the register. After the register receives the first valid signal sent by the first memory, the register can write the first segment data.

When the first memory receives the first permission signal sent by the register and the register also receives the first valid signal sent by the first memory, the first piece of data starts to be written into the register from the first memory. Wherein, when any signal stops sending, that is, when the register stops sending the first permission signal to the first memory or the first memory stops sending the first valid signal to the register, the transmission of the communication will stop immediately.

S130. The register receives a second permission signal sent by the second memory.

S140. The register provides a second valid signal to the second memory to write the first segment of data into the second memory.

In this embodiment, after step S120 is executed, the first piece of data has been written from the first memory into the register, and the first piece of data is stored in the register. When the register receives the first permission signal sent by the second memory, it means that the second memory is ready to receive the data that needs to be written in the register. After the register receives the second permission signal sent by the second memory, the register can be read The first paragraph of data. When the register provides the second valid signal to the second memory, it means that the register can write the first segment of data into the second memory. After the second memory receives the second valid signal sent by the register, the second memory can write to the second memory. A piece of data.

When the register receives the first permission signal sent by the second memory, and at the same time the second memory also receives the second valid signal sent by the register, the first piece of data starts to be written into the second memory from the register. Wherein, when any signal stops sending, that is, when the second memory stops sending the second permission signal to the register or the register stops sending the second valid signal to the second memory, the transmission of the communication will stop immediately. This completes the transfer of the first piece of data from the first memory to the second memory. In addition, it should be noted that the first piece of data does not refer to the first piece of data in order, and the first piece of data can be any piece of data in actual communication.

The embodiment of the application ensures the accuracy and stability of the data transmission between the modules by changing the transmission interface between the modules to the above-mentioned communication bus format. In addition, if the wiring distance between the modules is too long or the transmission data bit width is too large, it will cause There is a timing error in the data transmission between the modules. The embodiment of the present application also optimizes the timing of the communication bus by adding a register between the first memory and the second memory, and solves the problem of timing errors.

Example two

As shown in Figures 2 and 3, the second embodiment of the present application provides an inter-module communication method. The second embodiment of the present application is described on the basis of the first embodiment of the present application. Data transfer between a memory, a second memory and a register, the register being connected between the first memory and the second memory.

In this embodiment, the signal is sent only when the clock cycle rises. The first memory includes a first permission end, a first valid end, and a first data end, and the second memory includes a second permission end, a second valid end, and a first data end. The second data terminal, the register includes the upstream permit terminal, the upstream valid terminal, the upstream data terminal, the downstream permit terminal, the downstream valid terminal and the downstream data terminal. The first memory transmits data to the upstream data terminal of the register through the first data terminal, and the register passes The downlink data terminal transmits the data to the second data terminal of the second memory.

The inter-module communication methods include:

S210. The register pulls up the first permission signal of its uplink permission end.

S220: The first permitting terminal of the first memory enters the readable state after receiving the high-level first permitting signal sent by the uplink permitting terminal of the register.

In this embodiment, when data is not stored in the register, or data can be stored, the register can pull the first permission signal of its uplink permission end from low to high, which means that the register is ready to receive the first permission signal. The data to be written in the memory. When the clock cycle is rising, the first permission end of the first memory will receive the high level first permission signal sent by the upstream permission end of the register, and then the first memory will enter the readable state, that is, the first segment can be read data.

S230. The first memory pulls the first valid signal of the first valid end of the first memory high.

S240. The upstream valid end of the register becomes a writable state after receiving the first valid signal of high level and stores the first piece of data.

In this embodiment, after the first piece of data stored in the first memory is read, at any time thereafter, the first memory can pull the first valid signal of its first valid end from low to high. Ping means that the first memory can write the first segment of data into the register. When the clock cycle is rising, the upstream valid end of the register will receive the high-level first valid signal sent by the first valid end of the first memory, after which the register enters a writable state, and the first segment of data can be written and stored.

When the first permitting end of the first memory receives the first permit signal sent by the upstream permitting end of the register, and at the same time the upstream valid end of the register also receives the first valid signal sent by the first valid end of the first memory, the first The segment data starts to be written into the register from the first memory. Wherein, when any signal stops sending, that is, when the register stops sending the first permission signal to the first memory or the first memory stops sending the first valid signal to the register, the transmission of the communication will stop immediately.

S250. The second memory pulls the second permission signal of its second permission terminal high.

S260. The downlink permitting end of the register receives a high-level second permitting signal sent by the second permitting end of the second memory.

In this embodiment, at this time, the first piece of data has been written from the first data end of the first memory into the upstream data end of the register, and the first piece of data is stored in the register. At this time, the second memory can pull the second permission signal of its second permission terminal from low level to high level, which means that the second memory is ready to receive the data that needs to be written in the register. When the clock cycle is rising, the downstream permitting end of the register receives the high-level second permitting signal sent by the second permitting end of the second memory. After that, the register enters the readable state, that is, the second permitting end of the register can be read from the upstream data end. A piece of data is sent to the downstream data terminal.

S270. The register pulls the second valid signal of its downstream valid end high.

S280: The second valid end of the second memory receives a high-level second valid signal and becomes a writable state and stores the first piece of data.

In this embodiment, after the first piece of data stored in the register is read, at any time thereafter, the register can pull the second valid signal of its downstream valid end from low to high, which means that the register The first segment of data can be written into the second memory. When the clock cycle is rising, the second valid end of the second memory will receive the high-level second valid signal sent by the downstream valid end of the register. After that, the second memory becomes writable and can write and store all Describe the first paragraph of data.

When the register receives the first permission signal sent by the second memory and the second memory also receives the second valid signal, the first piece of data starts to be written from the register to the second memory. Wherein, when any signal stops sending, that is, when the second memory stops sending the second permission signal to the register or the register stops sending the second valid signal to the second memory, the transmission of the communication will stop immediately. This completes the transfer of the first piece of data from the first memory to the second memory. In addition, it should be noted that the first piece of data does not refer to the first piece of data in order, and the first piece of data can be any piece of data in actual communication.

In the same way, as shown in FIG. 3, the data transmission can be continuous, and the first data, the second data, the third data, and more data can be transmitted through the same method as described above.

Example three

As shown in FIG. 4, the third embodiment of the present application provides an inter-module communication system. The inter-module communication system includes a first memory 100, a second memory 300, and a register 200. The register 200 is connected to the first memory 100 and Between the second storage 300.

Wherein, the first memory 100 receives the first permission signal sent by the register 200; the first memory 100 provides the first valid signal to the register 200 to write the first piece of data into the register 200; The register 200 receives the second permission signal sent by the second memory 300; the register 200 provides a second valid signal to the second memory 300 to write the first piece of data into the second memory 300.

In this embodiment, the first storage 100 includes a first license port 120, a first valid port 130, and a first data port 110, and the second storage 300 includes a second license port 320, a second valid port 330, and a second data port 310. , The register 200 includes an upstream permit terminal 220, an upstream valid terminal 230, an upstream data terminal 210, a downstream permit terminal 250, a downstream valid terminal 260, and a downstream data terminal 240. The first memory 100 transmits data to the register 200 through the first data terminal 110 The register 200 transmits data to the second data terminal 310 of the second memory 300 through the downstream data terminal 240.

The register 200 pulls the first permission signal of its upstream permitting terminal 220 high; the first permitting terminal 120 of the first memory 100 receives the upstream permitting terminal 220 of the register 200 to send a high-level first permit After the signal, it enters the readable state. The first memory 100 pulls the first valid signal of its first valid end 130 high; the upstream valid end 230 of the register 200 becomes a writable state after receiving the first valid signal of high level and stores the first valid signal. A piece of data. The second memory 300 pulls the second permission signal of its second permission terminal 320 high; the downlink permission terminal 250 of the register 200 receives the high level first permission signal sent by the second permission terminal 320 of the second memory 300 2. Permission signal. The register 200 pulls the second valid signal of its downstream valid end 260 high; the second valid end 330 of the second memory 300 receives a high-level second valid signal and becomes a writable state and stores the first valid signal. A piece of data.

Specifically, in this embodiment, the signal is sent only when the clock cycle rises. When no data is stored in the register 200, or when data can be stored, the register 200 can change the first permission signal of the uplink permission terminal 220 from low. Pulling the level high to a high level means that the register 200 is ready to receive the data that needs to be written in the first memory 100. When the clock cycle is rising, the first permitting terminal 120 of the first memory 100 will receive the high-level first permitting signal sent by the upstream permitting terminal 220 of the register 200, and then the first memory 100 will enter the readable state, that is, Read the first piece of data.

After the first piece of data stored in the first memory 100 is read, at any time thereafter, the first memory 100 can pull the first valid signal of its first valid end 130 from low to high. , Which means that the first memory 100 can write the first segment of data into the register 200. When the clock cycle is rising, the upstream valid end 230 of the register 200 will receive the high-level first valid signal sent by the first valid end 130 of the first memory 100, after which the register 200 enters the writable state, which can be written and stored The first paragraph of data.

When the first permitting end 120 of the first storage 100 receives the first permitting signal sent by the upstream permitting end 220 of the register 200, at the same time, the upstream valid end 230 of the register 200 also receives the first valid end 130 of the first storage 100. When the first valid signal occurs, the first segment of data starts to be written from the first memory 100 to the register 200. Wherein, when any signal stops sending, that is, when the register 200 stops sending the first permission signal to the first memory 100 or the first memory 100 stops sending the first valid signal to the register 200, the transmission of the communication will stop immediately.

At this time, the first piece of data has been written from the first data terminal 110 of the first memory 100 into the upstream data terminal 210 of the register 200, and the first piece of data is stored in the register 200. At this time, the second memory 300 can pull the second permission signal of the second permission terminal 320 from the low level to the high level, which means that the second memory 300 is ready to receive the data to be written in the register 200. When the clock cycle is rising, the downstream permitting terminal 250 of the register 200 receives the high-level second permitting signal sent by the second permitting terminal 320 of the second memory 300, and then the register 200 enters the readable state, that is, it can start from the upstream The data terminal 210 reads the first piece of data to the downstream data terminal 240.

When the first piece of data stored in the register 200 is read, at any time thereafter, the register 200 can pull the second valid signal of its downstream valid end 260 from low to high, which means that the register 200 The first piece of data can be written into the second memory 300. When the clock cycle is rising, the second valid end 330 of the second memory 300 will receive the high-level second valid signal sent by the downstream valid end 260 of the register 200, and then the second memory 300 becomes a writable state. Write and store the first piece of data.

When the register 200 receives the first permission signal sent by the second memory 300 and the second memory 300 also receives the second valid signal, the first piece of data starts to be written from the register 200 to the second memory 300. Wherein, when any signal stops sending, that is, when the second memory 300 stops sending the second permission signal to the register 200 or the register 200 stops sending the second valid signal to the second memory 300, the transmission of the communication will stop immediately. Thus, the transfer of the first piece of data from the first memory 100 to the second memory 300 is completed. In addition, it should be noted that the first piece of data does not refer to the first piece of data in order, and the first piece of data can be any piece of data in actual communication.

The embodiment of the application ensures the accuracy and stability of the data transmission between the modules by changing the transmission interface between the modules to the above-mentioned communication bus format. In addition, if the wiring distance between the modules is too long or the transmission data bit width is too large, it will cause There is a timing error in data transmission between modules. The embodiment of the present application also optimizes the timing of the communication bus by adding a register 200 between the first memory 100 and the second memory 300, and solves the problem of timing errors.

Claims

An inter-module communication method for controlling data transmission between a first memory, a second memory and a register, the register being connected between the first memory and the second memory, the method comprising:

The first memory receives the first permission signal sent by the register;

The first memory provides a first valid signal to the register to write the first piece of data into the register;

The register receives the second permission signal sent by the second memory;

The register provides a second valid signal to the second memory to write the first segment of data into the second memory.
4. The inter-module communication method according to claim 1, wherein the receiving, by the first memory, the first permission signal sent by the register comprises:

The register pulls the first permission signal of its uplink permission end high;

The first permission end of the first memory enters the readable state after receiving the high-level first permission signal sent by the uplink permission end of the register.
The inter-module communication method according to claim 1, wherein the providing the first valid signal to the register by the first memory to write the first piece of data into the register comprises:

The first memory pulls the first valid signal of the first valid end of the first memory high;

The upstream valid end of the register becomes a writable state after receiving the first valid signal of high level and stores the first segment of data.
4. The inter-module communication method according to claim 1, wherein the register receiving the second permission signal sent by the second memory comprises:

The second memory pulls the second permission signal of its second permission terminal high;

The downlink permitting end of the register receives the high-level second permitting signal sent by the second permitting end of the second memory.
The inter-module communication method according to claim 1, wherein the register providing a second valid signal to the second memory to write the first piece of data into the second memory comprises:

The register pulls the second valid signal of its downstream valid end high;

The second valid end of the second memory receives a high-level second valid signal and becomes a writable state and stores the first piece of data.
An inter-module communication system includes a first memory, a second memory and a register, the register is connected between the first memory and the second memory, wherein,

The first memory receives the first permission signal sent by the register;

The first memory provides a first valid signal to the register to write the first piece of data into the register;

The register receives the second permission signal sent by the second memory;

The register provides a second valid signal to the second memory to write the first segment of data into the second memory.
The inter-module communication system according to claim 6, wherein:

The register pulls the first permission signal of its uplink permission end high;

The first permission end of the first memory enters the readable state after receiving the high-level first permission signal sent by the uplink permission end of the register.
The inter-module communication system according to claim 6, wherein:

The first memory pulls the first valid signal of the first valid end of the first memory high;

The upstream valid end of the register becomes a writable state after receiving the first valid signal of high level and stores the first segment of data.
The inter-module communication system according to claim 6, wherein:

The second memory pulls the second permission signal of its second permission terminal high;

The downlink permitting end of the register receives the high-level second permitting signal sent by the second permitting end of the second memory.
The inter-module communication system according to claim 6, wherein:

The register pulls the second valid signal of its downstream valid end high;

The second valid end of the second memory receives a high-level second valid signal and becomes a writable state and stores the first piece of data.