CN104008076B - The method and device that a kind of data signal bus for supporting DVFS transmits - Google Patents
The method and device that a kind of data signal bus for supporting DVFS transmits Download PDFInfo
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- CN104008076B CN104008076B CN201310059075.2A CN201310059075A CN104008076B CN 104008076 B CN104008076 B CN 104008076B CN 201310059075 A CN201310059075 A CN 201310059075A CN 104008076 B CN104008076 B CN 104008076B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses the method and device that a kind of data signal bus for supporting DVFS transmits, it is related to IC low power dissipation designs field, methods described includes：Sent by the use of originating party voltage domain clock signal and be used as the data signal bus across voltage domain signal；Will across the voltage domain signal carry out level conversion；Received and passed through described in level conversion across voltage domain signal using debit's voltage domain clock signal.The present invention realizes asynchronous AXI interfaces, and pass through the asynchronous AXI interfaces realized and data signal bus transmission stable at a high speed is carried out between two voltage domains, sequential is easier to restrain, so as to improve stability and reliability of the whole system when dynamic electric voltage and frequency adjust.
Description
Technical field
The present invention relates to IC low power dissipation design field, more particularly to a kind of support DVFS two support dynamic
Asynchronous AXI interfaces are realized between electric voltage frequency adjustment DVFS voltage domain, and using realizing that stating asynchronous AXI interfaces realizes bus
The method and relevant apparatus of data signal transmission.
Background technology
With being in fashion for consumer electronics product, consumer for can the requirement of portable product function also become increasingly complex.
How the relative capacity in battery also without before further being lifted, uses the energy of battery limited in the most efficient manner,
Become at present can the most significant problems that are faced of portable consumer electronics product, and carry out design chips using Low-power Technology
Seemingly only current option.The power consumption of complementary metal oxide semiconductor cmos circuit is divided to dynamic power consumption and quiescent dissipation two
Part.Dynamic power consumption is main relevant with load capacitance C with voltage V, working frequency F.Quiescent dissipation is main and voltage V, subthreshold value
It is current related.So the power consumption of circuit can be effectively reduced by reducing voltage V and working frequency F.
In recent years industry dynamic voltage frequency is adjusted DVFS research and application than wide, that is, in buck/boost
While V, working frequency F adjusts also with dynamic, reaches the purpose for reducing power consumption.Relative to traditional dynamic frequency scalable
DFS, DVFS can both reduce power consumption, also can really reach the purpose for reducing energy expenditure.
At present, in order to reduce the implementation complexity of system, DVFS application is improved, asynchronous interface circuit can first pass through
One indication signal blocks the bus data transfer between two voltage domains, after the completion of waiting DFS operations, release obstruction letter
Number, continue bus transfer.This asynchronous interface circuit frequency is not high, and data transmission efficiency is low.
, can also be by accurately adjusting the clock phases of two voltage domains for using between two voltage domains of synchronised clock
Position, reaches synchronization, to ensure the reliability of data transfer.This circuit uses fixed frequency, comes for DVFS designs
Say, because signal is bigger by delay jitter caused by Clock Tree, very big difficulty is caused to timing closure.
The content of the invention
, can be more preferable it is an object of the invention to provide the method and device that a kind of data signal bus for supporting DVFS transmits
Ground solves the problems, such as that data transmission efficiency is low in the prior art and sequential is difficult to convergence.
According to an aspect of the invention, there is provided a kind of method that data signal bus for supporting DVFS transmits, including：
Sent by the use of originating party voltage domain clock signal and be used as the data signal bus across voltage domain signal；
Will across the voltage domain signal carry out level conversion；
Received and passed through described in level conversion across voltage domain signal using debit's voltage domain clock signal.
Preferably, between originating party voltage domain and debit's voltage domain during transfer bus data-signal, originating party voltage domain and/
Or debit's voltage domain carries out dynamic voltage frequency adjustment DVFS processing.
Preferably, between originating party voltage domain and debit's voltage domain during transfer bus data-signal, originating party voltage domain will
The first asynchronous FIFO control unit, the first asynchronous FIFO control unit profit are sent into as the data signal bus across voltage domain signal
With the originating party voltage domain clock signal, the data signal bus is sent to level conversion unit.
Preferably, level conversion unit is by across the voltage domain signal carry out level conversion, and will pass through level conversion
Across voltage domain signal the second asynchronous FIFO control unit is sent to as debit's voltage domain data signal bus.
Preferably, debit's voltage domain reads the debit using its clock signal from the second asynchronous FIFO control unit
Voltage domain data signal bus.
Preferably, the originating party voltage domain is CPU voltage domains or BIU voltage domains, and debit's voltage domain is BIU voltage domains
Or CPU voltage domains.
According to another aspect of the present invention, there is provided the device that a kind of data signal bus for supporting DVFS transmits, it is special
Sign is, including：
Originating party part, for by the use of originating party voltage domain clock signal send as across voltage domain signal number of buses it is believed that
Number；
Level conversion part, for across the voltage domain signal carry out level conversion by described in；
Debit's part, pass through across voltage domain letter described in level conversion for being received using debit's voltage domain clock signal
Number.
Preferably, the originating party voltage domain and/or debit's voltage domain are additionally operable to during transfer bus data-signal,
Carry out dynamic voltage frequency adjustment DVFS processing.
Preferably, the originating party part includes：
Originating party voltage domain unit, for during the transfer bus data-signal between originating party voltage domain and debit's voltage domain,
Originating party voltage domain send as the data signal bus across voltage domain signal into the first asynchronous FIFO control unit；
First asynchronous FIFO control unit, for utilize the originating party voltage domain clock signal, by the number of buses it is believed that
Number send to level conversion part.
Preferably, the level conversion part includes：
Level conversion unit, for will across voltage domain signal the carries out level conversion, and by process level conversion across
Voltage domain signal sends the second asynchronous FIFO control unit to as debit's voltage domain data signal bus.
Preferably, debit's part includes：
Second asynchronous FIFO control unit, for receive level conversion part transmission debit's voltage domain number of buses it is believed that
Number；
Debit's voltage domain unit, for being read using debit's voltage domain clock signal from the second asynchronous FIFO control unit
Take debit's voltage domain data signal bus.
Preferably, the originating party voltage domain is BIU voltage domains or BIU voltage domains, and debit's voltage domain is CPU voltage domains
Or CPU voltage domains.
Compared with prior art, the beneficial effects of the present invention are：
The present invention can realize the stable transmission of data high-speed between two voltage domains, relatively conventional asynchronous interface circuit
Timing closure is easier to, so as to lift stability and reliability of the whole system when dynamic electric voltage and frequency adjust.
Brief description of the drawings
Fig. 1 is the method flow diagram of support DVFS provided in an embodiment of the present invention data signal bus transmission；
Fig. 2 is support DVFS provided in an embodiment of the present invention simple SOC overall architecture schematic diagram；
Fig. 3 is support DVFS provided in an embodiment of the present invention dual core processor overall architecture schematic diagram；
Fig. 4 is the support DVFS provided in an embodiment of the present invention device block diagram for realizing data signal bus transmission；
Fig. 5 is the structural representation of the AXI passages of separation read-write transmission provided in an embodiment of the present invention；
Fig. 6 is the structural representation of asynchronous AXI interface circuits provided in an embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing to a preferred embodiment of the present invention will be described in detail, it will be appreciated that described below is excellent
Select embodiment to be merely to illustrate and explain the present invention, be not intended to limit the present invention.
Fig. 1 is the method flow diagram of support DVFS provided in an embodiment of the present invention data signal bus transmission, such as Fig. 1 institutes
Show, step includes：
Step 101, by the use of originating party voltage domain clock signal send be used as the data signal bus across voltage domain signal.Specifically
Ground is said, between originating party voltage domain and debit's voltage domain during transfer bus data-signal, originating party voltage domain will be used as across voltage
The data signal bus of domain signal is sent into the first asynchronous FIFO control unit, and the first asynchronous FIFO control unit utilizes the originating party
Voltage domain clock signal, the data signal bus is sent to level conversion unit.
Step 102, across the voltage domain signal carry out level conversion by described in.Specifically, first, level conversion unit is by institute
State across voltage domain signal carry out level conversion, and using by level conversion across voltage domain signal as debit's voltage domain number of buses
It is believed that number sending the second asynchronous FIFO control unit to.
Step 103, received and passed through described in level conversion across voltage domain signal using debit's voltage domain clock signal.Specifically
Say that debit's voltage domain reads debit's voltage domain bus using its clock signal from the second asynchronous FIFO control unit in ground
Data-signal.
In above-mentioned steps, the originating party voltage domain is the CPU voltage domains in chip, and debit's voltage domain is in chip
BIU voltage domains, the data signal bus include writing address signal, write data signal, read address signal；Or the originating party
Voltage domain is the BIU voltage domains in chip, and debit's voltage domain is the CPU voltage domains in chip, the data signal bus
Including reading data signal, write response signal.
Further, between originating party voltage domain and debit's voltage domain during transfer bus data-signal, originating party voltage domain
And/or debit's voltage domain can carry out dynamic voltage frequency adjustment DVFS processing.
Fig. 2 is support DVFS provided in an embodiment of the present invention simple SOC overall architecture schematic diagram, such as Fig. 2 institutes
Show, including three voltage domains：CPU voltage domains, BIU voltage domains and SOC voltage domains.The functional unit that the CPU voltage domains include
Mainly two CPU cores.The BIU voltage domains mainly include the function for realizing buffer consistency between two CPU cores
Unit and Bus Interface Unit, as shown in Figure 3.The SOC voltage domains include system AXI buses, AXI2APB bridgers, are
System clock generator and phaselocked loop.Three voltage domains correspond to three power supply units respectively outside SOC.The CPU
Voltage domain needs to realize Dynamic voltage scaling, so SOC is matched somebody with somebody by configuring interface to the power supply unit of CPU voltage domains
Put.The present invention relates between CPU voltage domains and BIU voltage domains by EBI realize data signal bus transmit technology,
Number of buses between logic realization CPU voltage domains and BIU voltage domains is handled by the cross clock domain in Fig. 3 and voltage domain it is believed that
Number transmission.
Because the SOC using DVFS all uses GALS framework substantially, that is, Global Asynchronous, local synchronization when
Bell structure.This structure is easy to the convergence of sequential and the lifting of performance, and work clock is independent between each voltage domain, it is not necessary to complete
The clock tree balance of office.So just need to use asynchronous interface circuit between two voltage domains, to ensure the correct of data transfer
Property.But the invention is not restricted to SOC, in other chips, as long as needing to use between CPU voltage domains and BIU voltage domains
Asynchronous interface circuit carries out the transmission of data signal bus, can use technical solutions according to the invention.
Fig. 4 is the device block diagram of support DVFS provided in an embodiment of the present invention data signal bus transmission, such as Fig. 4 institutes
Show, including the originating party portion of the data signal bus across voltage domain signal is used as being sent by the use of originating party voltage domain clock signal
Part, for by the level conversion part of across the voltage domain signal carry out level conversion and for using debit's voltage domain clock believe
Number debit's part across voltage domain signal Jing Guo level conversion is received, wherein：
The originating party part includes originating party voltage domain unit and the first asynchronous FIFO control unit, the originating party voltage domain list
For member between originating party voltage domain and debit's voltage domain during transfer bus data-signal, originating party voltage domain will be used as across voltage domain letter
Number data signal bus be sent into the first asynchronous FIFO control unit, the first asynchronous FIFO control unit utilizes the originating party
Voltage domain clock signal, the data signal bus is sent to level conversion part.
The level conversion part includes level conversion unit, and the level conversion unit enters described across voltage domain signal
Line level is changed, and sends second to as debit's voltage domain data signal bus across voltage domain signal using by level conversion
Asynchronous FIFO control unit.
Debit's part includes the second asynchronous FIFO control unit and debit's voltage domain unit, second asynchronous FIFO
Control unit receives debit's voltage domain data signal bus of level conversion part transmission, and debit's voltage domain unit utilizes receipts
Square voltage domain clock signal reads debit's voltage domain data signal bus from the second asynchronous FIFO control unit.
Further, the originating party voltage domain unit is CPU or BIU in SOC, and debit's voltage domain unit is
BIU or CPU in SOC, between CPU and BIU during transfer bus data-signal, CPU voltage domains and/or BIU voltage domains
DVFS operations can be carried out.
Further, the first asynchronous FIFO control unit and the second asynchronous FIFO control unit are in two voltages
Between domain, together with level conversion part, asynchronous AXI interface circuits, the function that the asynchronous AXI interface circuits are realized are realized
Including：
1st, the SOC EBIs of specific protocol are supported for realizing；
2nd, for carrying out data interaction between two asynchronous clocks.
In traditional SOC design, the interface between two different voltage domains is typically located by asynchronous interface
Reason, so does not allow to be also easy to produce sequence problem across the part of voltage domain.The present invention uses two asynchronous FIFOs by asynchronous AXI interfaces
Read-write transmission separate, clock zone and voltage domain are cut between two asynchronous FIFOs so that the number between two voltage domains
More stable according to transmission, interfaces frequency is higher, and timing closure is more prone to.Fig. 5 is separation provided in an embodiment of the present invention
The structural representation of the asynchronous AXI passages of transmission is read and write, as shown in figure 5, being initiated by CPU to exemplified by BIU transmission request, entirely
The workflow of EBI is as follows：
1st, CPU initiates to BIU transmission to ask, and bus protocol logic is using as the data signal bus across voltage domain signal
Access is got off, and is then fed into the asynchronous FIFO control unit of CPU side；
2nd, the asynchronous FIFO control unit of CPU side utilizes CPU voltage domain clock signals, will across the voltage domain signal process
The asynchronous FIFO control unit of BIU sides is given after level conversion unit；
3rd, BIU reads the asynchronous FIFO control unit of BIU sides using BIU voltage domains clock signal, will pass through level conversion
Be transformed into its clock zone across voltage domain signal, complete the transmitting procedure of whole data.
Above-mentioned data signal bus includes writing address signal, write data signal, reads address signal.
Likewise, if BIU initiates transmission request to CPU, the workflow of whole EBI is as follows：
1st, BIU initiates to CPU transmission to ask, and bus protocol logic is using as the data signal bus across voltage domain signal
Access is got off, and is then fed into the asynchronous FIFO control unit of BIU sides；
2nd, the asynchronous FIFO control unit of BIU sides utilizes BIU voltage domain clock signals, will across the voltage domain signal process
The asynchronous FIFO control unit of CPU side is given after level conversion unit；
3rd, CPU reads the asynchronous FIFO control unit of CPU side using CPU voltage domains clock signal, will pass through level conversion
Be transformed into its clock zone across voltage domain signal, complete the transmitting procedure of whole data.
The clock of asynchronous FIFO input logic part and the clock of bus logic part are same in conventional asynchronous interface circuit
One source, so need to do two-part timing unit Clock Tree in back-end realization, and to accomplish the balance of Clock Tree.
And for DVFS design, the clock tree balance carried out across voltage domain is difficult to accomplish, and due to both sides Clock Tree
Adhere to different voltage domains separately, signal is also bigger by delay jitter caused by Clock Tree, and very big be stranded is caused to timing closure
It is difficult.Contrasted with conventional asynchronous interface circuit, the advantage of the asynchronous AXI interface circuits used in the present invention is, originating party and the side of connecing
The asynchronous FIFO control logic of separation read-write transmission is respectively adopted, the clock of both sides is asynchronous clock.Fig. 6 is implementation of the present invention
The structural representation for the asynchronous AXI interface circuits that example provides, as shown in fig. 6, the whole asynchronous AXI that transmission is read and write by separating connects
Mouth circuit, carries out the transmission of data signal bus.The asynchronous AXI interface circuits integrally use asynchronous working method, are sent out with CPU
Exemplified by the transmission request for playing BIU, the workflow of the asynchronous AXI interface circuits is as follows：
1st, during CPU transmit a request to BIU, when cpu_valid signals are effective, data signal bus is given to CPU
The asynchronous FIFO control unit of side, its asynchronous FIFO control logic is utilized so as to the asynchronous FIFO control unit of the CPU side（I.e.
CPU write control logic）Carry out respective handling；
2nd, the asynchronous FIFO control unit of CPU side utilizes the asynchronous FIFO control logic, first determines whether its register
It is whether full, if non-full, it is effective to put cpu_ready signals by NOT gate, and by by cpu_valid signals and cpu_
For ready signals as the input with door, it is effective to put pushdata signals, then, will be across voltage domain signal using CPU_CLOCK
It is latched into the register.
In this process, the asynchronous FIFO control logic of CPU side needs to know register in asynchronous FIFO control unit
The read pointer of depth and asynchronous BIU sides judges the full state of FIFO sky, and a burst transfer of CPU side does not exceed asynchronous
The depth of register in FIFO control units, it otherwise can influence the performance of whole asynchronous interface circuit.As long as register less than,
CPU cans continue to send data signal bus, it is not necessary to wait the biu_ready signals of BIU sides.
3rd, level conversion unit is to across the voltage domain signal carry out level conversion of the CPU side, and is sent into the asynchronous of BIU sides
FIFO control units, its asynchronous FIFO control logic is utilized so as to the asynchronous FIFO control unit of BIU sides（That is BIU reads control and patrolled
Volume）Carry out respective handling；
4th, the asynchronous FIFO control unit of BIU sides utilizes its asynchronous FIFO control logic, judges whether its register is not empty,
If so, it is effective then to return to biu_valid signals；When the biu_ready of BIU sides is effective, by by biu_valid signals and
Popdata signals are set to effectively, so as to utilize BIU_CLOCK will be through over level by biu_ready signals as the input with door
Being read out across voltage domain signal from its register after conversion, that is, BIU clock zones are transformed into, complete a bus transfer.
For 5 passages of asynchronous AXI interfaces, because address and data are separately transmitted, for originating party, it is necessary to record current
The quantity of address is sent, when quantity is not zero, data channel could send data.
It is asynchronous during the super large-scale integration VLSI chip that the present invention can be widely applied to need to support DVFS designs
AXI interface circuits can be with steady operation under high frequency clock, the transmission efficient stable of data signal bus, and back-end realization is also easy
Reach timing closure, the relatively conventional asynchronous interface circuit change very little of the asynchronous interface circuit, easily realize.
Although the present invention is described in detail above, the invention is not restricted to this, those skilled in the art of the present technique
Various modifications can be carried out according to the principle of the present invention.Therefore, all modifications made according to the principle of the invention, all should be understood to
Fall into protection scope of the present invention.
Claims (12)
1. a kind of method that data signal bus for supporting DVFS transmits, it is characterised in that including：
Originating party part utilizes the originating party voltage domain clock signal asynchronous with debit's voltage domain clock, sends across voltage domain bus data
Signal；
Level conversion part receives across the voltage domain data signal bus, and across the voltage domain data signal bus is carried out
Level conversion；
Transceiver unit utilizes the debit voltage domain clock signal asynchronous with originating party voltage domain clock, receives the institute Jing Guo level conversion
State across voltage domain data signal bus.
2. according to the method for claim 1, it is characterised in that the transfer bus between originating party voltage domain and debit's voltage domain
During data-signal, originating party voltage domain and/or debit's voltage domain carry out dynamic voltage frequency adjustment DVFS processing.
3. according to the method for claim 2, it is characterised in that the transfer bus between originating party voltage domain and debit's voltage domain
During data-signal, across voltage domain data signal bus is sent into the first asynchronous FIFO control unit by originating party voltage domain, and first is different
Step FIFO control units utilize the originating party voltage domain clock signal, and across the voltage domain data signal bus is sent to level
Converting unit.
4. according to the method for claim 3, it is characterised in that level conversion unit will across the voltage domain number of buses it is believed that
Number carry out level conversion, and using across the voltage domain data signal bus Jing Guo level conversion as debit's voltage domain number of buses it is believed that
Number send the second asynchronous FIFO control unit to.
5. according to the method for claim 4, it is characterised in that debit's voltage domain is different from described second using its clock signal
Walk FIFO control units and read debit's voltage domain data signal bus.
6. according to the method described in claim 1-5 any one, it is characterised in that the originating party voltage domain is BIU voltage domains
Or CPU voltage domains, debit's voltage domain are CPU voltage domains or BIU voltage domains.
A kind of 7. device that data signal bus for supporting DVFS transmits, it is characterised in that including：
Originating party part, for utilizing the originating party voltage domain clock signal asynchronous with debit's voltage domain clock, send total across voltage domain
Line data-signal；
Level conversion part, for receiving across the voltage domain data signal bus, and will across the voltage domain number of buses it is believed that
Number carry out level conversion；
Debit's part, for utilizing the debit voltage domain clock signal asynchronous with originating party voltage domain clock, receive and turn through over level
Across the voltage domain data signal bus changed.
8. device according to claim 7, it is characterised in that the originating party voltage domain and/or debit's voltage domain are also
For during transfer bus data-signal, carrying out dynamic voltage frequency adjustment DVFS processing.
9. device according to claim 8, it is characterised in that the originating party part includes：
Originating party voltage domain unit, will be across for during the transfer bus data-signal between originating party voltage domain and debit's voltage domain
Voltage domain data signal bus is sent into the first asynchronous FIFO control unit；
First asynchronous FIFO control unit, will across the voltage domain number of buses for utilizing the originating party voltage domain clock signal
It is believed that number sending to level conversion part.
10. device according to claim 9, it is characterised in that the level conversion part includes：
Level conversion unit, for across the voltage domain data signal bus to be carried out into level conversion, and level conversion will be passed through
Across voltage domain data signal bus send the second asynchronous FIFO control unit to as debit's voltage domain data signal bus.
11. device according to claim 10, it is characterised in that debit's part includes：
Second asynchronous FIFO control unit, for receiving debit's voltage domain data signal bus of level conversion part transmission；
Debit's voltage domain unit, for reading institute from the second asynchronous FIFO control unit using debit's voltage domain clock signal
State debit's voltage domain data signal bus.
12. according to the device described in claim 7-11 any one, it is characterised in that the originating party voltage domain is BIU voltages
Domain or CPU voltage domains, debit's voltage domain are CPU voltage domains or BIU voltage domains.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310059075.2A CN104008076B (en) | 2013-02-25 | 2013-02-25 | The method and device that a kind of data signal bus for supporting DVFS transmits |
| PCT/CN2013/090729 WO2014127674A1 (en) | 2013-02-25 | 2013-12-27 | Method and device for transmitting bus data signal, supporting dvfs |
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| CN201310059075.2A CN104008076B (en) | 2013-02-25 | 2013-02-25 | The method and device that a kind of data signal bus for supporting DVFS transmits |
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| CN110636240B (en) * | 2019-08-19 | 2022-02-01 | 南京芯驰半导体科技有限公司 | Signal regulation system and method for video interface |
| CN111752875A (en) * | 2020-06-22 | 2020-10-09 | 深圳鲲云信息科技有限公司 | Inter-module communication method and system |
| CN113093899B (en) * | 2021-04-09 | 2022-03-22 | 思澈科技(上海)有限公司 | Cross-power domain data transmission method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101482762A (en) * | 2009-02-11 | 2009-07-15 | 华为技术有限公司 | Method and system for regulating CPU clock frequency |
| CN101741372A (en) * | 2008-11-11 | 2010-06-16 | 株式会社瑞萨科技 | Semiconductor integrated circuit and control method for clock signal synchronization |
| CN102103561A (en) * | 2009-12-01 | 2011-06-22 | 三星电子株式会社 | Asynchronous upsizing circuit in data processing system |
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| US8004922B2 (en) * | 2009-06-05 | 2011-08-23 | Nxp B.V. | Power island with independent power characteristics for memory and logic |
| US8395454B2 (en) * | 2011-05-13 | 2013-03-12 | Oracle International Corporation | Synchronized output of multiple ring oscillators |
| JP2013012003A (en) * | 2011-06-29 | 2013-01-17 | Renesas Electronics Corp | Data processing device and data processing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741372A (en) * | 2008-11-11 | 2010-06-16 | 株式会社瑞萨科技 | Semiconductor integrated circuit and control method for clock signal synchronization |
| CN101482762A (en) * | 2009-02-11 | 2009-07-15 | 华为技术有限公司 | Method and system for regulating CPU clock frequency |
| CN102103561A (en) * | 2009-12-01 | 2011-06-22 | 三星电子株式会社 | Asynchronous upsizing circuit in data processing system |
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| Publication number | Publication date |
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| WO2014127674A1 (en) | 2014-08-28 |
| CN104008076A (en) | 2014-08-27 |
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