JP2013012003A - Data processing device and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further reduce power consumption of a data processing device that performs DVFS control.SOLUTION: A data processing device (1) calculates: actual power amounts (Pr_0-Pr_3) consumed during a predetermined period in a data processing control unit (10) that performs data processing in synchronization with a clock signal (CLK); and assumed power amounts (Pf1_0-Pf1_3, Pf2_0-Pf2_3, Pf3_0-Pf3_3) when assuming operations during the predetermined period by the data processing control unit at assumed frequencies (f1-f3). The data processing device (1) selectively controls the frequency of the clock signal corresponding to a load state relating to the data processing, in consideration of the frequency that achieves lower power consumption among the calculated actual power amounts and assumed power amounts.

Description

  The present invention relates to a technique for reducing power consumption of a data processing apparatus and a data processing system, and more particularly to a technique effective when applied to a data processing apparatus having a function of dynamically controlling the frequency and power supply voltage of a clock signal. .

  In recent years, the performance of embedded devices controlled by program processing by a microprocessor has been increasing. Accordingly, the power consumption of the microprocessor tends to increase. Under such circumstances, an increasing number of microprocessors apply DVFS (Dynamic Voltage and Frequency Scaling) control, which is one of the techniques for reducing the power consumption of the microprocessors. DVFS control is a power management technique that dynamically controls the frequency and power supply voltage of a clock signal supplied to a processor core based on the load state of the processor core such as a CPU.

  As conventional DVFS control techniques, Patent Documents 1 to 4 disclose a method of calculating the CPU load for each task or process executed by the CPU and controlling the operating frequency and operating voltage. Further, although different from the above DVFS control, in Patent Document 5, in a physical server having a virtual server that is virtually generated by allocating CPU resources, the total load of the virtual server and the physical server A technique for controlling the CPU drive frequency based on the total amount of CPU resources is disclosed.

JP 2008-107944 A JP 2008-59556 A JP 2004-152068 A JP 2001-517332 A JP 2009-175788 A

  As shown in Patent Documents 1 to 5, in the DVFS control, the operating frequency and the operating voltage are set based on the load of the CPU or the like, but the power state of the CPU or the like according to the setting is not monitored. Therefore, even if the operating frequency and the operating voltage are set based on the load state of the CPU or the like by DVFS control, there is a possibility that the setting is not necessarily optimal in terms of power (for example, setting that minimizes power consumption). The inventor thought. Specifically, in a microprocessor having an operation mode such as a sleep mode in which supply of a clock signal to the CPU is stopped or a standby mode in which not only a clock signal but also power supply is stopped, an operation frequency based on a load state of the CPU If only the operating voltage is set, it may not always be in an optimal state in terms of power. For example, when the waiting time from the completion of one data processing to the start of the next data processing is long, the microprocessor shifts to the standby mode, and when it is short, the microprocessor shifts to the sleep mode. Consider a case where the standby mode assumes that the CPU consumes less power than the sleep mode. In DVFS control in such a microprocessor, for example, two setting states are conceivable: a low-speed setting in which the CPU lowers the operating frequency to execute data processing, and a high-speed setting in which the operating frequency is increased to execute data processing. In the case of the low-speed setting, the power consumption is smaller during the data processing than when the operation frequency is increased, but the time required for the data processing becomes longer as the operation frequency is decreased. As a result, the waiting time from the completion of one data processing to the start of the next data processing is shortened, and thereafter there is a possibility that the standby mode cannot be entered and the sleep mode may be entered. Power consumption during standby is greater than in mode. On the other hand, in the case of the high-speed setting, the power consumption is larger than when the operation frequency is lowered during the data processing, but the time required for the data processing is shortened due to the higher operation frequency. This increases the waiting time from the completion of data processing to the start of the next data processing, so it may be possible to shift to standby mode instead of sleep mode, in which case lower power consumption may occur. There is sex.

  In this way, considering not only the power consumption during data processing but also the power consumption during the period including the standby time after data processing, data processing with a lower operating frequency is performed when data processing is performed with a higher operating frequency. There is a possibility that the power consumption may be lower during the period than when executing. Therefore, in the microprocessor in which the sleep mode and the standby mode are selected and controlled according to the length of the standby time and the DVFS control is performed, the data processing time can be adjusted even if the operating frequency is adjusted based only on the CPU load state. The inventor of the present application considered that the optimum state in terms of power may not be obtained depending on the length of the standby time.

  An object of the present invention is to further reduce power consumption in a data processing apparatus that performs DVFS control.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the present data processing apparatus is configured such that the actual amount of power consumed in a predetermined period in the data processing control unit that executes data processing in synchronization with the clock signal and the predetermined period by the data processing control unit at the assumed frequency. The clock signal corresponding to the state of the load related to the data processing is calculated by calculating an assumed power amount when an operation is assumed, and taking into account the actual power amount and the frequency that results in low power consumption among the assumed power amount Select and control the frequency.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to this data processing device, it is possible to further reduce power consumption.

FIG. 1 is a block diagram illustrating a data processing system including a data processing apparatus according to this embodiment. FIG. 2 is an explanatory diagram illustrating an example of the unit power amount table 3044. FIG. 3 is an explanatory diagram showing an example of the processing time ratio table 3045. FIG. 4 is an explanatory diagram illustrating a correspondence relationship between the actual operation and the assumed operation of the CPU 10. FIG. 5 is another explanatory diagram showing a correspondence relationship between the actual operation and the assumed operation of the CPU 10. FIG. 6 is a flowchart showing an example of the flow of processing for calculating the actual power amount and the assumed power amount by the DVFS management module 30. FIG. 7 is a flowchart showing an example of a conversion time calculation process. FIG. 8 is an explanatory diagram showing an example of the operation timing of the data processing apparatus 1. FIG. 9 shows an example of the operation timing of the data processing apparatus according to the comparative example. FIG. 10 is an explanatory diagram illustrating power characteristics of the data processing device 1 and the data processing device according to the comparative example.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (Calculate the assumed power amount for each frequency setting assuming the power amount during actual operation and feed it back to the CPU)
A data processing device (1) according to a representative embodiment of the present invention executes data processing in synchronization with a clock signal (CLK), and based on the state of a load related to the data processing, A data processing control unit (10) for selecting and controlling the frequency, and an actual power amount (Pr_0 to Pr3) for a predetermined period (measurement count information 3042) consumed by the data processing control unit during actual operation of the data processing control unit. As well as calculating, calculate the assumed power amounts (Pf1_0 to Pf1_3, Pf2_0 to Pf2_3, Pf3_0 to Pf3_3) in the predetermined period during the assumed operation assuming the operation by the data processing control unit at the assumed frequency (f1 to f3). And a power calculation unit (30). The data processing control unit selectively controls the frequency of the clock signal corresponding to the state of the load in consideration of the frequency of low power consumption among the actual power amount and the assumed power amount.

  In the data processing device according to item 1, since the actual power amount in the predetermined period and the frequency that becomes low power consumption among the assumed power at the assumed frequency are determined, the current operating frequency of the data processing control unit is It is possible to determine whether the operating frequency is optimal for the data processing control unit. As a result, when the current operating frequency of the data processing control unit is not optimal in terms of power, it is possible to change to an operating frequency that can further reduce the power consumption of the data processing control unit.

[2] (Understanding the duration for each CPU operating state and calculating the power for each operating state)
2. The data processing apparatus according to item 1, wherein the operation state of the data processing control unit includes an active state in which data processing can be performed and an inactive state in which data processing cannot be performed, wherein the inactive state includes the data processing A first low power consumption state (sleep state) in which supply of the clock signal to the control unit is stopped, and a second low power consumption state (in which supply of the clock signal and power supply voltage to the data processing control unit is stopped) Standby state). The power calculation unit grasps the duration of the active state, the duration of the first low power consumption state, and the duration of the second low power consumption state during the actual operation and the assumed operation. The actual power amount and the assumed power amount are calculated based on the duration time and the power consumption amount per unit time in each operation state.

  In the data processing device according to item 2, since the three operation states in the predetermined period are distinguished and the electric energy is calculated in consideration of the duration of each operation state, the actual electric energy in the predetermined period and The estimated power amount can be calculated with higher accuracy.

[3] (Notification every time calculation is completed)
In the data processing device according to item 1 or 2, the power calculation unit notifies the data processing control unit that the calculation is completed each time the calculation of the actual power amount and the assumed power amount for the predetermined period is completed. Notify them.

  According to this, it can be determined at every predetermined period whether or not the current operating frequency of the data processing control unit is an optimal frequency in terms of power.

[4] (Calculate the amount of power every fixed period or every change in the CPU operating state)
In the data processing device according to item 2 or 3, the power calculation unit performs the data processing every predetermined period (the upper limit value of the timer set in the measurement time information 3041) or every change in the operation state of the data processing control unit. The actual power amount consumed by the control unit is calculated, and the actual power amount for the predetermined period is calculated by accumulating the calculated actual power amount for a predetermined number of times. Further, the power calculation unit calculates the assumed power amount for each calculation related to the actual power amount, and accumulates the calculated assumed power amount for the predetermined number of times to thereby calculate the virtual power amount in the predetermined period. Is calculated.

  According to this, it is possible to easily calculate the electric energy in consideration of the operation state in the predetermined period. In addition, even when the operation state of the data processing control unit does not change, the amount of power can be calculated for each predetermined period, so that the number of times the amount of power is calculated does not reach the predetermined number of times. It is possible to prevent the calculation of the amount of power during the predetermined period from being lost.

[5] (Calculation method of the actual measured electric energy for one time)
In the data processing device according to item 4, the actual power consumption for one time out of the predetermined number of times is the power consumption per unit time in the operation state of the data processing control unit (PA1 to PA3, PS1 to PS3, PB1 to PB3). ) And the first duration (Tc) indicating the duration of the operation state at the time of the actual operation in one time.

  According to this, it is possible to easily calculate the actual power amount for each operation state during the actual operation of the data processing control unit.

[6] (Calculation method of estimated power consumption for one time)
In the data processing device according to item 5, the assumed power consumption for one of the predetermined times is a power consumption per unit time (PA1 to PA3, PS1) in the operation state of the data processing control unit at the assumed frequency. ˜PS3, PB1 to PB3) and a second duration (Tv) indicating the duration of the operation state at the time of the assumed operation for one time.

  According to this, it is possible to easily calculate the assumed power amount for each operation state during the assumed operation of the data processing control unit.

[7] (Calculation of conversion time Tv (when active))
In the data processing device according to Item 6, when the operation state at the time of the assumed operation is the active state, the power calculation unit calculates the corresponding first duration time at the actual operation at the time of the assumed operation. It converts according to the data processing capability (r11-r13, r21-r23, r31-r33) of the said data processing control part in a frequency, and let the converted time be the said 2nd continuation time.

  As described above, if the data processing is executed with the clock signal frequency increased, the time required for the data processing is shortened. Conversely, if the data processing is executed with the frequency lowered, the time required for the data processing is increased. . That is, it can be said that the data processing capability is high when the frequency is high, and the data processing capability is low when the frequency is low. Therefore, in the data processing apparatus according to item 7, the duration of the active state in the current data processing control unit is used as a reference, and the duration is converted according to the data processing capability of the data processing control unit at the assumed frequency. Thus, the second duration time is calculated. According to this, the data processing time corresponding to the assumed frequency can be easily calculated.

[8] (Calculation of conversion time Tv (when inactive))
In the data processing device according to item 7, when the operation state of the data processing control unit at the time of the assumed operation is the active state, the power conversion unit is configured to perform the first duration with respect to the calculated second duration. When the operation state of the data processing control unit at the time of the assumed operation is the inactive state, the difference time (ΔT) indicating the difference between the first duration and the time is calculated. The second duration time is determined based on a time calculated by adding the accumulated difference time.

  As described above, when the operation state of the data processing control unit shifts from the active state to the inactive state, the duration in the subsequent inactive state varies depending on the length of the duration in the active state. Therefore, according to the data processing device of item 8, when the operation state of the data processing control unit is in the active state, the difference time is accumulated, and then the operation state of the data processing control unit is inactive. When the state is reached, the second duration time in the inactive state is determined using the accumulated difference time. As a result, the duration of the inactive state during the assumed operation can be calculated with higher accuracy.

[9] (Switching between sleep state and standby state according to conversion time Tv)
The power calculation unit in the data processing device according to item 8, wherein the second duration is greater than a predetermined threshold (Tth) when the operation state of the data processing control unit during the assumed operation is the inactive state. When the operation state of the data processing control unit during the assumed operation is assumed to be the second low power consumption state, and when the operation state is smaller than the predetermined threshold, the data processing control unit during the assumed operation Assuming that the operating state is the first low power consumption state, the assumed power is calculated.

  According to this, since the first low power consumption state and the second low power consumption state during the assumed operation are determined by themselves, the estimated power amount in the inactive state during the assumed operation is more accurately determined. Can be calculated.

[10] (Storage area for storing the calculated electric energy)
In the data processing device according to any one of Items 4 to 9, the power calculation unit includes first power information (3065) based on the calculated actual power amount for each predetermined period, and the calculated for each predetermined period. Storage area (3062) for storing second power information (3066 to 3068) based on the assumed power amount. The storage area can be accessed by the data processing control unit.

[11] (Stores information on cumulative power difference)
In the data processing device according to item 10, the power calculation unit selects the smallest power amount from the actual power amount and the assumed power amount, and calculates a power amount indicating a difference between the selected power amount and the actual power amount. The information cumulatively added for the predetermined number of times is stored in the storage area as the first power information, and the power amount indicating the difference between the selected power amount and the assumed power amount is cumulatively added for the predetermined number of times. The second power information is stored in the storage area.

  According to this, for example, the amount of data to be stored can be reduced compared to the case where the calculated actual power amount and the assumed power amount for each predetermined period are stored in the storage area. Thereby, since the capacity of the storage area can be reduced, for example, when the data processing device is formed on a semiconductor substrate, it contributes to a reduction in the area of the semiconductor substrate.

[12] (Stores difference information of accumulated power difference)
In the data processing device according to item 10, the power calculation unit selects the smallest power amount among the actual power amount and the assumed power amount for each predetermined period or for each change in the operation state of the data processing control unit. And calculating a first differential power amount (3053) indicating a difference between the selected power amount and the actual power amount, and a second differential power amount indicating a difference between the selected power amount and the assumed power amount ( 3054-3056). In addition, the power calculation unit adds the first difference power amount calculated last time and the first difference power amount calculated this time to calculate a cumulative difference power amount related to the actual power amount. The calculated second differential power amount and the currently calculated second differential power amount are added to calculate a cumulative differential power amount related to the assumed power amount. Further, the power calculation unit selects the smallest power amount among the cumulative difference power amount related to the actual power amount and the cumulative difference power amount related to the assumed power amount, and relates to the selected power amount and the actual power amount. A power amount indicating a difference from the cumulative power difference amount is stored in the storage area as the first power information (3065), and a power indicating a difference between the selected power amount and the cumulative power difference amount related to the assumed power amount. The amount is stored in the storage area as the second power information (3066 to 3068).

  According to this, by making the first power information and the second power information into information on the amount of power obtained by taking a difference with respect to the amount of power of the cumulative difference, the data amount can be further reduced. Can do. Thereby, the capacity of the storage area can be further reduced.

[13] (Power calculation using a table)
Item 12. The data processing device according to any one of Items 9 to 12, wherein the power calculation unit includes an amount of power per unit time (PA1 to PA3, PS1 to PS3, PB1 to PB3) according to the operation state of the data processing control unit. Is stored corresponding to each frequency that can be assumed, the data processing capability of the data processing control unit at the frequency related to the actual electric energy, and the assumed frequency A second table (3045) in which information (r11 to r13, r21 to r23, r31 to r33) indicating a ratio to the data processing capability of the data processing control unit is stored for each assumed frequency. . The power calculation unit calculates the actual power amount and the assumed power amount based on the values of the first table and the second table.

  According to this, for example, the actual power amount can be easily calculated without actually measuring the current flowing through the data processing control unit, the supplied voltage, or the like.

[14] (System)
A data processing system (100) according to a representative embodiment of the present invention operates with a first semiconductor device (2) that outputs a power supply voltage in response to an instruction from the outside, and power supply from the first semiconductor device. And a second semiconductor device (1). In the data processing system, the second semiconductor device executes data processing in synchronization with a clock signal (CLK) and selects a frequency and a power supply voltage of the clock signal based on a load state related to the data processing. A data processing control unit (10) for controlling, a clock generation unit (20) for generating and outputting the clock signal based on control by the data processing control unit, and the data processing during actual operation of the data processing control unit The actual power amount (Pr_0 to Pr_3) consumed by the control unit for a predetermined period is calculated, and the assumed power amount (Pf1_0) for the predetermined period at the time of the assumed operation assuming the operation by the data processing control unit at the assumed frequency. ~ Pf1_3, Pf2_0 to Pf2_3, Pf3_0 to Pf3_3), and a power calculation unit (60). That. The data processing control unit selectively controls the frequency of the clock signal corresponding to the state of the load in consideration of the frequency with low power consumption among the actual power amount and the assumed power amount, and the selected frequency The first semiconductor device is instructed to supply the power supply voltage according to the above.

  According to the data processing system, as in item 1, it is possible to determine whether or not the current operating frequency in the data processing control unit is an optimal operating frequency in terms of power for the data processing control unit. . As a result, when the operating frequency in the data processing control unit is not optimal, it is possible to change to an operating frequency that can further reduce the power consumption of the data processing control unit.

2. Details of Embodiments Embodiments will be further described in detail.

≪Data processing system configuration≫
FIG. 1 illustrates a data processing system including a data processing apparatus according to this embodiment. In the data processing system 100 shown in the figure, the data processing apparatus 1 is not particularly limited, but a plurality of circuit modules such as a CPU and peripheral circuit modules are made of one single crystal silicon by a known CMOS integrated circuit manufacturing technique. This is a system LSI (SOC: System on Chip) formed on such a semiconductor substrate.

  The data processing apparatus 1 receives supply of the power supply voltage VDD from the power supply IC 2 through the external power supply terminal. The power supply IC 2 is a power generation circuit that generates a power supply voltage based on the input voltage VIN, for example, and supplies the generated power supply voltage to the data processing device 1, the external memory (MRY) 3, and the crystal oscillator (TCXO) 4. is there. The data processing apparatus 1 instructs the power supply IC 2 to supply a desired power supply voltage VDD by the control signal 11, and the power supply IC 2 generates and outputs a voltage according to the instruction. As a result, the power supply voltage VDD having the voltage value instructed from the data processing device 1 is supplied to the data processing device 1. The external memory 3 is an external storage device having a volatile storage area such as an SDRAM or an external storage device having a nonvolatile storage area such as a flash memory.

  The data processing device 1 is not particularly limited, and includes a central processing unit (CPU) 10, a clock signal generation unit (CPG) 20, a DVFS management module 30, and other peripheral circuit modules not shown.

  The clock signal generation unit 20 generates a clock signal based on the reference clock signal output from the crystal oscillator 4 and supplies the generated clock signal to the CPU 10 and other peripheral circuit modules. The clock signal generation unit 20 includes, for example, a PLL (Phase Locked Loop) circuit, a frequency divider, and the like, and can generate clock signals having a plurality of types of frequencies. FIG. 1 typically illustrates a case where the clock signal CLK among the generated clock signals is supplied to the CPU 10. When the control signal 12 from the CPU 10 instructs the clock signal generation unit 20 to supply the clock signal CLK having a desired frequency, the clock signal generation unit 20 generates the clock signal CLK having a frequency corresponding to the instruction and outputs the clock signal CLK to the CPU 10. . Further, the clock signal generation unit 20 outputs a clock state signal Vsc indicating the frequency of the clock signal CLK supplied to the CPU 10 to the DVFS management module 30.

  The CPU 10 performs various data processing by executing program processing based on software stored in a storage device such as a ROM (Read Only Memory) (not shown) or the external memory 3.

  The operation state of the CPU 10 includes, for example, an active state and an inactive state, and the inactive state includes a sleep state and a standby state. The active state is a state in which data processing can be performed. For example, the clock signal CLK and the power supply voltage VDD are both supplied to the CPU 10. On the other hand, the inactive state is a state where data processing cannot be performed. The sleep state is a state where supply of the clock signal CLK to the CPU 10 is stopped, for example, and the standby state is a state where supply of the clock signal CLK and the power supply voltage VDD to the CPU 10 is stopped, for example. For example, the supply of the power supply voltage VDD is stopped when the supply of the power supply voltage VDD from the power supply IC 2 is stopped or when the supply of the power supply voltage VDD is stopped inside the chip by a power switch (not shown). Etc. In the standby state, not only the clock signal CLK but also the supply of the power supply voltage VDD is stopped as described above, so that the power consumption is lower than that in the sleep state. Cost.

  The transition from the active state of the CPU 10 to the inactive state (sleep state or standby state) is realized by the following control. For example, the CPU 10 calculates a standby time from the completion of one data process to the start of the next data process, and shifts from the active state to the standby state when the standby time is long. Conversely, when the waiting time is short, the state shifts from the active state to the sleep state. Whether to shift to the standby state or the sleep state is determined, for example, by comparing the calculated waiting time with a predetermined threshold value Tth. For example, when the calculated standby time is equal to or greater than the threshold value Tth, the CPU 10 shifts to a standby state, and when it is smaller than the threshold value Tth, the CPU 10 shifts to a sleep state. The operating state of the CPU 10 is notified to a peripheral circuit module such as the DVFS management module 30 by a standby state signal Vsb and a sleep state signal Vsp output from the CPU 10. For example, the standby state signal Vsb is asserted when the CPU 10 is in the standby state, and the sleep state signal Vsp is asserted when the CPU 10 is in the sleep state. When the standby state signal Vsb and the sleep state signal Vsp are both negated, the CPU 10 is in an active state.

  In addition to the control for switching the operation state according to the standby time, the CPU 10 monitors the state of the load related to the data processing to be executed, and performs DVFS control for adjusting the operation voltage and the operation frequency of the CPU 10 according to the load state. Specifically, the CPU 10 grasps the state of a load related to data processing from a queue of tasks and processes to be executed. For example, when the load state changes from a low load state to a high load state, the clock signal generation unit 20 is instructed to increase the frequency of the clock signal, and the power supply IC 2 has the changed frequency. It is instructed to supply a power supply voltage (higher power supply voltage) corresponding to On the other hand, for example, when the load state changes from a high load state to a low load state, the CPU 10 instructs the clock signal generation unit 20 to lower the frequency of the clock signal and also changes the power supply IC 2 after the change. It is instructed to supply a power supply voltage (lower power supply voltage) corresponding to the frequency of.

  As described above, even if the operating frequency is adjusted using only the load state of the CPU 10 as a determination criterion, there is a possibility that the optimum state in terms of power may not be obtained depending on the length of the data processing time and the standby time. Therefore, in the data processing device 1 according to the present embodiment, the DVFS management module 30 assumes the actual power amount during the actual operation of the CPU 10 and the assumed power amount during the assumed operation assuming the operation of the CPU 10 at the assumed operating frequency. Based on the calculated actual power amount and the assumed power amount, it is determined whether or not the current setting of the operating frequency of the CPU 10 is optimal in terms of power. For example, if the CPU 10 determines that the other frequency settings have lower power consumption than the current frequency setting, the CPU 10 changes the setting of the operating frequency in consideration of the load state related to data processing.

≪Overview of DVFS management module≫
The DVFS management module 30 calculates the actual power amount consumed by the CPU 10 during the actual operation of the CPU 10 and also assumes the assumed power amount during the predetermined operation during the assumed operation assuming the operation of the CPU 10 at the assumed operating frequency. Is calculated. The DVFS management module 30 includes, for example, a detection unit 301, a monitor unit 302, a calculation unit 303, a basic data unit 304, a power difference generation unit 305, and an accumulation unit 306.

  The detection unit 301 detects the operation state (active state, sleep state, and standby state) and the operation frequency of the CPU 10 based on the sleep state signal Vsp, the standby state signal Vsb, and the clock state signal Vsc, and outputs a detection result. . For example, the detection unit 301 includes a sleep state change detection unit 3011, a standby state change detection unit 3012, and a clock signal change detection unit 3013. The clock signal change detection unit 3013 monitors the clock state signal Vsc and outputs a signal indicating the setting of the frequency of the clock signal CLK. The sleep state change detection unit 3011 monitors the sleep state signal Vsp, outputs a signal indicating whether or not the CPU 10 is in the sleep state, and outputs a signal corresponding to the change in the sleep state signal Vsp. The standby state change detection unit 3012 monitors the standby state signal Vsb, outputs a signal indicating whether or not the CPU 10 is in the standby state, and outputs a signal corresponding to the change in the standby state signal Vsb. Hereinafter, the signal according to the change in the sleep state signal Vsp and the signal according to the change in the standby state signal Vsb are also collectively referred to as a change detection signal 13. The change detection signal 13 is a signal whose signal level is switched between a high level and a low level each time the sleep state signal Vsp and the standby state signal Vsb change, for example.

  The monitor unit 302 generates data (hereinafter, also referred to as “element profile”) indicating the current state of the CPU 10 based on the signal output from the detection unit 301, and changes every time the change detection signal 13 changes (CPU 10). The generated element profile is output to the calculation unit 303 every time a predetermined period elapses).

  The element profile includes, for example, CPU status information 3021, DVFS status information 3022, and duration information 3023.

  The CPU status information 3021 is information indicating an operation state of the CPU 10, and is information indicating any of the active state, the sleep state, and the standby state, for example.

  The DVFS status information 3022 is information indicating the frequency setting of the CPU 10. For example, when there are three frequency settings of the first frequency (f1), the second frequency (f2), and the third frequency (f3) as the operating frequency of the CPU 10 that can be set by DVFS control, any one of the three frequencies It is information indicating settings.

  The duration information 3023 is information indicating a time from when the change detection signal 13 changes to the next change, or a time indicating the predetermined period (hereinafter referred to as a duration Tc). Specifically, the duration 3023 is a time measured when the monitor unit 302 uses a timer provided therein to measure the change detection signal 13 as a trigger. For example, the monitor unit 302 causes the timer to count the time from when the change detection signal 13 changes until the next change, and sets the measured count value as the duration time Tc. Further, when the predetermined period elapses before the next change of the change detection signal 13 occurs after the monitor unit 302 starts counting, the monitor unit 302 displays a count value indicating the predetermined period as a duration time. Let Tc. The predetermined period is, for example, an upper limit value of a timer set in measurement time information 3041 of the basic data unit 304 described later. The count value of the timer is reset every time the monitor unit 302 outputs the element profile (CPU status information 3021, DVFS status information 3022, duration information 3023). As a result, the timer repeats timing every time the change detection signal 13 changes or every time the predetermined period elapses.

  A specific operation of the monitor unit 302 will be described. For example, when the operating frequency of the CPU 10 is the first frequency (f1), when the operating state of the CPU 10 is switched from the active state to the standby state, information indicating the standby state is written in the CPU status information 3021 and the DVFS status information 3022 is displayed. Is written with information indicating the first frequency (f1). Further, the timer starts measuring time with the switching of the operation state as a trigger. After that, when the operation state of the CPU 10 is switched to the active state, the monitor unit 303 writes the count value of the timer at that time in the duration information 3023 as the duration time Tc, and the CPU status information 3021, DVFS status information 3022, and continuation The element profile including the time information 3023 is output to the calculation unit 303. Thereafter, the monitor unit 303 resets the timer and restarts timing, and writes information indicating the active state in the CPU status information 3021. When the predetermined time elapses before the operation state of the CPU 10 changes after the timer starts measuring time, the monitor unit 303 displays the count value of the timer (or the upper limit value of the timer set in the measurement time information 3041). ) As the duration Tc, and the element profile including the CPU status information 3021, the DVFS status information 3022, and the duration information 3023 is output to the computing unit 303. Thereafter, the monitor unit 303 resets the timer and restarts timing. Through the above processing, the element profile is generated every time the operating state of the CPU 10 changes or every time a predetermined period elapses, and is output to the calculation unit 303.

  The calculation unit 303 performs a calculation for calculating the actual power amount consumed by the CPU 10 and the assumed power amount during the assumed operation. The calculation is realized by a program process using, for example, a DSP (Digital Signal Processor). The calculation unit 303 calculates the actual power amount and the assumed power amount each time the element profile is given from the monitor unit 302. Specifically, when the element profile is given, the calculation unit 303 calculates the power consumption of the CPU 10 in the operation state and frequency setting according to the element profile as the actual power amount 3031 and the settable clock signal. An assumed power amount is calculated for each CLK frequency (operating frequency) and output to the power difference generation unit 305. For example, when three frequency settings of the first frequency (f1), the second frequency (f2), and the third frequency (f3) are possible as the setting of the operating frequency of the CPU 10, it is assumed that the first frequency is set. The power amount 3032, the assumed power amount 3033 when the second frequency is set, and the assumed power amount 3034 when the third frequency is set are calculated. A detailed calculation method of the actual power amount and the assumed power amount will be described later.

  The basic data unit 304 stores initial setting data serving as a reference for calculating the amount of power by the DVFS management module 30. For example, the initial setting data is stored in a ROM in the data processing apparatus 1 at the time of manufacture. For example, when the data processing apparatus 1 is turned on and the reset state is released, the CPU 10 reads the initial setting data from the ROM and sets it in the basic data unit 304. The basic data unit 304 is a register group including a plurality of registers, for example. In the basic data unit 304, for example, measurement time information 3041, threshold information 3043, measurement frequency information 3042, a unit power amount table 3044, and a processing time ratio table 3045 are stored as initial setting data.

  As described above, the measurement time information 3041 is information for determining the upper limit value of the timer of the monitor unit 303. The threshold information 3043 is information indicating the value of the threshold Tth described above.

  The measurement frequency information 3042 is information for determining how often the DVFS management module 30 feeds back the power state of the CPU 10 under the DVFS control to the CPU 10. Specifically, the DVFS management module 30 notifies the CPU 10 of the completion of power calculation when the calculation and accumulation of the amount of power for the number of times set in the measurement number information 3042 is completed. Therefore, the smaller the value of the number of measurements set in the number-of-measurements information 3042, the higher the frequency of feedback to the CPU 10.

  The unit power amount table 3044 is a look-up table in which the power consumption amount per unit time for each frequency setting of the CPU 10 by DVFS control is stored for each operation state of the CPU 10. Details of the table will be described later.

  The processing time ratio table 3045 stores the value of the processing time ratio according to the ratio between the data processing capability of the CPU 10 at the operating frequency during actual operation and the data processing capability of the CPU 10 at the operating frequency during assumed operation. Lookup table. Details of the table will be described later.

  The power difference generation unit 305 detects the smallest power amount among the plurality of given power amount data, and calculates the difference power amount representing the difference between the detected power amount and the plurality of power amounts at the time of actual operation and It is generated for each frequency setting during the assumed operation and is output to the accumulating unit 306. Specifically, the power difference generation unit 305 includes a comparison unit 3051 and a difference calculation unit 3052. For example, the comparison unit 3051 detects the smallest power amount (minimum power amount) among the actual power amount 3031 and the assumed power amount 3032 to 3034 given from the calculation unit 303. The difference calculation unit 3052 has a difference power amount 3053 during actual operation that represents the difference between the minimum power amount and the actual power amount 3031 and an assumed operation time (f1) that represents the difference between the minimum power amount and the assumed power amount 3032. Difference power amount 3054, difference power amount 3055 in the assumed operation (f2) representing the difference between the minimum power amount and the assumed power amount 3033, and assumed operation representing the difference between the minimum power amount and the assumed power amount 3034 Difference electric energy 3056 of time (f3) is generated. The process of generating the difference power amounts 3053 to 3056 is performed every time the actual power amount and the assumed power amount are output from the calculation unit 303 (every time the operation state of the CPU 10 changes or every predetermined period elapses).

  Further, the power difference generation unit 305 cumulatively adds the difference power amounts 3053 to 3056 generated every time the operation state of the CPU 10 changes or a predetermined period elapses, so that the accumulated difference power amount during actual operation is obtained. Difference information 3065 and accumulated difference power amount difference information 3066 to 3068 during the assumed operation are generated and output to the accumulation unit 306. Note that a detailed method for generating the difference information 3065 to 3068 of the accumulated difference power amount will be described later.

  The accumulating unit 306 includes an accumulated power storage unit 3062, a notification unit 3063, and a counter 3064. The accumulated power storage unit 3062 includes a storage area for storing accumulated difference power amount difference information 3065 to 3068 for each frequency setting during actual operation and assumed operation.

  The counter 3064 counts the number of times the difference power amounts 3053 to 3056 are cumulatively added, and gives the count value to the notification unit 3063. When the count value of the counter 3064 matches the value of the number of times set as the number-of-times information 3042 in the basic data unit 304, the notification unit 3063 notifies the CPU 10 that the calculation of the electric energy has been completed. The CPU 10 that has received the notification refers to the actual power amount calculated by accessing the cumulative power storage unit 3062 and the assumed power amount, and determines the frequency setting that results in lower power consumption. It is determined whether the frequency setting is optimal in terms of power.

≪Calculation of electric energy≫
A method of calculating the actual power amount and the assumed power amount will be described in detail.

(1) Calculation method of actual power amount The actual power amount is calculated by multiplying the power consumption amount per unit time in the operation state during the actual operation of the CPU 10 by the duration time Tc of the operation state. First, upon receiving the element profile from the monitor unit 302, the calculation unit 303 accesses the basic data unit 304 and refers to the unit power amount table 3044 per unit time corresponding to the CPU status information 3021 and the DVFS status information 3022. Read the power consumption of.

  FIG. 2 is an explanatory diagram illustrating an example of the unit power amount table 3044. As shown in the figure, the unit power amount table 3044 stores the power consumption per unit time for each frequency of the CPU 10 that can be set by the DVFS control for each operation state of the CPU 10. In the figure, as an example, power consumption per unit time for each of three operation states (active state, sleep state, and standby state) at three frequency settings (f1 to f3) is shown. For example, as illustrated in FIG. 2, when the operation state of the CPU 10 during the actual operation is an active state and the operation frequency is the first frequency, the calculation unit 303 reads the parameter PA1. Further, when the operation state of the CPU 10 during the actual operation is the sleep state and the operation frequency is the second frequency, the calculation unit 303 reads the parameter PS2.

  The computing unit 303 calculates the actual power amount by multiplying the read power consumption parameter by the duration Tc included in the duration information 3023. That is, the actual power amount Pr is expressed by an equation (Pr = Pn × Tc). Note that Pn is the amount of power per unit time (for example, 1 mW / s) and is one of the parameters PA1 to PA3, PS1 to PS3, and PB1 to PB3 shown in FIG. As described above, the duration Tc is information on the time from when the change detection signal 13 changes to the next change or the time indicating the predetermined period, and is included in the duration information 3023 of the element profile. . For example, when the operation state of the CPU 10 during the actual operation is a standby state of the period 4T and the operation frequency is the third frequency, the actual electric energy Pr = Pn × Tc = PB3 × 4T.

(2) Calculation method of assumed electric energy The said assumed electric energy is calculated by multiplying the consumed electric energy per unit time in the operation state at the time of assumption operation | movement of CPU10, and conversion time Tv in the operation state. .

(I) Assumed power amount in active state First, the case where the CPU status information 3021 is in the active state will be described.

  When the CPU status information 3021 received from the monitor unit 302 is information indicating an active state, the calculation unit 303 calculates the conversion time Tv based on the processing time ratio table 3045 and calculates the difference time ΔT.

  FIG. 3 shows an example of the processing time ratio table. As shown in the figure, in the processing time ratio table 3045, the processing time ratio indicating the data processing capability at the operating frequency at the assumed operation to the data processing capability at the operating frequency at the actual operation of the CPU 10 is set for each frequency setting. Stored in For example, the first frequency f1 = f, the second frequency f2 = 2f, the third frequency f3 = 4f, and the processing time when the CPU 10 executes data processing of a predetermined amount of data at the first frequency f1 during actual operation is “ 1 ”. In this case, as shown in FIG. 3, if the frequency at the assumed operation is the first frequency f1, the processing time ratio when the same data processing as that at the actual operation is executed is “r11 (= 1)”. . On the other hand, if the frequency at the assumed operation is the second frequency f2, the processing time ratio when the same data processing as that at the actual operation is executed is “r12 (= 0.5)”, and the frequency at the assumed operation is the first frequency. If the frequency is 3 f3, the processing time ratio when the same data processing as in the actual operation is executed is “r13 (= 0.25)”. Therefore, the conversion time Tv in the active state at the time of the assumed operation is expressed by the equation (Tv = Tc × rn). Here, rn is any parameter among r11 to r13, r21 to r23, and r31 to r33. For example, when the state of the CPU 10 during the actual operation is the first frequency setting (f1) and the active state during the period 4T, and the frequency setting during the assumed operation is the third frequency setting (f3), the conversion time Tv is Tv = Tc × r13 = 4T × 0.25 = 1T.

  The computing unit 303 refers to the unit power amount table 3044, reads out the parameter of the power consumption per unit time corresponding to the assumed frequency setting and the operating state, and multiplies the read parameter by the calculated conversion time Tv. Thus, the assumed power amount is calculated. That is, the assumed power amount Pfn in the active state is expressed by an expression (Pfn = Pn × Tv). For example, when the state of the CPU 10 during the actual operation is the first frequency setting (f1) and the active state for the period 4T, and the frequency setting during the assumed operation is the third frequency setting (f3), the assumed power consumption Pfn = PA3 × 1T.

  As described above, the processing time (converted time Tv) in the active state at the time of the assumed operation varies depending on the frequency setting. Therefore, the variation affects the duration of the next operation state. Therefore, the calculation unit 303 calculates a difference time ΔT that represents the difference between the active state duration Tc during actual operation and the corresponding operation state conversion time Tv during assumed operation.

  When the CPU status information 3021 is in the active state, the difference time ΔT is, for example, a value obtained by subtracting the duration Tc of the active state during actual operation and the corresponding conversion time Tv of the active state during assumed operation. Is calculated by adding the difference time accumulated in (hereinafter also referred to as accumulated difference time) T0. That is, the difference time ΔT in the active state is expressed by the equation (ΔT = T0 + Tc−Tv). For example, when the state of the CPU 10 during the actual operation is the first frequency setting and the active state during the period 4T, the frequency setting during the assumed operation is the third frequency setting, and the accumulated difference time T0 = 2T, the difference time ΔT ΔT = 2T + 4T-1T = 5T.

  When calculating the difference time ΔT, the method is not limited to the method of subtracting the converted time Tv from the continuous time Tc, but may be a method of subtracting the continuous time Tc from the converted time Tv.

(Ii) Assumed power amount in inactive state Next, a case where the CPU status information 3021 is in an inactive state (sleep state or standby state) will be described. When the CPU status information 3021 is in an inactive state, the calculation unit 303 calculates a conversion time Tv based on the accumulated difference time T0 and the duration Tc during actual operation.

  For example, when the value obtained by adding the accumulated difference time T0 and the duration time Tc during actual operation is smaller than “0”, the calculation unit 303 sets the conversion time Tv = 0 and the difference time ΔT by the equation (ΔT = T0 + Tc). Represent. On the other hand, when the value obtained by adding the accumulated difference time T0 and the duration time Tc in actual operation is “0” or more, the calculation unit 303 represents the conversion time Tv by the equation (Tv = T0 + Tc), and the difference time ΔT = 0.

  The computing unit 303 refers to the unit power amount table 3044, reads out the parameter of the power consumption per unit time corresponding to the assumed frequency setting and the operating state, and multiplies the read parameter by the calculated conversion time Tv. Thus, the assumed power amount in the inactive state is calculated. That is, the assumed power amount Pfn in the inactive state is calculated by the equation (Pfn = Pn × Tv).

  Next, a specific calculation method of the actual power amount and the assumed power amount will be described with reference to FIGS.

(3) Specific examples of actual power consumption and assumed power consumption (Fig. 4)
FIG. 4 is an explanatory diagram illustrating a correspondence relationship between the actual operation and the assumed operation of the CPU 10. (A) of the figure shows the change in the operating state during the actual operation of the CPU 10 and the duration Tc in each operating state. (B) of the same figure shows the change of the operation state at the time of the assumed operation in which the operation frequency of the CPU 10 is the first frequency (f1) and the conversion time Tv of each operation state. (C) of the figure shows a change in the operation state at the time of the assumed operation with the operation frequency of the CPU 10 as the second frequency (f2) and a conversion time Tv of each operation state. (D) of the same figure shows the change of the operation state at the time of the assumed operation in which the operation frequency of the CPU 10 is the third frequency (f3) and the conversion time Tv of each operation state. In the following description including this figure, it is assumed that f1 = f, f2 = 2f, and f3 = 4f, and the standby time threshold value Tth for entering the standby state is 5T.

(I) Actual power amount As shown in FIG. 5A, the operation state of the CPU 10 during actual operation changes in the order of the standby state 400, the active state 401, the sleep state 402, and the active state 403, and continues for each. It is assumed that the time Tc is 5T, 4T, 4T, 4T. Further, it is assumed that the operating frequency of the CPU 10 in the standby state 400 is the third frequency (f3) and the operating frequency of the CPU 10 in the other operating states 401 to 403 is the first frequency (f1). At this time, the real power amount Pr_0 = PB3 × 5T in the standby state 400, the real power amount Pr_1 = PA1 × 4T in the active state 401, the real power amount Pr_2 = PS1 × 4T in the sleep state 402, and the real power amount Pr_3 in the active state 403 = PA1 × 4T.

  The operation state at the time of the assumed operation ((B) to (D) in FIG. 4) changes in the same way as the operation state at the actual operation, but the time during which each operation state at the assumed operation continues is the assumed operation frequency. It depends on. The assumed electric energy in each of FIGS. (B) to (D) is as follows.

(Ii) Assumed electric energy of frequency setting f1 As shown in FIG. 4B, a period 410 corresponding to the standby state 400 is a standby state period in which the CPU 10 does not execute data processing. Therefore, assuming that the accumulated difference time T0 = 0, the value obtained by adding the accumulated difference time T0 and the duration time Tc (= 5T) of the standby state 400 during actual operation is 5T, which is 0 or more. Tv = T0 + Tc = 5T. At this time, the difference time ΔT is 0, and the assumed power amount Pf1_0 = PB1 × 5T.

  Next, a period 411 corresponding to the active state 401 is an active state period in which the CPU 10 can execute data processing, and the frequency setting coincides with the frequency setting (f1) in actual operation. Therefore, the conversion time Tv = Tc × r11 = 4T × 1 = 4T. At this time, the difference time ΔT = 0, and the assumed power amount Pf1_1 = PA1 × 4T.

  Hereinafter, the conversion time Tv of the periods 412 and 413 can be calculated in the same manner, and the assumed power amount Pf1_2 = PS1 × 4T of the period 412 and the assumed power amount Pf1_3 = PA1 × 4T of the period 413 are obtained. Is also 0.

(Iii) Assumed electric energy of frequency setting f2 As shown in FIG. 4C, the period 420 corresponding to the standby state 400 is a period of the standby state in which the CPU 10 does not execute data processing. Therefore, if the accumulated difference time T0 is 0, the value obtained by adding the accumulated difference time T0 and the duration time Tc (= 5T) of the standby state 400 during actual operation is 5T, which is 0 or more. Tv = T0 + Tc = 5T. At this time, the difference time ΔT is 0, and the assumed power amount Pf2 — 0 = PB2 × 5T.

  A period 421 corresponding to the active state 401 is an active period during which the CPU 10 can execute data processing, and the frequency setting is the frequency f2. Therefore, the conversion time Tv = Tc × r12 = 4T × 0.5 = 2T from the processing time ratio table 3045 in FIG. At this time, the difference time ΔT = T0 + Tc−Tv = 0 + 4T−2T = 2T, and the assumed power amount Pf2_1 = PA2 × 2T.

  A period 422 corresponding to the sleep state 402 is a period in an inactive state in which the CPU 10 does not execute data processing. Here, the duration Tc of the sleep state 402 is 4T, but since the previous period 421 is shortened compared to the actual operation time, it is possible to allocate the reduced time as the period of the inactive state. It becomes. That is, the value obtained by adding the accumulated difference time T0 and the duration time Tc (= 4T) of the sleep state 402 during actual operation is 6T, which is 0 or more, so the conversion time Tv = T0 + Tc = 6T. In this case, since the conversion time Tv (= 6T) in the inactive state is equal to or longer than the threshold value Tth (= 5T), the period 422 is a period in the standby state. That is, the calculation unit 303 calculates the assumed power amount with the period 422 as a period in which the standby state continues for 6T. Therefore, the assumed power amount Pf2_2 = PB2 × 6T. Further, the difference time ΔT at this time is zero.

  The assumed power amount of the period 423 can be calculated in the same manner as the period 421, and the assumed power amount of the period 423 is Pf2_3 = PA2 × 2T.

(Iv) Assumed electric energy of frequency setting f3 As shown in FIG. 4D, first, a period 430 corresponding to the standby state 400 is a period of a standby state in which the CPU 10 does not execute data processing. Therefore, assuming that the accumulated difference time T0 = 0, the value obtained by adding the accumulated difference time T0 and the duration time Tc (= 5T) of the standby state 400 during actual operation is 5T, which is 0 or more. Tv = T0 + Tc = 5T. The difference time ΔT at this time is 0, and the assumed power amount Pf3_0 = PB3 × 5T.

  A period 431 corresponding to the active state 401 is an active state period in which the CPU 10 can execute data processing, and the frequency setting is the frequency f3. Therefore, according to the processing time ratio table 3045, the conversion time Tv = Tc × r13 = 4T × 0.25 = 1T. At this time, the difference time ΔT = T0 + Tc−Tv = 0 + 4T−1T = 3T, and the assumed power amount Pf2_1 = PA2 × 1T.

  A period 432 corresponding to the sleep state 402 is a period in an inactive state in which the CPU 10 does not execute data processing. Here, the duration Tc of the sleep state 402 is 4T, but since the previous period 431 is shorter than that during actual operation, the reduced time can be assigned as the period of the inactive state. It becomes. That is, the value obtained by adding the cumulative difference time T0 (= 3T) and the duration time Tc (= 4T) of the sleep state 402 during actual operation is 7T, which is 0 or more, and therefore the conversion time Tv = T0 + Tc = 7T. . In this case, since the conversion time Tv (= 7T) in the inactive state is equal to or greater than the threshold value Tth (= 5T), the period 432 is a period in the standby state. That is, the calculation unit 303 calculates the assumed power amount with the period 432 as a period in which the standby state continues for 7T. Therefore, the assumed power amount Pf3_2 = PB3 × 7T. Further, the difference time ΔT at this time is zero.

  The estimated power amount of the period 433 can be calculated in the same manner as the period 431, and the assumed power amount of the period 433 is Pf3_3 = PA3 × 1T.

(4) Specific examples of actual power consumption and assumed power consumption (Fig. 5)
FIG. 5 is another explanatory diagram showing a correspondence relationship between the actual operation and the assumed operation of the CPU 10. (A) of the same figure shows the change of the operation state during the actual operation of the CPU 10 and the conversion time Tc of each operation state. (B) of the same figure shows the change of the operation state at the time of the assumed operation in which the operation frequency of the CPU 10 is the first frequency (f1) and the conversion time Tv of each operation state. (C) of the figure shows a change in the operation state at the time of the assumed operation with the operation frequency of the CPU 10 as the second frequency (f2) and a conversion time Tv of each operation state. (D) of the figure shows the change of the operation state at the time of the assumed operation in which the operation frequency of the CPU 10 is the third frequency (f3) and the duration Tv in each operation state.

(I) Actual power amount First, as shown in FIG. 5A, the operation state of the CPU 10 during actual operation changes in the order of sleep state 500, active state 501, stein-by state 502, and active state 503. Assume that the respective durations are 4T, 2T, 6T, and 2T. The operating frequency of the CPU 10 in the sleep state 500 is the first frequency (f1), and the operating frequency of the CPU 10 in the other operating states 501 to 503 is the third frequency (f3). At this time, the real power amount Pr_0 = PB1 × 4T in the standby state 500, the real power amount Pr_1 = PA3 × 2T in the active state 501, the real power amount Pr_2 = PS3 × 6T in the sleep state 502, and the real power amount Pr_3 in the active state 503 = PA3 × 2T.

  The assumed electric energy in each of FIGS. (B) to (D) is as follows.

(Ii) Assumed power consumption of frequency setting f1 As shown in FIG. 5B, a period 510 corresponding to the sleep state 500 during actual operation is a period of the sleep state in which the CPU 10 does not execute data processing. Therefore, if the accumulated difference time T0 is 0, the value obtained by adding the accumulated difference time T0 and the duration time Tc (= 4T) of the sleep state 500 during actual operation is 4T, which is 0 or more. Tv = T0 + Tc = 4T. The difference time ΔT at this time is 0, and the assumed power amount Pf1_0 = PS1 × 4T.

  A period 511 corresponding to the active state 501 is an active state period in which the CPU 10 can execute data processing, and the frequency setting is the frequency f1. Therefore, the conversion time Tv = Tc × r31 = 2T × 4 = 8T from the processing time ratio table 3045 of FIG. At this time, the difference time ΔT = T0 + Tc−Tv = 0 + 2T−8T = −6T, and the assumed power amount Pf1_1 = PA1 × 8T.

  A period 512 during an assumed operation corresponding to the standby state 502 is a period in an inactive state in which the CPU 10 does not execute data processing. At this time, the duration Tc of the standby state 502 is 6T. However, since the previous period 511 is extended as compared with the actual operation, the extended time and the duration Tc are offset, and the period of the inactive state Is not assigned. That is, since the value obtained by adding the accumulated difference time T0 (= −6T) and the duration time Tc (= 6T) of the sleep state 502 during actual operation is 0, the conversion time Tv = T0 + Tc = 0. As a result, the active period 511 and the subsequent active period 513 are continued. The calculation unit 303 calculates the assumed power amount with the period 512 as a period in which the standby state continues for 0T. That is, the assumed power amount Pf1_2 = 0. Further, the difference time ΔT at this time is zero.

  The assumed power amount of the period 513 can be calculated in the same manner as the period 511, and the assumed power amount Pf1_3 of the period 513 = PA1 × 8T.

(Iii) Assumed power amount of frequency setting f2 As shown in FIG. 5C, a period 520 corresponding to the standby state 500 is a period of a sleep state in which the CPU 10 does not execute data processing. Therefore, assuming that the accumulated difference time T0 = 0, the value obtained by adding the accumulated difference time T0 and the duration time Tc (= 4T) of the sleep state 500 during actual operation is 4T, which is 0 or more. Tv = T0 + Tc = 4T. The difference time ΔT at this time is 0, and the assumed power amount Pf2_0 = PS2 × 4T.

  A period 521 corresponding to the active state 501 is an active period during which the CPU 10 can execute data processing, and the frequency setting is the frequency f2. Therefore, the conversion time Tv = Tc × r32 = 2T × 2 = 4T is obtained from the processing time ratio table 3045 of FIG. At this time, the difference time ΔT = T0 + Tc−Tv = 0 + 2T−4T = −2T, and the assumed electric energy Pf2_1 = PA2 × 4T.

  A period 522 corresponding to the standby state 502 is a period in an inactive state in which the CPU 10 does not execute data processing. At this time, the duration Tc of the standby state 502 is 6T, but since the previous period 511 is extended as compared with the actual operation, the duration of the period 522 is shortened by the extended amount. That is, the value obtained by adding the accumulated difference time T0 (= −2T) and the continuation time Tc (= 6T) of the sleep state 502 at the time of actual operation is 4T, which is equal to or greater than 0, and therefore the conversion time Tv = T0 + Tc = 4T Become. In this case, since the conversion time Tv (= 4T) in the inactive state is smaller than the threshold value Tth (= 5T), the period 522 is a period in the sleep state. That is, the calculation unit 303 calculates the assumed power amount with the period 522 as a period in which the sleep state continues for 4T. Therefore, the assumed power amount Pf2_2 = PS2 × 4T. Further, the difference time ΔT at this time is zero.

  The assumed power amount of the period 523 can be calculated in the same manner as the period 521, and the assumed power amount Pf2_3 of the period 523 = PA2 × 4T.

(Iv) Assumed electric energy of frequency setting f3 As shown in FIG. 5D, a period 530 corresponding to the standby state 500 is a period of the standby state in which the CPU 10 does not execute data processing. Therefore, if the accumulated time difference T0 = 0, the value obtained by adding the accumulated time difference T0 and the duration time Tc (= 5T) of the standby state 500 during actual operation is 5T, which is 0 or more. Tv = T0 + Tc = 5T. At this time, the difference time ΔT is 0, and the assumed power amount Pf3_0 = PB3 × 5T.

  Next, a period 531 corresponding to the active state 501 is an active period during which the CPU 10 can execute data processing, and the frequency setting matches the frequency setting (f3) in actual operation. Therefore, the conversion time Tv = Tc × r33 = 2T × 1 = 2T from the processing time ratio table 3045 of FIG. At this time, the difference time ΔT = 2T−2T = 0, and the assumed power amount Pf3_1 = PA3 × 2T.

  Hereinafter, the conversion time Tv of the periods 532 and 533 can be calculated in the same manner. The assumed power amount Pf3_2 = PS3 × 6T in the period 532 and the assumed power amount Pf3_3 = PA3 × 2T in the period 533 are obtained, and the difference time ΔT is any Is also 0.

  The actual power amount and the virtual power amount calculated as described above are calculated every time the operating state of the CPU 10 changes or every time a predetermined period elapses (each time an element profile is generated). Given. For example, in the case of FIG. 4, first, when an element profile corresponding to the standby state 400 is given to the calculation unit 303, a first data group of the actual power amount Pr_0, the assumed power amount Pf1_0, Pf2_0, and Pf3_0 is generated. The first data group is output to the power difference generation unit 305. Thereafter, when an element profile corresponding to the active state 401 is given to the calculation unit 303, a second data group of the actual power amount Pr_1, the assumed power amount Pf1_1, Pf2_1, and Pf3_1 is generated, and the second data group is This is given to the power difference generation unit 305. In this way, a data group of power amount is generated for each element profile, and sequentially output to the power difference generation unit 305.

≪Method for generating cumulative power difference≫
A method for generating the accumulated power difference will be described.

  Here, as an example, consider a case where each power amount generated in FIG. 4 described above is input to the power difference generation unit 305. It is assumed that the initial value of cumulative power storage unit 3062 is zero.

  First, when the actual power amount Pr_0, the assumed power amount Pf1_0, Pf2_0, and Pf3_0 are given to the power difference generation unit 305 as the first power amount data group, the comparison unit 3051 displays the actual power amount Pr_0 and the assumed power amount. The smallest electric energy is detected among Pf1_0, Pf2_0, and Pf3_0. The difference calculation unit 3052 generates a difference power amount based on the detected minimum power amount and the four power amounts of the actual power amount Pr_0, the assumed power amount Pf1_0, Pf2_0, and Pf3_0. For example, when the assumed power amount Pf1_0 is the smallest power amount, ΔPr_0 (= Pr_0−Pf1_0), ΔPf1_0 (= Pf1_0−Pf1_0), ΔPf2_0 (= Pf2_0−Pf1_0), and ΔPf3_0 (= Pf3_0−P) Four power differences are calculated. The calculated difference power amounts ΔPr_0, ΔPf1_0, ΔPf2_0, and ΔPf3_0 are given to the accumulation unit 306 and stored in the accumulation power storage unit 3062.

  Next, when the actual power amount Pr_1, the assumed power amount Pf1_1, Pf2_1, and Pf3_1 are given to the power difference generation unit 305 as the second power amount data group, the comparison unit 3051 has the smallest power as described above. The amount is detected, and the difference calculation unit 3052 generates a difference power amount. For example, when the assumed power amount Pr_1 is the smallest power amount, ΔPr_1 (= Pr_1-Pr_1), ΔPf1_1 (= Pf1_1-Pr_1), ΔPf2_1 (= Pf2_1-Pr_1), and ΔPf3_1 (= Pf3_1-Pr_1). Four power differences are calculated. Then, the power difference generation unit 305 includes the difference power amounts (ΔPr_0, ΔPf1_0, ΔPf2_0, and ΔPf3_0) that are already stored in the accumulated power storage unit 3062 and the difference power amounts calculated this time (ΔPr_1, ΔPf1_1, ΔPf2_1, and ΔPf3_1). ) Is added for each frequency setting during actual operation and assumed operation and stored in the accumulated power storage unit 3062. For example, the difference calculation unit 3052 calculates (ΔPr_0 + ΔPr_1), (ΔPf1_0 + Pf1_1), (ΔPf2_0−ΔPf2_1), and (ΔPf3_0−ΔPf3_1), and updates the value of the cumulative difference power amount of the cumulative power storage unit 3062. . The updated accumulated difference power amount is again provided to the comparison unit 3051, and the difference calculation unit 3052 generates a difference of the accumulated difference power amount. For example, when (ΔPf1_0 + Pf1_1) is the smallest power amount among the four accumulated differential power amounts, the difference generation unit 3052 uses {(ΔPr_0 + ΔPr_1) − (ΔPf1_0 + Pf1_1)}, {(ΔPf1_0 + ΔPf1_1) − (ΔPf1_0), (ΔPf1_0), The difference between the four accumulated differential power amounts of {(ΔPf2_0 + ΔPf2_1) − (ΔPf1_0 + Pf1_1)} and {(ΔPf3_0 + ΔPf3_1) − (ΔPf1_0 + Pf1_1)} is calculated. Here, the accumulated difference power amount difference 3065 during actual operation is {(ΔPr — 0 + ΔPr — 1) − (ΔPf1 — 0 + Pf1 — 1)}, and the accumulated difference power amount difference 3066 during assumed operation (f1) is {(ΔPf1 — 0 + ΔPf1 — 1) − (ΔPf1 — 0 + Pf1 — 1). )}, And the difference 3067 in the accumulated differential power amount during the assumed operation (f2) is {(ΔPf2 — 0 + ΔPf2 — 1) − (ΔPf1 — 0 + Pf1 — 1)}, and the difference 3067 in the accumulated differential power amount during the assumed operation (f3) is {(ΔPf3 — 0 + ΔPf3 — 1). ) − (ΔPf1_0 + Pf1_1)}. Information on the difference between these accumulated differential power amounts is stored in the accumulated power storage unit 3062.

  As described above, the power difference generation unit 305 repeatedly generates and accumulates the difference power, so that the accumulated power storage unit 3062 has an actual value every time the operating state of the CPU 10 changes or every time a predetermined period elapses. The difference information 3065 to 3068 of the accumulated difference power amount for each frequency during the operation and the assumed operation is stored. The stored difference information of the accumulated difference power amount is information obtained by accumulating the difference of the electric energy with respect to the smallest electric energy as described above, and further taking the difference, so that the electric energy is simply accumulated for the number of times of measurement. The amount of data can be reduced as compared with the case of doing so. As a result, the capacity of the storage area of the cumulative power storage unit 3062 can be reduced, which contributes to a reduction in the chip area of the data processing apparatus 1.

≪Process flow related to calculation of actual power consumption and assumed power consumption≫
FIG. 6 is a flowchart showing an example of the flow of processing for calculating the actual power amount and the assumed power amount by the DVFS management module 30.

  When the data processing apparatus 1 is powered on and reset is released, processing related to the calculation of the actual power amount and the assumed power amount is started. First, the CPU 10 sets various initial setting data stored in, for example, a ROM or the like in the basic data unit 304 (S101). The DVFS management module 30 monitors the sleep state signal Vsp, the standby state signal Vsb, and the like of the CPU 10, and waits until a change in the operation state of the CPU 10 or a predetermined period elapses (S102). When the monitor unit 302 of the DVFS management module 30 detects a change in the operating state of the CPU 10 or the elapse of a predetermined period, the monitor unit 302 generates an element profile and outputs it to the computing unit 303 (S103). Thereafter, the monitor unit 302 resets the internal timer and monitors the change in the operating state of the CPU 10 or the elapse of a predetermined period (S104).

  Receiving the element profile, the calculation unit 303 starts calculating the actual power amount (S105). The computing unit 303 refers to the unit power amount table 3044, and acquires the unit power amount parameter corresponding to the received CPU status information 3021 and DVFS status information 3022 of the element profile (S106). Then, the computing unit 303 calculates the actual power amount based on the duration Tc of the received duration information 3023 of the element profile and the unit power amount parameter (S107).

  Next, the calculation unit 303 starts calculating the assumed electric energy at any one of the frequencies f1, f2,... Fn−1, fn (n is a natural number) that can be set in the DVFS control. (S108). First, the calculation unit 303 calculates a conversion time Tv at an assumed frequency setting (for example, f1) (S109). The processing flow relating to the calculation of the conversion time Tv will be described in detail later. Next, the computing unit 303 calculates an assumed power amount at the assumed frequency setting (f1) (S110). Thereafter, the processing from step 108 to step 110 is repeatedly executed for each assumed frequency setting f1 to fn, and the assumed power amount at each assumed operation is calculated. Note that the calculation procedure of the actual power amount and the assumed power amount is not particularly limited. For example, Steps 108 to 110 for calculating the assumed power amount at each assumed operation are executed, and then Step 105 for calculating the actual power amount is performed. It is good also as a procedure which performs-step 107.

  When the actual power amount and the assumed power amount are calculated, the power difference generation unit 305 detects the smallest power amount among the calculated actual power amount and the assumed power amount (S111). The power difference generation unit 305 and the accumulation unit 306 generate the difference information of the accumulated difference power amount for each frequency setting during the actual operation and the assumed operation by the method described above, and store the information in the accumulation power storage unit 3062 (S112). ). Thereafter, the accumulating unit 306 increments the counter 3064 (S113). The notification unit 3063 compares the counter value of the counter 3064 with the set value of the measurement count information 3042 (S114). As a result of the comparison, if the counter value is smaller than the set value, the process proceeds to step 102, and the calculation of the actual power amount and the assumed power amount is performed after the next change in the operating state of the CPU 10 or the predetermined period has elapsed. Perform again (S102 to S113). On the other hand, when the counter value is equal to or larger than the set value, the notification unit 3063 notifies the CPU 10 that the calculation of the actual power amount and the assumed power amount is completed (S115). Receiving the notification, the CPU 10 refers to the actual power amount calculated by accessing the cumulative power storage unit 3062 and the information on the assumed power amount, determines the frequency setting for lower power consumption, and determines the frequency as necessary. Change the setting.

  Next, the conversion time calculation process in step 109 will be described in detail with reference to FIG.

  FIG. 7 is an explanatory diagram illustrating an example of the flow of conversion time calculation processing.

  First, when calculation of the conversion time Tv is started in step 109 of FIG. 6, the calculation unit 303 refers to the CPU status information 3021 of the acquired element profile, and the operation state of the CPU 10 during the actual operation is an active state. Whether or not (S201). When the operation state is the active state, the calculation unit 303 refers to the processing time ratio table 3045, and acquires the processing time ratio parameter corresponding to the frequency setting at the actual operation and the assumed frequency setting (S202). ). The calculation unit 303 calculates the conversion time Tv by the equation (Tv = Tc × rn) (S203). Subsequently, the calculation unit 303 calculates a difference time ΔT by an equation (ΔT = T0 + Tc−Tv) (S204).

  In step 201, when the operation state is not the active state, the calculation unit 303 determines whether or not a value obtained by adding the duration time Tc during the actual operation and the accumulated difference time T0 is 0 or more (S205). When the added value is smaller than 0, the calculation unit 303 calculates the difference time ΔT by the equation (ΔT = T0 + Tc) (S206). Subsequently, the calculation unit 303 sets the conversion time Tv = 0 (S207). That is, it is assumed that the inactive period during the assumed operation has disappeared.

  On the other hand, when the added value is equal to or greater than 0 in step 205, the calculation unit 303 calculates the conversion time Tv from the equation (Tv = Tc × rn) (S208). Subsequently, the calculation unit 303 sets the difference time ΔT = 0 (S209). Next, the calculation unit 303 reads threshold information 3043 (the threshold Tth) from the basic data unit 304 (S210). The calculation unit 303 compares the read threshold value Tth with the conversion time Tv calculated in step 208 (S211). As a result of the comparison, when the conversion time Tv is equal to or greater than the threshold value Tth, the calculation unit 303 determines the operation state of the CPU 10 during the assumed operation as the standby state (S212). Otherwise, the calculation unit 303 determines the operation state of the CPU 10 during the assumed operation as the sleep state (S213).

  When the above step 204, step 212, and step 213 are completed, the calculation unit 303 refers to the unit power amount table 3044 and acquires the unit power amount parameter corresponding to the assumed frequency setting and the assumed operation state. (S212). Thereafter, the process proceeds to step 110 described above, and the calculation of the assumed power amount during the assumed operation is performed.

<< Effect of feedback of actual power amount and assumed power amount to CPU 10 >>
As described above, the CPU 10 that has received the notification of the completion of the calculation of the actual power amount and the assumed power amount refers to the actual power amount calculated by accessing the cumulative power storage unit 3062 and the assumed power amount, thereby reducing the power consumption. By determining the frequency setting for power, the setting of the operating frequency of the CPU 10 is changed as necessary.

  FIG. 8 is an explanatory diagram showing an example of operation timing of the data processing apparatus 1 according to the present embodiment. In the figure, as an example, it is assumed that the frequency setting can be switched between the low speed setting (low frequency setting) and the high speed setting (high frequency setting) by DVFS control, and the actual power amount by the DVFS management module 30 is assumed. The case where the number of times of measurement of electric energy (cumulative number) is 4 is shown. In the waveform showing the operation state of FIG. 6, the high level period indicates a period during which the CPU 10 is executing data processing, and the low level period indicates a period during which the CPU 10 is not performing data processing.

  As shown in FIG. 8, the data processing device 1 calculates the actual power amount and the assumed power amount each time the standby state signal Vsb and the sleep state signal Vsp change, and each time the calculation of the power amount is completed four times. The CPU 10 notifies the CPU 10 of the completion of the calculation of the power amount, thereby feeding back the power amount. Hereinafter, the timing for notifying the completion of the electric energy is referred to as feedback timing. First, when the load state related to the data processing of the CPU 10 changes from the high load state to the low load state at the timing t0, the CPU 10 performs the data processing by switching the frequency of the clock signal from the high speed setting to the low speed setting at the timing t1. After that, upon feedback timing tf2, the CPU 10 that has received notification from the DVFS management module 30 that the calculation of the amount of power for four times has been completed accesses the cumulative power storage unit 3062 to determine the frequency setting with the lowest power consumption. Then, it is determined whether or not to change the frequency setting in consideration of the subsequent load state. In the drawing, the case where the CPU 10 determines that the high speed setting consumes less power than the current low speed setting and changes the frequency setting to the high speed setting at the timing t2 is shown as an example. In this case, since the data processing is completed in a shorter time than in the case of the low speed setting, the waiting time from one data processing to the next data processing becomes longer, and it becomes possible to shift to the standby state. In the figure, the case where the CPU 10 shifts to the standby state and the standby state signal Vsb is asserted at the timing t3 is shown.

  Thereafter, at the feedback timing tf3, the CPU 10 that has received the notification from the DVFS management module 30 accesses the cumulative power storage unit 3062 again to determine the frequency setting with the lowest power consumption, and whether to change the frequency setting. to decide. In the figure, the case where the CPU 10 determines that the current high speed setting is lower in power consumption and the CPU 10 continues to operate at the high speed setting is shown as an example. Thereafter, when the load state changes to the high load state and data processing is started at timing t4, the data processing is completed at timing t5, and the state shifts to the standby state.

  Here, as a comparative example of the data processing apparatus 1 according to the present embodiment, FIG. 9 illustrates an example of operation timing of the data processing apparatus that performs DVFS control without performing feedback of the actual power amount and the assumed power amount.

  As shown in the figure, when the load state related to the data processing of the CPU changes from the high load state to the low load state at the timing t0, the CPU switches the frequency of the clock signal from the high speed setting to the low speed setting at the timing t1. Data processing. Since the CPU of the data processing device according to the comparative example does not perform feedback control based on the actual power amount and the assumed power amount, the CPU does not change the frequency setting until the load state changes. As a result, the CPU operates at the low speed setting until the next timing t4 when the load state changes. In this case, since the time required for data processing becomes longer than in the case of the high-speed setting, the waiting time between one data processing and the next data processing is shortened, and the CPU cannot shift to the standby state. Therefore, in the CPU, the operation state is alternately switched between the active state and the sleep state. Thereafter, the load related to data processing changes from the low load state to the high load state at timing t4, but the CPU cannot immediately switch to the high speed setting, and performs the data processing with the low speed setting. Then, at timing t6 immediately before the completion of data processing, the setting is switched to the high speed setting. When the data processing is completed, the CPU shifts to a sleep state.

  FIG. 10 is an explanatory diagram illustrating power characteristics of the data processing device 1 and the data processing device according to the comparative example. In the figure, a characteristic 501 indicated by a solid line indicates the power consumption of the data processing apparatus 1 according to the present embodiment shown in FIG. 8, and a characteristic 502 indicated by a broken line indicates the data processing of the comparative example shown in FIG. The power consumption of the apparatus 1 is shown. Timings t0 to t5 shown in the figure correspond to timings t0 to t5 in FIGS.

  As shown in the figure, since the DVFS control is similarly performed in both data processing apparatuses until the timing t2, the power consumption is the same. Since the data processing apparatus according to the comparative example continues to operate at a low speed setting and repeats the sleep state and the active state, the power consumption gradually increases. On the other hand, the data processing device 1 according to the present embodiment switches to the high speed setting at the timing t2. As a result, the standby time between one data process and the next data process becomes long, so that the CPU 10 can shift to the standby state at the timing t3, and the power consumption is suppressed. After that, when the load state related to the data processing changes from the low load state to the high load state at timing t4, the data processing is completed at timing t5 because the CPU 10 related to the data processing device 1 is set at high speed, and then again. It will be in a standby state. As a result, an increase in power consumption can be suppressed. On the other hand, in the data processing apparatus according to the comparative example, even after the load state of the CPU changes from the low load state to the high load state at timing t4, the CPU cannot immediately switch to the high speed setting, and the CPU is set to the low speed setting. Data processing is performed until timing t6. During this time, power consumption can be suppressed, but the time required for data processing becomes longer. Thereafter, at time t6 immediately before the completion of data processing, the setting is switched to the high speed setting, and the power consumption increases. Even after the data processing is completed, the CPU shifts to the sleep state instead of the standby state, so that the power consumption gradually increases.

  As described above, the data processing apparatus 1 that finishes data processing in a short time with the high-speed setting and then waits in the standby state may consume less power than the data processing apparatus according to the comparative example.

  As described above, according to the data processing device 1 according to the present embodiment, not only the load state related to the data processing of the CPU 10 but also the actual power amount and the assumed power amount are calculated. It can be determined whether the setting is optimal in terms of power. As a result, the data processing device 1 can be changed to a frequency setting with lower power consumption, and the power consumption can be further reduced as compared with a data processing device that performs only conventional DVFS control. .

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, although the case where the arithmetic unit 303 is configured by a DSP has been shown, if the actual power amount and the assumed power amount can be calculated, the arithmetic unit 303 can also be configured by a dedicated logic circuit. Further, in the description of FIG. 8 and FIG. 10, the case where the number of times of measurement is four and the CPU 10 is notified every time the calculation of the power amount of four times is completed is shown as an example. The number of measurements may be increased or decreased. Further, the number of measurements may be changed according to the data processing state of the CPU 10. For example, in a situation where data processing by the CPU 10 is continuously performed at regular intervals, it is less necessary to change the frequency setting. Therefore, the frequency of power feedback is reduced by increasing the number of measurements, and the CPU 10 is controlled by DVFS. Reduce the load. Thereafter, when the above situation is avoided, the frequency of power feedback is increased by reducing the number of measurements, and the frequency setting according to the power state of the CPU 10 can be easily changed.

  The information stored in the accumulated power storage unit 3062 may be information that allows the CPU 10 to determine the frequency setting at which the power consumption is low, and is not limited to the difference information of the accumulated difference power amount. For example, if an increase in the capacity of the storage area of the cumulative power storage unit 3062 is allowable, the difference calculation unit 3052 does not calculate the difference, and accumulates the actual power amount 3031 and the assumed power amount 3032 to 3034 by the number of times of measurement. The added information may be stored for each frequency setting during actual operation and assumed operation. Further, for example, the difference power amount 3053 to 3056 calculated by the difference calculation unit 3052 is cumulatively added for the number of times of measurement for each frequency setting at the time of actual operation and assumed operation, and the difference power amount at the time of actual operation obtained by cumulative addition. And the accumulated difference power amount for each frequency setting during the assumed operation is stored in the accumulated power storage unit 3062. According to this, since the amount of data can be reduced as compared with the case where the actual power amount 3031 and the assumed power amount 3032 to 3034 are simply accumulated and stored, the capacity of the storage area of the cumulative power storage unit 3062 can be reduced. can do. Further, the processing becomes easier as compared with the above-described method for calculating the difference between the accumulated differential power amounts.

100 Data processing system 1 Data processing device 2 Power supply IC
3 External memory 4 Crystal oscillator 10 CPU
20 Clock signal generator (CPG)
11, 12 Control signal VDD Power supply voltage CLK Clock signal 30 DVFS management module 301 Detection unit 3011 Sleep state change detection unit 3012 Standby state change detection unit 3013 Clock signal change detection unit Vsp Sleep state signal Vsb Standby state signal Vsc Clock state signal 13 Change Detection signal 302 Monitor unit 3021 CPU status information 3022 DVFS status information 3023 Duration information 303 Calculation unit 3031 Actual power amount 3032-3034 Estimated power amount 3035-3037 Difference time 304 Basic data unit 3041 Measurement time information 3042 Measurement frequency information 3043 Threshold information 3044 Unit power amount table 3045 Processing time ratio table 305 Power difference generation unit 3051 Comparison unit 3052 Difference calculation unit 3053-30 56 Difference power amount 306 Accumulation unit 3062 Accumulated power storage unit 3063 Notification unit 3064 Counter 3065 to 3068 Difference of accumulated difference energy amount 400 to 403, 500 to 503 Period of operation state in actual operation 410 to 413, 510 to 513 Assumed operation Period of operation state at time (frequency f1) 420 to 423, 520 to 523 Period of operation state at assumed operation (frequency f2) 430 to 433, 530 to 533 Period of operation state at assumed operation (frequency f3) t0 t5 timing tf1 to tf3 feedback timing 501 power characteristic of the data processing apparatus 1 502 power characteristic of the data processing apparatus according to the comparative example

Claims (14)

A data processing control unit that executes data processing in synchronization with a clock signal and that selectively controls the frequency of the clock signal based on a load state related to the data processing;
The actual power consumption for a predetermined period consumed by the data processing control unit during the actual operation of the data processing control unit is calculated, and the predetermined operation during the assumed operation assuming the operation by the data processing control unit at an assumed frequency. A power calculator that calculates an assumed amount of power in the period,
The data processing control unit is configured to select and control a frequency of a clock signal corresponding to the state of the load in consideration of a frequency with low power consumption among the actual power amount and the assumed power amount. The operation state of the data processing control unit includes an active state in which data processing can be performed and an inactive state in which data processing cannot be performed,
The inactive state includes a first low power consumption state in which the supply of the clock signal to the data processing control unit is stopped, and a second state in which the supply of the clock signal and the power supply voltage to the data processing control unit is stopped. Including low power consumption state,
The power calculation unit grasps the duration of the active state, the duration of the first low power consumption state, and the duration of the second low power consumption state during the actual operation and the assumed operation. The data processing device according to claim 1, wherein the actual power amount and the estimated power amount are calculated based on each of the duration times and a power consumption amount per unit time in each of the operation states.   The said power calculation part notifies the said data processing control part that the said calculation was completed each time the calculation of the said actual electric energy and the said estimated electric energy of the said predetermined period is completed. Data processing device. The power calculation unit calculates an actual power amount consumed by the data processing control unit every predetermined period or for each change in the operation state of the data processing control unit, and calculates the calculated actual power amount by a predetermined number of times. While calculating the actual electric energy in the predetermined period by accumulating,
The virtual power amount in the predetermined period is calculated by calculating the assumed power amount for each calculation related to the actual power amount, and accumulating the calculated assumed power amount for the predetermined number of times. Data processing equipment.   The actual power amount for one time out of the predetermined number of times indicates a power consumption amount per unit time in the operation state of the data processing control unit and a duration time of the operation state of the data processing control unit in the one time. The data processing apparatus according to claim 4, wherein the data processing apparatus is calculated by multiplying one duration.   The assumed power consumption for one time out of the predetermined number of times is the power consumption per unit time in the operation state of the data processing control unit at the assumed frequency, and the operation state at the time of the assumed operation in the one time. The data processing device according to claim 5, wherein the data processing device is calculated by multiplying a second duration time indicating a duration time of.   When the operation state at the time of the assumed operation is the active state, the power calculation unit calculates the corresponding first duration time at the actual operation as the data processing control unit at the frequency at the assumed operation time. The data processing device according to claim 6, wherein conversion is performed in accordance with the data processing capability of the first and the converted time is defined as the second duration time.   The power conversion unit calculates a difference time indicating a difference between the first duration time and the calculated second duration time when the operation state of the data processing control unit at the time of the assumed operation is the active state. And when the operation state of the data processing control unit at the time of the assumed operation is the inactive state, based on the time calculated by adding the first duration and the accumulated difference time The data processing device according to claim 7, wherein the second duration is determined.   In the case where the operation state of the data processing control unit at the time of the assumed operation is the inactive state, the power calculation unit, when the second duration is greater than a predetermined threshold, the data at the assumed operation Assuming that the operation state of the processing control unit is the second low power consumption state, and when the operation state is smaller than the predetermined threshold, the operation state of the data processing control unit during the assumed operation is the first low power consumption state. The data processing apparatus according to claim 8, wherein the assumed power is calculated on the assumption that The power calculation unit stores first power information based on the calculated actual power amount for each predetermined period and second power information based on the calculated estimated power amount for each predetermined period. Storage area,
The data processing apparatus according to claim 9, wherein the storage area is accessible by the data processing control unit.   The power calculation unit selects the smallest power amount from the actual power amount and the assumed power amount, and cumulatively adds a power amount indicating a difference between the selected power amount and the actual power amount for the predetermined number of times. The first power information is stored in the storage area, and the power amount indicating the difference between the selected power amount and the assumed power amount is cumulatively added the predetermined number of times, and the second power information is stored in the storage region. The data processing device according to claim 10, wherein the data processing device is stored. The power calculation unit selects the smallest power amount among the actual power amount and the assumed power amount for each predetermined period or for each change in the operation state of the data processing control unit, and the selected power amount and the Calculating a first difference power amount indicating a difference from the actual power amount, and calculating a second difference power amount indicating a difference between the selected power amount and the assumed power amount;
The first difference power amount calculated last time and the first difference power amount calculated this time are added to calculate a cumulative difference power amount related to the actual power amount, and the second difference power amount calculated last time And the second difference power amount calculated this time is added to calculate a cumulative difference power amount related to the assumed power amount,
Further, the power calculation unit selects the smallest power amount among the cumulative difference power amount related to the actual power amount and the cumulative difference power amount related to the assumed power amount, and relates to the selected power amount and the actual power amount. A power amount indicating a difference from the cumulative power difference amount is stored in the storage area as the first power information, and a power amount indicating a difference between the selected power amount and the cumulative power difference amount related to the assumed power amount is stored in the storage area. The data processing apparatus according to claim 10, wherein the data processing apparatus stores the second power information in the storage area. The power calculation unit stores a first table in which a power amount per unit time according to the operation state of the data processing control unit is stored corresponding to each frequency that can be assumed,
Information indicating a ratio between the data processing capability of the data processing control unit at the frequency related to the actual power amount and the data processing capability of the data processing control unit at the assumed frequency is stored for each assumed frequency. A second table,
The data processing apparatus according to claim 9, wherein the power calculation unit calculates the actual power amount and the assumed power amount based on values of the first table and the second table. A first semiconductor device that outputs a power supply voltage in response to an instruction from the outside;
A data processing system comprising: a second semiconductor device that operates by supplying power from the first semiconductor device;
The second semiconductor device performs data processing in synchronization with a clock signal and selects and controls a frequency and a power supply voltage of the clock signal based on a load state related to the data processing;
A clock generation unit that generates and outputs the clock signal based on control by the data processing control unit;
The actual power consumption for a predetermined period consumed by the data processing control unit during the actual operation of the data processing control unit is calculated, and the predetermined operation during the assumed operation assuming the operation by the data processing control unit at an assumed frequency. A power calculator that calculates an assumed amount of power in the period,
The data processing control unit selectively controls the frequency of the clock signal corresponding to the state of the load in consideration of the frequency with low power consumption among the actual power amount and the assumed power amount, and the selected frequency A data processing system for instructing the first semiconductor device to supply a power supply voltage according to the above.

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