JP2016527630A - System and method for idle state optimization in a multiprocessor system on a chip - Google Patents

Abstract

Various embodiments of methods and systems for idle state optimization in a portable computing device (“PCD”) are disclosed. An exemplary method compares the total power consumption level for all processing cores in the PCD with the power budget and operates in the first idle state if the power budget is available Transitioning the active core to a different idle state. In doing so, the latency value associated with transitioning the transitioned core from the idle state to the active state can be shortened as needed. As a result, idle cores with otherwise long latencies can be better positioned to quickly transition to the active state and handle the workload, improving user experience and QoS May be.

Description

  The present invention relates to a system and method for idle state optimization in a multiprocessor system on a chip.

  Portable computing devices ("PCD") are becoming a necessity for people at the individual and professional level. These devices can include cell phones, personal digital assistants (“PDAs”), portable game consoles, palmtop computers, and other portable electronic devices. Most PCDs on the market include multi-core processors, which can operate at various frequencies and active core configurations, depending on the particular use case.

  One particular aspect of PCD is that it generally does not have an active cooling device, such as a fan, which is often found in larger computing devices such as laptop computers and desktop computers. As a result, thermal energy generation is often managed in the PCD through the application of various thermal management techniques, which make the processing core active and idle based on real-time or near real-time workload demands. Transitioning between states can be included. By transitioning the core from the active processing state to the idle state, the power consumption associated with the active state can be avoided when the core is not needed to handle the workload.

  However, putting the core in an idle state can adversely affect the quality of service (“QoS”) provided to the user by the PCD. For example, many PCD use cases generate a “burst load” and the user experience will inevitably worsen if the core is not in an active state ready to handle burst workloads quickly. become. As a result, having a long latency to put the core into an idle state and transition from it to the original active state may be desirable if the goal is to save power, but at the same time It is undesirable if the goal is to optimize QoS during burst loads.

  Therefore, a method and method for optimizing the core idle state selection from the perspective of the total power budget within the PCD and to minimize latency when the core is transitioned to the original active state A system is needed in the art.

  Various embodiments of methods and systems for idle state optimization in a portable computing device (“PCD”) are disclosed. An exemplary method for idle state optimization in PCD includes determining a power budget for PCD. In particular, since the form factor for the PCD varies, those skilled in the art will recognize that the allowable or maximum power budget may vary depending on the particular form factor of the PCD. The total power consumption level for all processing cores can then be compared to the power budget, and if lower than the power budget, the core operating in the idle state transitions to a different idle state. Can be identified as being eligible.

  Based on the operating temperature of the eligible core, one or more of the appropriate cores are in the first idle state (e.g., a sudden power down idle state) to the second idle state (e.g., `` waiting for interrupt '' idle) When transitioning to (state), it is possible to determine the possible impact on the total power consumption. If transitioning one or more cores to a different idle does not increase the total power consumption beyond the power budget, the one or more cores can transition. In doing so, if needed, the latency value associated with transitioning the transitioned core from the idle state to the active state can be reduced. As a result, idle cores that are otherwise idle with long latencies can be better positioned to quickly transition to the active state and handle the workload, improving user experience and QoS May be.

  In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise indicated. For reference numbers with character designations such as “102A” or “102B”, the character designation can distinguish between two similar parts or elements present in the same figure. When a reference number is intended to encompass all parts having the same reference number in all figures, the character designation for the reference number may be omitted.

For a given idle state and junction temperature, the latency and leakage rate associated with exemplary cores 0, 1, 2, and 3 in a given quad-core chipset of a portable computing device (`` PCD '') It is a graph to show. 1 is a functional block diagram illustrating an embodiment of an on-chip system for idle state optimization in a multi-core PCD. FIG. FIG. 2 is a functional block diagram of an exemplary, non-limiting aspect of a PCD in the form of a wireless telephone to implement a method and system for idle state optimization. FIG. 4 is a schematic diagram illustrating an example software architecture of the PCD of FIG. 3 to support idle state optimization. FIG. 4 is a logic flow diagram illustrating an embodiment of a method for idle state optimization in the PCD of FIG.

  The term “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any aspect described herein as "exemplary" is not necessarily to be construed as exclusive, preferred or advantageous over other aspects.

  As used herein, the term “application” can also include files with executable content, such as object code, scripts, bytecodes, markup language files, and patches. In addition, an “application” as referred to herein also includes files that are not inherently executable, such as documents that may need to be published or other data files that need to be accessed. In some cases.

  As used herein, “component”, “database”, “module”, “system”, “thermal energy generation component”, “processing component”, “processing engine”, “application processor”, etc. The term is intended to refer to a computer-related entity that is either hardware, firmware, a combination of hardware and software, software, or running software, provides functionality, and is used herein. Fig. 4 represents an exemplary means for performing a particular step in the described process or process flow. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may exist in a process and / or in a thread of execution, a component may be localized on one computer, and / or two or more May be distributed among computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. A component is a single or multiple data packets (e.g., interacting with another component in a local system, distributed system, and / or signaling to another system over a network such as the Internet Can communicate via local and / or remote processes, eg according to signals having data) from components.

  As used herein, the terms “central processing unit” (“CPU”), digital signal processor (“DSP”), “chip”, and “chipset” refer to processing components that may be present in a PCD. This is a non-limiting example, and is used interchangeably unless otherwise specified. Further, as distinguished herein, a CPU, DSP, or chip or chipset may be comprised of one or more separate processing components, commonly referred to herein as a “core”.

  As used herein, the terms “heat” and “thermal energy” may be used in connection with a device or component capable of generating or dissipating energy that can be measured in units of “temperature”. It will be understood that there is. As a result, the term “temperature” assumes any measurement relative to some reference value that can indicate the relative warmth or lack of heat of the device or component that produces “thermal energy”. Will be further understood. For example, when two components are in “thermal” equilibrium, the “temperature” of the two components is the same.

  As used herein, the terms “workload”, “processing workload” and “processing workload” are used interchangeably and are generally associated with a given processing component in a given embodiment, Or directed to the processing burden or percentage of processing burden that may be allocated. Similarly, the term “burst load” requires a higher prioritization than other queued workloads and therefore should be processed immediately to optimize the user experience. Used to indicate The burst load may further represent a relatively large workload that not only needs to be processed immediately, but also requires a relatively high processing capacity.

  In addition to those defined above, a “processing component” includes, but is not limited to, a central processing unit, graphical processing unit, core, main core, sub-core, processing area, hardware engine, etc., or portable computing device It can be any component within or outside the integrated circuit. Further, as long as terms such as “heat load”, “heat distribution”, “thermal signature”, “heat treatment load” indicate the workload burden that may be performed on the processing component, these “ One skilled in the art will recognize that the use of the term “heat” may relate to processing load distribution, workload burden and power consumption.

  As used herein, the terms “thermal mitigation technique”, “thermal policy”, “thermal management”, and “thermal mitigation measures” are used interchangeably.

  As used herein, the term “portable computing device” (“PCD”) is used to describe any device that operates from a limited capacity power source, such as a battery. Battery-operated PCDs have been used for decades, but the technological advancements in rechargeable batteries are linked to the emergence of third-generation (“3G”) and fourth-generation (“4G”) wireless technologies Has enabled many PCDs with many functions. Therefore, PCD should be a cell phone, satellite phone, pager, PDA, smartphone, navigation device, tablet, smart book or reader, media player, combination of the above devices, laptop computer with wireless connection, among others Can do.

  As used herein, the term “latency” generally refers to the time required for a given processing component to transition from a particular idle state to an active state in order to process a workload, such as a burst workload. Used to refer to Multiple idle states may be available for a given exemplary core and can be distinguished from each other based on core latency and leakage power for each idle state. Generally speaking, the longer the latency associated with a particular idle state, the lower the leakage rate (ie, the lower the power consumption). Thus, as those skilled in the art will appreciate, idle states associated with long latencies can provide better power savings, in contrast, idle states associated with high leakage rates can be further processed in the PCD. Better QoS can be provided when capacity is needed.

  For purposes of describing the exemplary embodiment, this specification describes three idle states: a “wait for interrupt” (“WFI”) idle state, a hold idle state, and a power diminishing idle state. Even so, embodiments of the system and method are not limited to only three idle states, or any particular combination of idle states. As will be appreciated by those skilled in the art, any number of idle states are available and may be utilized in the PCD, each such state providing various latency and power saving levels. Advantageously, embodiments of systems and methods for idle state optimization recognize different latency and power savings associated with available idle states and optimize these to optimize QoS and user experience Take advantage of the differences. QoS and user experience are optimized by various embodiments both through strategic assignment of individual cores to various idle states and transitions between idle and active processing states. Allocation to and transition between idle and active states balances power saving goals (i.e. thermal mitigation goals) with QoS / user experience goals (i.e. efficient handling of workloads, especially burst loads). Is determined through applying an idle state optimization algorithm that takes into account the total power budget of a particular PCD.

  In particular, when a processing core enters a WFI idle state, its processor clock is stopped or “gated off” until an interrupt or debug event occurs. In that case, the core is no longer in the active state to handle the workload (thus saving power consumption) and active whenever an interrupt (such as to handle a burst load) is detected It remains in a state where it can quickly return to the state. When in the WFI idle state, even if the core does not consume power to handle the workload, the voltage continues to be applied to the core and a non-negligible current will inevitably result in leakage current. In shape, it remains on the core power rail. Among other things, leakage current can be directly correlated with the core temperature (i.e. junction temperature), so the measured core temperature can be used to calculate the current power consumption rate (the core becomes Those skilled in the art will recognize that (regardless of the idle state that may be obtained).

  The retained idle state is similar to the WFI idle state in that the processing core in the retained state is clocked. Nevertheless, the power voltage supplied to the processing core is also reduced when in the hold state. The advantage of the hold state over the WFI state is that there is less leakage current associated with the hold state, and therefore power savings in the hold state are improved over the WFI state. However, among other things, the waiting time for the processor to return from the holding idle state to the active state is longer than the transition from the WFI state.

  A third exemplary idle state is a power dip idle state. Compared to the hold idle state, the processing core that enters the power droop idle state is fully clocked and all power is removed from its power rail. As a result, the power savings associated with the power steep idle state is improved over the WFI state and the hold state. However, the latency associated with the power dip idle state is the longest of all three exemplary state durations because the core must go through a warm boot sequence to return to the active state.

  Again, a general description of the above three idle states where exemplary processing components may be available, and references to those idle states are provided for illustrative purposes only, and the system and There is no intention to imply or suggest that the method embodiment is applicable only to three idle states. It is contemplated that any number of idle states may be utilized by embodiments of the present system and method. Some idle states can clock gate the processor and / or reduce its power supply by software, while other idle states can do so by hardware. Similarly, in addition to clock gating and power reduction to processing components, some idle states can also switch off memory, drivers, bus hardware, etc. In general, however, the more extreme the action taken in a given idle state to conserve power, the longer it takes for an idle processor to return to the active processing state.

  In particular, it is believed that not all processing cores will exhibit equivalent power savings and latency when operating at a given temperature and a given idle state. As those skilled in the art will appreciate, the performance characteristics of the various processing cores when in the same idle state and at the same operating temperature can be any number of reasons, including but not limited to different silicon levels, design changes, etc. May vary. Further, those skilled in the art will appreciate that the performance characteristics associated with any given processing core may vary in relation to the operating temperature of the processing core, the power supplied to that processing component according to idle conditions, etc. Be recognized.

  For example, consider an exemplary heterogeneous multi-core processor that may include several different processing cores that generally range in execution capability from low to high (particularly several different, each including one or more cores) One skilled in the art will recognize that an exemplary heterogeneous multiprocessor system on chip (“SoC”) may also be considered that may include processing components). As will be appreciated by those skilled in the art, low to medium capacity processing cores within heterogeneous processors exhibit a lower power leakage rate at a given idle state, resulting in a relatively high execution capacity. However, it exhibits a lower heat energy generation rate than the processing core in the same idle state. For these reasons, high capacity cores may be most desirable to handle burst loads, but low capacity cores cannot be exceeded in full power budget due to low leakage rates, so in certain scenarios WFI idle state It may be more desirable to specify

  FIG. 1 is a graph showing latency and leakage rates associated with exemplary cores 0, 1, 2, and 3 in a given quad-core chipset of PCD for a given idle state and junction temperature. . In particular, although specific features and aspects of various embodiments are described herein with respect to a quad-core chipset, those skilled in the art will recognize that these embodiments can be applied in any multi-core or single-core chip.

  Illustratively, for a given junction temperature and idle state, each core exhibits unique performance characteristics with respect to latency and power consumption. Core 0 can return to the active processing state relatively quickly (core 0 latency), but also has a relatively high leakage power level (core 0 leakage). Core 1 will take more time to return to the active processing state than Cores 0 and 3, but not as late as Core 2. According to the IDDq evaluation of core 1 (core 1 leakage), the leakage rate is the second highest efficiency among the cores.

  Advantageously, the latency and quiescent leakage rates differ between cores by the idle state selection (“ISS”) module to select the most suitable processing component to transition to various idle states. Can be utilized, thereby managing power consumption in the PCD without unnecessarily increasing the latency to handle burst loads. For example, if the given idle state represented in the graph of FIG. 1 is a WFI idle state, and core 3 is currently in a power-sag idle state, core 3 will In order to minimize latency, the ISS module can choose to transition the core 3 from the power down idle state to the WFI idle state. Taking the example further, when making a choice to move Core 3 from a power declining state to a WFI idle state, the ISS will see that the increase in leakage rate associated with Core 3 affects the total power budget of PCD. Can be recognized. Nevertheless, if the processing capacity is required in a sudden notification, the advantage of shortening the waiting time may be better than the increase in power consumption expressed by putting the core 3 in the WFI idle state. . In this way, the ISS module is not used to actively handle the workload so that the user experience that may be evaluated in latency is not exceeded without exceeding the total power budget. It works to efficiently select the idle state for each core (not just core 3).

  FIG. 2 is a functional block diagram illustrating one embodiment of an on-chip system 102 for idle state selection and optimization in a heterogeneous multi-core PCD 100. As described above, embodiments of the system and method for idle state optimization may be used in any SoC having one or more processing cores, even if the core is heterogeneous. It is considered unnecessary. However, the various performance characteristics of the core at different operating temperatures and within different idle states offer great flexibility in minimizing latency considering managing the total power budget of the PCD. It is further believed that embodiments of the present systems and methods may be particularly useful in heterogeneous multi-core PCDs. To this end, the exemplary embodiments herein are primarily described in the context of heterogeneous multi-core PCDs, but embodiments of idle state optimization systems and methods include heterogeneous multi-core processing components. Those skilled in the art will recognize that they are not limited to PCD.

  Referring to the illustration of FIG. 2, an idle state selection (“ISS”) module 101 communicates with a heterogeneous multi-core processor 110, a monitor module 114, a scheduler 207, and an idle state lookup table (“LUT”) 24. . In operation, the monitor module 114 monitors temperature sensors 157 that may each be positioned to monitor the junction temperature associated with each of the cores 222, 224, 226, and 228, among others. The monitored temperature can be regarded as the operating temperature of the core and is correlated to the power being consumed by each of the cores 222, 224, 226 and 228, as explained above.

  The ISS module 101 receives the temperature as measured by the temperature sensor 157 via the monitor module 114 and determines the temperature and the current state (active state or idle state) of each core. Based on that, query LUT24. For each core, depending on its temperature and specific conditions, the ISS module 101 can query similar data to the graph shown in FIG. Also, for a given core, the ISS module 101 can query the LUT 24 to determine core performance characteristics when transitioning to an operating state other than its current operating state. ISS module 101 identifies or determines the workload in the queue that may require currently unavailable processing capacity through the active operation of any of the cores 222, 224, 226, and 228 Further communication with the scheduler 207 is possible.

  From various queries and monitored data, the ISS module 101 can calculate the current power consumption of all cores 222, 224, 226 and 228 and compare it to the total power budget associated with the PCD 100 be able to. If the full power budget is exceeded (or the threshold associated with the full power budget is exceeded), the ISS module 101 is asked to bring the migrated core back online as the active core. Recognizing that there is a trade-off in terms of latency added in the event that one or more of the cores 222, 224, 226, and 228 is moved from the active state to the idle state, or from the idle state to a different idle state You can choose to migrate. However, if there is a headroom in the total power budget, the ISS module 101 is one of the cores 222, 224, 226 and 228 to transition to an active state or an idle state associated with a short latency. One or more can be selected. In doing so, the ISS module 101 will “immediately respond” if the migrated core is needed to quickly deal with a sudden workload increase (or the next workload increase in the queue). It can be appreciated that a reduction in waiting time will be prioritized over an increase in power consumption associated with a transition to a “done” idle state (such as a transition from a retained idle state to a WFI idle state).

  With respect to selecting the cores 222, 224, 226, and 228 by the ISS module 101 to transition from one state to another, the selection is based on the total power budget of the PCD 100 and the power consumption expected to result from the transition. It is thought that it can be based on a comparison with the quantity level. To make that comparison, the ISS module 101 can compare the operating characteristics stored in the LUT 24 for a given core in relation to multiple idle states at its current operating temperature. Similarly, if the ISS module 101 recognizes that the power consumption of a core is correlated to its operating temperature, the ISS module 101 is associated with a given core at a given operating temperature when in different operating states. Compare levels to see the impact that a given core can have on the total power consumption of the PCD100 when transitioning from one operating state to another (e.g., from a power-down idle state to a WFI idle state) Judgment can be made.

  In particular, the illustration of FIG. 2 illustrates an idle state optimization system and method that queries the LUT 24 to determine the impact on latency and power consumption when the core transitions from one operational state to another. Although one embodiment is represented, other embodiments may not use the LUT 24, and in the alternative, it is contemplated that a mathematical function may be used to calculate the impact. Since the core power consumption when in a given operating state can be determined from the measured operating temperature of the core, embodiments of the present system and method have an impact on latency and power consumption. One skilled in the art will recognize that it can be easily calculated.

  In particular, the contents of the LUT 24 can be experimentally collected for each of the cores 222, 224, 226 and 228 according to bench tests and platform characteristics understood by those skilled in the art. In essence, for each combination of operating temperature and operating conditions, performance characteristics including latency and IDDq leakage rates are measured for each processing component 222, 224, 226 and 228 "in the factory" and stored in the LUT 24 ( Or used to generate a function). From that data, the ISS module 101 can determine which of the cores 222, 224, 226, and 228 from one operating state to minimize latency without exceeding the full power budget of the PCD 100 or chip 102. It can be determined whether it is possible to shift to another operating state. One skilled in the art will appreciate that the LUT 24 may reside in hardware and / or may take the form of software, depending on the particular embodiment. Further, as will be appreciated by those skilled in the art, the LUT 24 in hardware can be fused into silicon and the LUT 24 in software form can be stored in firmware.

  FIG. 3 is a functional block diagram of an exemplary non-limiting aspect of a PCD 100 in the form of a wireless telephone for implementing the method and system for idle state optimization. As shown, PCD 100 includes an on-chip system 102 that includes a heterogeneous multi-core central processing unit (“CPU”) 110 and an analog signal processor 126 coupled together. As will be appreciated by those skilled in the art, the CPU 110 can include a zeroth core 222, a first core 224, and an Nth core 230. Further, as will be appreciated by those skilled in the art, a digital signal processor (“DSP”) can be utilized in place of the CPU 110. Further, as understood in the technical field of heterogeneous multi-core processors, each core 222, 224, 230 is capable of handling workloads at different maximum voltage frequencies, and having different IDDq leakage rates at a given temperature and operating condition. Indicating, having a different waiting time to transition from a given idle operating state to an active state, etc.

  In general, the ISS module 101 is responsible for migrating cores between idle states so that the latency to come back online to handle the workload is minimized while adhering to the full power budget of chip 102. Responsible for monitoring and applying idle state optimization policies, including. The application of the idle state optimization policy helps the PCD 100 manage thermal conditions and / or thermal loads and make additional processing capacity available, for example, when burst loads are scheduled to process Can help avoid unnecessary waiting times. The ISS module 101 receives temperature data and other condition indicators from the monitor module 114 and uses that data to transition one or more of the cores 222, 224, 230 to different operating states. It is possible to determine the waiting time that may occur and the effect on power consumption. In this way, the ISS module 101 can optimize the user experience by positioning one or more cores to quickly respond to burst workloads, making one or more cores consume high power There is no need to leave a certain amount of operating state (active state, etc.).

  The monitor module 114 communicates with a plurality of operating sensors (eg, thermal sensor 157) and components distributed throughout the on-chip system 102, and the CPU 110 of the PCD 100 and the ISS module 101. Among other things, the monitor module 114 can communicate with and / or monitor off-chip components such as, but not limited to, a power source 188, a touch screen 132, and an RF switch 170. The ISS module 101 can cooperate with the monitor module 114 to identify conditions in the PCD that provide an opportunity to optimize the idle state of one or more processing components.

  As shown in FIG. 3, display controller 128 and touch screen controller 130 are coupled to CPU 110. Touch screen display 132 external to on-chip system 102 is coupled to display controller 128 and touch screen controller 130. The PCD 100 further includes a video decoder 134, such as a phase inversion line (“PAL”) decoder, a sequential color memory (“SECAM”) decoder, a National Television Standards Committee (“NTSC”) decoder, or any other type. A video decoder 134 may be included. Video decoder 134 is coupled to a multi-core central processing unit (“CPU”) 110. A video amplifier 136 is coupled to the video decoder 134 and the touch screen display 132. Video port 138 is coupled to video amplifier 136. As shown in FIG. 4, a universal serial bus (“USB”) controller 140 is coupled to CPU 110. A USB port 142 is coupled to the USB controller 140. Memory 112 and subscriber identification module (“SIM”) card 146 may also be coupled to CPU 110. Further, as shown in FIG. 3, a digital camera 148 may be coupled to the CPU 110. In the exemplary embodiment, digital camera 148 is a charge coupled device (“CCD”) camera or a complementary metal oxide semiconductor (“CMOS”) camera.

  As further shown in FIG. 3, a stereo audio codec 150 may be coupled to the analog signal processor 126. Further, an audio amplifier 152 may be coupled to the stereo audio codec 150. In the exemplary embodiment, first stereo speaker 154 and second stereo speaker 156 are coupled to audio amplifier 152. FIG. 3 shows that a microphone amplifier 158 may also be coupled to the stereo audio codec 150. Further, microphone 160 may be coupled to microphone amplifier 158. In certain aspects, a frequency modulation (“FM”) radio tuner 162 may be coupled to the stereo audio codec 150. An FM antenna 164 is coupled to the FM radio tuner 162. Further, stereo headphones 166 may be coupled to stereo audio codec 150.

  FIG. 3 further illustrates that a radio frequency (“RF”) transceiver 168 may be coupled to the analog signal processor 126. RF switch 170 may be coupled to RF transceiver 168 and RF antenna 172. As shown in FIG. 3, a keypad 174 may be coupled to the analog signal processor 126. Also, a mono headset 176 with a microphone may be coupled to the analog signal processor 126. Further, a vibrator device 178 may be coupled to the analog signal processor 126. FIG. 3 also shows that a power source 188, such as a battery, is coupled to the on-chip system 102 via a power management integrated circuit (“PMIC”) 180. In certain aspects, the power source 188 includes a rechargeable DC battery or a DC power source derived from an AC-DC converter connected to an alternating current (“AC”) power source.

  CPU 110 may also be coupled to one or more internal on-chip thermal sensors 157A and 157B, and one or more external off-chip thermal sensors 157C. On-chip thermal sensors 157A and 157B are based on a vertical PNP structure and are typically dedicated to complementary metal oxide semiconductor (“CMOS”) very large-scale integration (“VLSI”) circuits. Alternatively, a plurality of proportional to absolute temperature (“PTAT”) temperature sensors can be provided. The off-chip thermal sensor 157C can include one or more thermistors. The thermal sensor 157 can cause a voltage drop that is converted to a digital signal by an analog-to-digital converter (“ADC”) controller (not shown). However, other types of thermal sensors 157 may be utilized without departing from the scope of the present invention.

  In addition to being controlled and monitored by the ADC controller, the thermal sensor 157 may also be controlled and monitored by one or more ISS modules 101 and / or monitor modules 114. The ISS module 101 and / or the monitor module 114 can comprise software executed by the CPU 110. However, the ISS module 101 and / or monitor module 114 may also be formed from hardware and / or firmware without departing from the scope of the present invention. The ISS module 101 can be responsible for monitoring and applying an idle state optimization policy that can help the PCD 100 avoid critical temperatures while maintaining a high level of functionality.

  Returning to FIG. 3, touch screen display 132, video port 138, USB port 142, camera 148, first stereo speaker 154, second stereo speaker 156, microphone 160, FM antenna 164, stereo headphones 166, RF switch 170 , RF antenna 172, keypad 174, mono headset 176, vibrator 178, thermal sensor 157C, PMIC 180 and power supply 188 are external to on-chip system 102. However, the monitor module 114 also provides one or more instructions or instructions from one or more of these external devices by the analog signal processor 126 and CPU 110 to assist in real-time management of resources operable in the PCD 100. It should be understood that a signal can be received.

  In certain aspects, one or more of the method steps described herein are performed by executable instructions and parameters stored in memory 112 forming one or more ISS modules 101. Can do. These instructions forming ISS module 101 may be executed by CPU 110, analog signal processor 126, GPU 182 or another processor in addition to ADC controller 103 to perform the methods described herein. it can. Further, processor 110, 126, memory 112, instructions stored therein, or combinations thereof serve as a means for performing one or more of the method steps described herein. be able to.

  FIG. 4 is a schematic diagram illustrating an example software architecture 200 of the PCD of FIG. 3 to support an idle state optimization technique. Any number of algorithms may form an idle state optimization method that may be applied by the ISS module 101 when justified by one or more core temperature conditions, latency values and leakage rates. Can or can be part of it.

  As shown in FIG. 4, the CPU or digital signal processor 110 is coupled to the memory 112 via a bus 211. As mentioned above, the CPU 110 can be a multi-core heterogeneous processor having N core processors. That is, the CPU 110 includes a 0th core 222, a first core 224, and an Nth core 230. As known to those skilled in the art, the zeroth core 222, the first core 224, and the Nth core 230 are each available to support a dedicated application or program and have a heterogeneous score. As part of, different latency levels and different IDDq current leakage levels can be shown depending on their operating conditions. Alternatively, one or more applications or programs can be distributed for processing across more than one core of available heterogeneia scores.

  The CPU 110 can receive commands from the ISS module 101, which can comprise software and / or hardware. When implemented as software, the ISS module 101 includes instructions executed by the CPU 110, and the CPU 110 issues commands to other application programs being executed by the CPU 110 and other processors.

  The 0th core 222, the first core 224 to the Nth core 230 of the CPU 110 are integrated on a single integrated circuit die, or integrated or combined on separate dies in a multiple circuit package There is. Designers can couple the 0th core 222, the 1st core 224 to the Nth core 230 through one or more shared caches, for bus, ring, mesh, and crossbar topologies. Message or command transmission can be implemented through such a network topology.

  As is known in the art, the bus 211 can include multiple communication paths via one or more wired or wireless connections. The bus 211 may have additional elements that are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to allow communication. In addition, the bus 211 can include address, control, and / or data connections to allow proper communication between the above-described components.

  As shown in FIG. 4, when the logic used by PCD 100 is implemented in software, start logic 250, management logic 260, idle state optimization interface logic 270, applications in application storage 280, and file system 290 It should be noted that one or more of the portions may be stored on any computer-readable medium for use by or in connection with any computer-related system or method.

  In the context of this document, a computer-readable medium is an electronic, magnetic, optical or other physical capable of storing or storing computer programs and data for use by or in connection with a computer-related system or method. It is a device or means. Various logic elements and data storage devices execute instruction, such as a computer-based system, a system including a processor, or other system, that is capable of retrieving instructions and executing instructions from an instruction execution system, apparatus, or device. It can be embodied in any computer readable medium for use by, or in connection with, a system, apparatus or device. In the context of this document, a “computer-readable medium” is any medium capable of storing, communicating, propagating, or transferring a program for use by or in connection with an instruction execution system, apparatus, or device. It can be a means.

  The computer readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples of computer readable media (non-comprehensive list) include: electrical connections (electronic) with one or more wires, portable computer diskettes (magnetic), Random access memory (RAM) (electronic), read-only memory (ROM) (electronic), erasable programmable read-only memory (EPROM, EEPROM, or flash memory) (electronic), optical fiber (optical), And portable compact disc read only memory (CDROM) (optical). The program may be electronically captured using, for example, optical scanning of paper or other media, and then compiled, interpreted, or otherwise processed as appropriate, and then stored in computer memory It should be noted that the computer readable medium can also be paper on which the program is printed, or another suitable medium.

  In alternative embodiments where one or more of start logic 250, management logic 260, and possibly idle state optimization interface logic 270 are implemented in hardware, each of the various logics may be well known in the art. The following known techniques: discrete logic circuits with logic gates to perform logic functions on data signals, application specific integrated circuits (ASIC) with appropriate combinational logic gates, programmable gate arrays (PGA) ), A field programmable gate array (FPGA), etc., or a combination thereof.

  The memory 112 is a non-volatile data storage device such as a flash memory or solid state memory device. Although shown as a single device, the memory 112 may be a distributed memory device that uses separate data storage devices coupled to the digital signal processor 110 (or additional processor core).

  The start logic 250 determines the operating states of the available cores, such as the 0th core 222, the 1st core 224 to the Nth core 230, to transition to different operating states, one of which One or more executable instructions for selectively identifying, loading and executing a selection program for selecting a plurality are included. Management logic 260 includes one or more executable instructions for terminating the idle state optimization processor and selectively identifying, loading, and executing a more suitable alternative program. The management logic 260 is configured to perform these functions at run time or while the PCD 100 is powered on and used by an operator of the device. Alternative programs can be found in the program storage 296 of the embedded file system 290.

  The alternative program may operate according to one or more signals provided by the ISS module 101 and / or the monitor module 114 when executed by one or more of the core processors of the digital signal processor. In this regard, module 114 can provide one or more indicators of junction temperature in response to control signals originating from ISS module 101.

  Interface logic 270 presents external inputs, manages external inputs, and interacts with external inputs to observe, configure, or otherwise update information stored in embedded file system 290 One or more executable instructions for In one embodiment, interface logic 270 can operate with manufacturer input received via USB port 142. These inputs can include one or more programs that are to be deleted from or added to the program storage device 296. Alternatively, the input can include edits or changes to one or more of the programs in program storage device 296. Further, the input may specify one or more changes to one or both of start logic 250 and management logic 260, or an overall alternative. As an example, the input may include a change to management logic 260 that instructs the ISS module 101 to recognize an increase in the total power budget when the skin temperature of the PCD 100 is below a certain threshold.

  Interface logic 270 allows the manufacturer to controlably configure and adjust the end user experience under the prescribed operating conditions of PCD 100. When memory 112 is flash memory, can one or more of start logic 250, management logic 260, interface logic 270, application programs in application storage 280, or information in embedded file system 290 be edited? Can be substituted or otherwise changed. In some embodiments, interface logic 270 allows end users or PCD 100 operators to search and locate information in initiating logic 250, management logic 260, applications in application storage 280, and embedded file system 290. , May be able to change or substitute. The operator can make changes that will be implemented at the next start of the PCD 100 using the resulting configured interface. Alternatively, the operator can make changes that are performed during runtime using the resulting configured interface.

  The embedded file system 290 includes an idle state lookup table 24 arranged in a hierarchy. In this regard, the file system 290 performs the performance characteristics of the various cores 222, 224, 226, 228 when operating according to a specific operating state (such as a holding idle state or a WFI idle state) at a specific operating temperature. A reserved portion of the total file system capacity for storing information associated with the.

  FIG. 5 is a logic flow diagram illustrating one embodiment of a method 500 for idle state optimization in PCD 100 of FIG. In the embodiment of FIG. 5, the ISS module 101 is aware of the total power budget associated with the PCD 100, chip 102, processor 110, etc. As will be appreciated by those skilled in the art, the power budget represents the target power consumption level and ideally cannot be exceeded by the total power consumption of the cores 222, 224, 226, 228. In particular, by selecting one or more of the cores 222, 224, 226, 228 to transition from one operating state to another (e.g., from a power sag state to a WFI state), the ISS module 101 is the total power consumption of cores 222, 224, 226, 228 and if one or more of the idle cores 222, 224, 226, 228 is needed to handle the workload Can have a direct impact on the waiting time you will experience. Therefore, at block 505 of method 500, the maximum power budget is determined.

  At block 510, the temperature associated with the core 222, 224, 226, 228 junction temperature (ie, operating temperature) is monitored by the monitor module 114 and provided to the ISS module 101. At block 515, the LUT 24 is queried using the monitored temperature. As noted above, the LUT 24 may contain data for each of the cores 222, 224, 226, 228 that represents the functional characteristics of the core when the core is operating at a specific temperature and in a specific mode of operation. it can. From the inquiry, the power leakage level for each core can be obtained. For example, returning briefly to Figure 1, if the core is in the operating state represented by the table and is at operating temperature, the leak rate for any of cores 0, 1, 2, and 3 can be determined. it can. Also, as explained above, in certain embodiments, instead of querying the LUT 24, it is also possible to use a function that simply calculates the core power consumption level based on its operating temperature.

  At block 520, the active leakage rates of all cores 222, 224, 226, 228 are summed and compared to the power budget. At decision block 525, if the total active leakage rate approximately matches or exceeds the power budget determined at block 505, then return to block 510 according to the “no” branch and method 500 continues. However, if the total active leakage rate is relatively lower than the power budget at decision block 525, the method 500 can follow the “yes” branch and proceed to block 530.

  If the method 500 proceeds to block 530, the ISS module 101 may select one or more of the cores 222, 224, 226, 228 so that the latency value is reduced without exceeding the power budget. The opportunity to adjust the operating state of the can be obtained. In that case, in block 530, the active setting for each of the cores 222, 224, 226, 228 is determined. The active setting can include, but is not limited to, the current operating state (ie, whether the core is active or idle) and the operating temperature. From the current settings determined at block 530, the ISS module 101 can identify one or more cores that are suitable for transitioning to different operating states. As an example, the ISS module 101 can determine that the core 222 is actively processing a workload, but the cores 224 and 226 are in a power droop idle state and the core 228 is in a holding idle state. In such a scenario, the ISS module 101 can conclude that the cores 224, 226 and 228 are all suitable for transitioning to different idle states.

  Returning to method 500, at block 535, the ISS module 101 queries the LUT 24 for each suitable core (or uses a function associated with each suitable core), and one or more of the suitable cores are in different operating states. Determine the impact on power consumption and latency that can be achieved when migrating. At block 540, the ISS module 101 can aggregate the power consumption levels for various combinations of transitions. Referring back to the example given above, where the ISS module 101 determines that cores 224 and 226 are in a power droop idle state and core 228 is in a holding idle state, the transition combination will cause core 226 to power droop. Leaving the core 224 in the hold state and the core 228 in the WFI state. In particular, the transition can improve the latency required for cores 224 and 228 to transition to an active state that can handle burst loads at any time.

  For various combinations, the possible impact on power consumption that may result from idle state transitions is compared at decision block 545 to the power budget. If the total of all identified transition combinations exceeds the power budget, there may not be enough room in the power budget for any core to transition to the idle state associated with the reduced latency So, return to block 510 according to the “no” branch. With respect to decision block 545, it is contemplated that the method 500 can “loop” through the various combinations until the optimal transition combination is identified. It is also contemplated that a combination may include an operational state transition for only a single processing core, or may include a transition for multiple cores.

  Returning to method 500, if it is determined at decision block 545 that the expected total power consumption level for a particular combination of core transitions is less than the power budget, block according to the “yes” branch. Proceeding to 550, the ISS module 101 performs the specified idle state transition. In this way, the ISS module 101 has the latency required to bring the idle core online to handle the workload without unduly affecting the power consumption and thermal energy level of the PCD 100. The idle state of one or more cores 222, 224, 226, 228 can be optimized to be minimized. Advantageously, in doing so, the ISS module 101 optimizes the user experience by positioning the various core states to quickly respond to workload processing requests.

  In order for the present invention to function as described above, certain steps in the process or process flow described herein necessarily precede other steps. However, the invention is not limited to the order of steps described if such order or sequence does not change the functionality of the invention. That is, it will be appreciated that some steps may be performed before, after, or in parallel (substantially simultaneously) with other steps without departing from the scope and spirit of the invention. In some cases, some steps may be omitted or not performed without departing from the invention. Further, terms such as “after that”, “after”, “next” are not intended to limit the order of the steps. These terms are only used to guide the reader to understand the description of the exemplary method.

  Further, those skilled in the art of programming can write computer code or appropriate hardware and / or circuitry to implement the disclosed invention without difficulty, for example, based on the flowcharts and associated descriptions herein. Can be specified. Thus, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary to fully understand the methods of making and using the present invention. The inventive functionality of the claimed computer-implemented process is described in more detail in the foregoing description, along with drawings that may illustrate various process flows.

  In one or more exemplary aspects, the functions described above can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer readable media can be RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage device, or instructions or data structure Any other medium that can be used to carry or store the desired program code in the form of and can be accessed by a computer can be included.

  Also, any connection is legally called a computer readable medium. For example, the software uses a coaxial cable, fiber optic cable, twisted pair wire, digital subscriber line (DSL), or wireless technology such as infrared, wireless, and microwave to websites, servers, or other remote When transmitted from a source, coaxial cables, fiber optic cables, twisted pair wires, DSL, or wireless technologies such as infrared, radio, and microwave are included in the media specification.

  Discs and discs, as used herein, are compact discs (“CDs”), laser discs (discs), optical discs (discs), digital versatile discs (discs) ) ("DVD"), floppy disk and Blu-ray disc, the disk usually plays data magnetically, while the disc uses a laser to optically reproduce the data. To play. Combinations of the above should also be included within the scope of computer-readable media.

  Accordingly, although selected aspects have been shown and described in detail, various alternatives and modifications may be made in the present invention without departing from the spirit and scope of the invention as defined by the following claims. It will be appreciated that can be done.

24 Idle state lookup table
100 heterogeneous multi-core PCD
101 Idle state selection (ISS) module
102 On-chip system
110 Heterogeneous multi-core processor (CPU)
112 memory
114 Monitor module
126 Analog signal processor
128 display controller
130 Touch screen controller
132 Touch screen display
134 Video decoder
136 Video amplifier
138 video port
140 Universal Serial Bus (USB) controller
142 USB port
146 Subscriber Identification Module (SIM) card
148 Digital camera
150 stereo audio codecs
152 audio amplifier
154 First stereo speaker
156 Second stereo speaker
157 Temperature sensor
157A temperature sensor
157B temperature sensor
157C temperature sensor
158 Microphone amplifier
160 microphone
162 Frequency modulation (FM) radio tuner
164 FM antenna
166 Stereo headphones
168 radio frequency (RF) transceiver
170 RF switch
172 RF antenna
174 keypad
176 Mono headset with microphone
178 Vibrator device
180 Power Management Integrated Circuit (PMIC)
188 power supply
207 Scheduler
211 Bus
222 core
224 core
226 core
228 core
230 cores
250 start logic
260 Management logic
270 Idle state optimization interface logic
280 Application storage
290 file system
296 program storage

Claims (40)

A method for idle state optimization in a portable computing device (“PCD”) comprising:
Determining a power budget, wherein the power budget represents a maximum total power consumption level for a plurality of processing cores;
Determining a current total power consumption level for the plurality of processing cores;
Comparing the current total power consumption level to the power budget;
Transitioning at least one suitable processing core from a first idle state to a second idle state if the current total power consumption level is lower than the power budget, the at least one suitable processing A method for idle state optimization in a portable computing device (“PCD”), wherein a latency value associated with a core is reduced by the transition from the first idle state to the second idle state.   The method of claim 1, wherein the current total power consumption level is determined based on operating temperatures of the plurality of processing cores.   The method of claim 2, wherein the current total power consumption level is determined from a lookup table.   The method of claim 2, wherein the current total power consumption level is determined from a mathematical function associated with each of the plurality of processing cores.   The method of claim 1, wherein the first idle state is a power down state and the second idle state is a wait for interrupt (“WFI”) state.   2. The method of claim 1, wherein the first idle state is a sudden power reduction state and the second idle state is a holding state.   2. The method of claim 1, wherein the first idle state is a holding state and the second idle state is a WFI state.   The method of claim 1, wherein the suitable processing core is suitable for transitioning because it exists in an idle operating state.   The method of claim 1, further comprising receiving a workload to be processed and transitioning the processing core from the second idle state to an active state.   The PCD includes at least one of a cellular phone, a satellite phone, a personal digital assistant (“PDA”), a smartphone, a navigation device, a tablet, a smart book, a media player, and a laptop computer. the method of. A computer system for idle state optimization in a portable computing device ("PCD") comprising:
Comprising an idle state selection (“ISS”) module,
Configured to determine a power budget, wherein the power budget represents a maximum total power consumption level for a plurality of processing cores;
Determining a current total power consumption level for the plurality of processing cores;
Comparing the current total power consumption level to the power budget;
If the current total power consumption level is lower than the power budget, the at least one suitable processing core is configured to transition from a first idle state to a second idle state, and the at least one suitable processing core A computer system for idle state optimization in a portable computing device ("PCD"), wherein a latency value associated with a core is reduced by the transition from the first idle state to the second idle state .   12. The computer system of claim 11, wherein the current total power consumption level is determined based on operating temperatures of the plurality of processing cores.   The computer system of claim 12, wherein the current total power consumption level is determined from a look-up table.   The computer system of claim 12, wherein the current total power consumption level is determined from a mathematical function associated with each of the plurality of processing cores.   12. The computer system of claim 11, wherein the first idle state is a sudden power reduction state and the second idle state is an interrupt waiting (“WFI”) state.   12. The computer system according to claim 11, wherein the first idle state is a power suddenly decreasing state, and the second idle state is a holding state.   12. The computer system according to claim 11, wherein the first idle state is a holding state and the second idle state is a WFI state.   12. The computer system of claim 11, wherein the suitable processing core is suitable for transitioning because it exists in an idle operating state.   12. The computer system of claim 11, wherein the ISS module is further configured to recognize a workload to be processed and transition the processing core from the second idle state to an active state.   The PCD includes at least one of a cellular phone, a satellite phone, a personal digital assistant (“PDA”), a smartphone, a navigation device, a tablet, a smart book, a media player, and a laptop computer. Computer system. A computer system for idle state optimization in a portable computing device ("PCD") comprising:
Means for determining a power budget, the power budget representing a maximum total power consumption level for a plurality of processing cores;
Means for determining a current total power consumption level for the plurality of processing cores;
Means for comparing the current total power consumption level with the power budget;
Means for transitioning at least one suitable processing core from a first idle state to a second idle state if the current total power consumption level is lower than the power budget, the at least one Latency values associated with appropriate processing cores are shortened by the transition from the first idle state to the second idle state, for idle state optimization in a portable computing device (“PCD”). Computer system.   24. The computer system of claim 21, wherein the current total power consumption level is determined based on operating temperatures of the plurality of processing cores.   23. The computer system of claim 22, wherein the current total power consumption level is determined from a lookup table.   23. The computer system of claim 22, wherein the current total power consumption level is determined from a mathematical function associated with each of the plurality of processing cores.   23. The computer system of claim 21, wherein the first idle state is a sudden power reduction state and the second idle state is an interrupt waiting (“WFI”) state.   22. The computer system according to claim 21, wherein the first idle state is a power suddenly decreasing state, and the second idle state is a holding state.   22. The computer system according to claim 21, wherein the first idle state is a holding state and the second idle state is a WFI state.   22. The computer system of claim 21, wherein the suitable processing core is suitable for transitioning because it exists in an idle operating state.   The computer system of claim 21, further comprising means for receiving a workload to be processed and means for transitioning the processing core from the second idle state to an active state.   The computer of claim 21, wherein the PCD includes at least one of a cellular phone, a satellite phone, a personal digital assistant (PDA), a smartphone, a navigation device, a tablet, a smart book, a media player, and a laptop computer. system. A computer program product comprising a computer usable medium embodying computer readable program code, said computer readable program code for implementing a method for idle state optimization in a portable computing device ("PCD") Configured to be performed, the method comprising:
Determining a power budget, wherein the power budget represents a maximum total power consumption level for a plurality of processing cores;
Determining a current total power consumption level for the plurality of processing cores;
Comparing the current total power consumption level to the power budget;
Transitioning at least one suitable processing core from a first idle state to a second idle state if the current total power consumption level is lower than the power budget, the at least one suitable processing A computer program product, wherein a latency value associated with a core is reduced by the transition from the first idle state to the second idle state.   32. The computer program product of claim 31, wherein the current total power consumption level is determined based on operating temperatures of the plurality of processing cores.   The computer program product of claim 32, wherein the current total power consumption level is determined from a look-up table.   The computer program product of claim 32, wherein the current total power consumption level is determined from a mathematical function associated with each of the plurality of processing cores.   32. The computer program product of claim 31, wherein the first idle state is a rapid power reduction state and the second idle state is a wait for interrupt (“WFI”) state.   32. The computer program product according to claim 31, wherein the first idle state is a power suddenly decreasing state and the second idle state is a holding state.   32. The computer program product of claim 31, wherein the first idle state is a holding state and the second idle state is a WFI state.   32. The computer program product of claim 31, wherein the suitable processing core is suitable for transitioning because it exists in an idle operating state.   32. The computer program product of claim 31, further comprising receiving a workload to be processed and transitioning the processing core from the second idle state to an active state.   32. The computer of claim 31, wherein the PCD comprises at least one of a cellular phone, a satellite phone, a personal digital assistant (PDA), a smartphone, a navigation device, a tablet, a smart book, a media player, and a laptop computer. Program product.

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