CN203422642U - Multichannel dynamic signal acquisition card based on PXI bus - Google Patents

Abstract

The utility model provides a multichannel dynamic signal acquisition card based on a PXI bus. The acquisition card comprises a multipath simulation signal conditioning circuit, an AD conversion circuit, a frequency multiplication and phase-locked loop circuit, a DDS circuit, an AD clock distribution circuit, a PCI interface circuit, a reference source circuit, a FPGA circuit, a constant current source circuit, a TEDS intelligent sensor interface, etc. The dynamic signal acquisition card can provide a function of high-precision synchronous acquisition of a multichannel simulation signal for a test measure user. The acquisition card can directly acquire an electric quantity signal, provide a function of acquiring non electrical quantities such as speed, microphone, etc. based on IEPE, satisfy the test requirement of fields such as sound and vibration analysis, etc. to the greatest extent, and provide TEDS support for an intelligent sensor following the IEEE1451.4 Class 1 standard.

Description

Hyperchannel dynamic signal acquisition card based on PXI bus

Technical field

The utility model relates to hyperchannel dynamic signal acquisition card, is specifically related to a kind of hyperchannel dynamic signal acquisition card based on PXI bus, belongs to virtual instrument technique field.

Background technology

At present, the external hyperchannel dynamic signal acquisition snap gauge based on PXI bus is intended port number and is 8 to the maximum, and its high sampling rate is 102.4kSa/s, does not support TEDS intelligent sensor interface, and above-mentioned technical parameter is difficult to adapt to the technical requirement improving constantly; Domestic at present also without the hyperchannel dynamic signal acquisition card release based on PXI bus.

Summary of the invention

The purpose of this utility model is to provide a kind of hyperchannel dynamic signal acquisition card based on PXI bus, has mainly solved prior art sampling rate and the lower problem of dynamic range.

The hyperchannel dynamic signal acquisition card based on PXI bus that the utility model provides, on the PXI of 3U size board, be provided with nearly 8 independently signal condition and acquisition channels, high sampling rate is 204.8kSa/s, the dynamic signal acquisition of supporting TEDS intelligent sensor interface.

Concrete technical solution of the present utility model is as follows:

Should comprise programmable logic controller (PLC) and analog signal modulate circuit by the hyperchannel dynamic signal acquisition card based on PXI bus, analog signal conditioner circuit connects with one end of programmable logic controller (PLC), reference source circuit, constant-current source circuit, AD clock distribution circuit and TEDS interface circuit respectively; The other end of described AD clock distribution circuit is connected with PXI interface circuit by DDS circuit; Described PXI interface circuit is also directly connected with programmable logic controller (PLC) respectively, by frequency multiplication, is connected with programmable logic controller (PLC) with phase-locked loop circuit; Described programmable logic controller (PLC) is also connected with Trigger Function modular circuit with DDR circuit.

Above-mentioned PXI interface circuit is comprised of protocol converter, PXI bus, PXI Trigger Bus and clock circuit, one end of protocol converter, PXI Trigger Bus and clock circuit is all connected with PXI bus, the other end of protocol converter and PXI Trigger Bus is connected with programmable logic controller (PLC), and the other end of clock circuit is connected with phase-locked loop circuit with frequency multiplication.

Above-mentioned analog signal conditioner circuit comprises a plurality of difference or pseudo-differential single channel analog signal conditioner circuit independently, and each passage has 1 independently 24 sigma-delta AD converter, each passage independent parallel sampling, and sampling rate is by the downward frequency division of DDS circuit.

Said reference source circuit comprises successively the high stability reference source that connects and for increasing the amplifier of driving force.

Above-mentioned constant-current source circuit is the constant-current circuit of zero-temperature coefficient.

Above-mentioned TEDS interface circuit is typical 2 line constant current-supplying sensors, common signal line.

Above-mentioned frequency multiplier circuit and phase-locked loop circuit are comprised of integrated voltage controlled oscillator and phase-locked loop chip.

Above-mentioned DDS circuit is the DDS chip of built-in 10 figure place weighted-voltage D/A converters and voltage comparator.

The utility model has the advantage of:

It is 204.8kSa/s analog acquisition passage that the hyperchannel dynamic signal acquisition card based on PXI bus that the utility model provides not only provides nearly 8 high sampling rates, the TEDS intelligent sensor interface of two-wire system is also provided for each passage simultaneously, can, so that user builds dynamic signal acquisition system, effectively reduces system cost, there is good engineering practical value.

Specifically, the utility model possesses following features:

Should adopt highly integrated chip by the hyperchannel dynamic signal acquisition card based on PXI bus, nearly 8 analog channels on the PXI of monolithic 3U board, have been designed, adopt 24 sigma-delta AD converter of AD company, high sampling rate is 204.8kSa/s, has realized hyperchannel and high sampling rate; Adopt DDS circuit to produce the sampling clock of AD converter, sampling rate step-length is micro-hertz of sampling of 36.38uS/s(), sampling rate is arranged meticulous flexibly, simultaneously, synchronism between passage is high, and interchannel synchronism is mainly to guarantee by the consistance of sampling clock and the consistance of analog channel.

Adopt multiplexer and programme-controlled gain instrument amplifier PGA, provide difference and pseudo-differential two kinds of input modes, be convenient to user and select; Adopt low-noise simulation signal condition technology, programme-controlled gain, program control filtering and multiple spot collimation technique and sigma-delta AD converter, capture card dynamic range reaches 110dB, and the signal amplitude of collection, from ± 30uV to ± 10V, has improved dynamic range.

The acquisition function of the non electrical quantities such as acceleration based on IEPE, microphone is provided.Adopt single chip integrated constant current source chip, for the sensors such as the acceleration based on IEPE, microphone provide conditioning.For following the intelligent sensor of the CLASS1 standard of IEEE1451.4, provide TEDS support.

Accompanying drawing explanation

Fig. 1 is hyperchannel dynamic signal acquisition card schematic diagram;

Fig. 2 is single channel analog signal conditioner circuit diagram;

Fig. 3 is reference source circuit figure;

Fig. 4 is constant-current source circuit figure;

Fig. 5 is frequency multiplication and phase-locked loop circuit figure;

Fig. 6 is TEDS interface circuit figure;

Fig. 7 is DDS circuit diagram;

Fig. 8 is AD clock distribution circuit figure;

Fig. 9 is Trigger Function module circuit diagram;

Figure 10 is pci interface circuit diagram;

Figure 11 is DDR circuit diagram;

Figure 12 is programmable logic controller (PLC) inner function module circuit diagram;

Accompanying drawing is detailed: 2-analog signal conditioner circuit; 3-reference source circuit; 4-constant-current source circuit; 5-frequency multiplication and phase-locked loop circuit; 6-TEDS interface circuit; 7-DDS circuit; 8-AD clock distribution circuit; 9-Trigger Function modular circuit; 10-PXI interface circuit; 11-DDR circuit; 13-programmable logic controller (PLC).

Embodiment

Below in conjunction with Figure of description, describe embodiment of the present utility model in detail.

This capture card can be divided into the circuit such as analog signal conditioner, AD conversion, frequency multiplication and phaselocked loop, DDS and AD clock distribution, pci interface, reference source circuit, FPGA, constant current source, TEDS intelligent sensor interface function.Fig. 1 is hyperchannel dynamic signal acquisition card schematic diagram.

From the simulating signal of sensor input first send into that multiplexer exchanges, direct current, ground connection coupling select.The output signal of multiplexer is connected to accurate program controlled gain amplifier PGA, and PGA to the maximum input range that approaches AD, can guarantee that signal has maximum signal to noise ratio (S/N ratio) by analog signal conditioner like this.PGA is single-ended signal output, and AD is difference input, so just must increase the single-ended transfer difference amplifier of one-level precision.Differential signal, before entering AD converter, also must carry out analogue low pass filtering processing to noise, and 24 sigma-delta-converter AD7764 that filtered signal is finally delivered to difference input again carry out analog to digital conversion.Fig. 2 is single channel analog signal conditioner circuit diagram.

The AD voltage reference of Low Drift Temperature, high stability is the assurance of high-precision number of degrees extraction system.In the design, use the ADR444 of LiaoAD company as the high stability reference source of all AD converter.It is 1ppm/ ℃ that ADR444 temperature is floated representative value, is 3ppm/ ℃ to the maximum, and noise is 1.8uVp-p, and output voltage is 4.096V.4.096V reference voltage is followed by amplifier AD706 again, increases after driving force for 8 tunnel AD converter.Fig. 3 is reference source circuit figure.

Constant current source adopts LM334 chip.The integrated three end adjustable constant-flow sources of monolithic that LM334 ShiNS company produces, during use, as long as external 2 resistance R 1, R2(R2=10R1) and a diode IN457 just can form the constant current source of zero-temperature coefficient.Select different R1 can make constant current value adjustable continuously to l0mA from l uA.Fig. 4 is constant-current source circuit figure.

The TEDS circuit of this capture card is typical 2 line constant current-supplying sensors, common signal line.By the polarity of reverse signal line, diode allows sequential access amplifier or TEDS storer.When gauge tap is during in " analog " position, the constant current source electric current of collection plate is that amplifier is powered by the diode of signal wire and top.Transmitter output shows as analog voltage on signal wire.When gauge tap is during in " digital " position, memory device is powered by the diode of below by negative logic power supply.In circuit, provided the pull down resistor (Rt) between TEDS memory chip terminal.This resistance, for discharging the electric charge of memory circuitry and lead capacitance, guarantees that logical zero level meets time slot requirement.The compatible sensor of IEEE1451.4 is connected to TP4 by analog/digital switch.TP2 and TP6 are connected to respectively output (writing) and input (reading) port of FPGA, are used for reading and writing the TEDS information of intelligent sensor.Fig. 6 is TEDS interface circuit figure.

Voltage controlled oscillator VCXO produces the local clock of 40MHz, utilizes PLL chip the 10M clock lock in this clock and PXI bus.40MHz clock is for functional circuits such as FPGA, PCI9054, DDR.Fig. 5 is frequency multiplication and phase-locked loop circuit figure.

The sampling rate of this capture card is that 1kS/s is adjustable to 204.8kS/s, for guaranteeing the accuracy of 24 bit AD sample rates and being convenient to user, arranges, and the sampling clock of AD is produced or decided from the clock of star-like triggering line transmission by the DDS circuit on board.DDS built-in chip type 10 figure place weighted-voltage D/A converter and voltage comparators, can export the square wave of required frequency easily.Fig. 7 is DDS circuit diagram.

In order to increase driving force, DDS mono-road clock output becomes multipath clock again after the clock buffer CDCLVC1110PW of low jitter, for the AD converter of this board or be routed on star-like triggering line the AD converter for other board.Fig. 8 is AD clock distribution circuit figure.

Trigger source is divided into software triggering, analog channel triggering, external digital triggering, star-like triggering and PXI_TRIG[0..7] backboard triggering.Fig. 9 is Trigger Function module circuit diagram.

PCI9054 realizes the effect of PCI bridge, by complicated PCI protocol conversion, is a kind of relatively simple bus interface.Figure 10 is pci interface circuit diagram.

DDR partial circuit is selected the 32M X16BIT chip of MICRON company, and Figure 11 is DDR circuit diagram.

FPGA mainly realizes following major function:

1, PCI9054 is controlled, realize the communication with pci bus;

2, DDR chip is read and write to control, realize the buffer memory of AD image data;

3, the triggering configuration to each acquisition channel, controls multi-channel A/D synchronous acquisition;

4, DDS chip is controlled, realized generation and the switching of AD sample frequency;

5, support intelligent sensor TEDS interface, realize the read-write operation to sensor TEDS;

6, support 3 kinds of data acquisition schemes: delayed trigger, leading triggering, continuous trigger.

Fpga chip used is the XC6SLX45-FG676 of SPARTAN-6, and configuring chip is XCF04S.

In the design, FPGA is the control center of whole acquisition system.FPGA internal main will be divided into: acquisition control module, clock-reset module, local bus interface module, analog channel control module, routing module control, DDR control module, DDS sampling clock control module, simulation trigger control module and TEDS control module, EEPROM control module etc.Figure 12 is FPGA inner function module circuit diagram.

Claims (8)

1. the hyperchannel dynamic signal acquisition card based on PXI bus, comprise programmable logic controller (PLC), it is characterized in that: also comprise analog signal conditioner circuit, described analog signal conditioner circuit is connected with programmable logic controller (PLC), reference source circuit, constant-current source circuit, AD clock distribution circuit and one end of TEDS interface circuit respectively; The other end of described AD clock distribution circuit is connected with PXI interface circuit by DDS circuit; Described PXI interface circuit is also directly connected with programmable logic controller (PLC) respectively, by frequency multiplication, is connected with programmable logic controller (PLC) with phase-locked loop circuit; Described programmable logic controller (PLC) is also connected with Trigger Function modular circuit with DDR circuit.

2. the hyperchannel dynamic signal acquisition card based on PXI bus according to claim 1, it is characterized in that: described PXI interface circuit is comprised of protocol converter, PXI bus, PXI Trigger Bus and clock circuit, one end of protocol converter, PXI Trigger Bus and clock circuit is all connected with PXI bus, the other end of protocol converter and PXI Trigger Bus is connected with programmable logic controller (PLC), and the other end of clock circuit is connected with phase-locked loop circuit with frequency multiplication.

3. the hyperchannel dynamic signal acquisition card based on PXI bus according to claim 1 and 2, it is characterized in that: described analog signal conditioner circuit comprises a plurality of difference or pseudo-differential single channel analog signal conditioner circuit independently, each passage has 1 independently 24 sigma-delta AD converter, each passage independent parallel sampling, sampling rate is by the downward frequency division of DDS circuit.

4. the hyperchannel dynamic signal acquisition card based on PXI bus according to claim 3, is characterized in that: described reference source circuit comprises the high stability reference source that connects successively and for increasing the amplifier of driving force.

5. the hyperchannel dynamic signal acquisition card based on PXI bus according to claim 3, is characterized in that: the constant-current source circuit that described constant-current source circuit is zero-temperature coefficient.

6. the hyperchannel dynamic signal acquisition card based on PXI bus according to claim 3, is characterized in that: described TEDS interface circuit is typical 2 line constant current-supplying sensors, common signal line.

7. the hyperchannel dynamic signal acquisition card based on PXI bus according to claim 3, is characterized in that: described frequency multiplication and phase-locked loop circuit are comprised of integrated voltage controlled oscillator and phase-locked loop chip.

8. the hyperchannel dynamic signal acquisition card based on PXI bus according to claim 3, is characterized in that: described DDS circuit is the DDS chip of built-in 10 figure place weighted-voltage D/A converters and voltage comparator.

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