CN205139911U - Timer conter based on PXI bus - Google Patents

Abstract

The utility model relates to a virtual instrument technical field, concretely relates to timer conter based on PXI bus. A timer conter based on PXI bus, includes analog circuit part and digital circuit part, analog circuit part including parallel two sets of, first group is a AD converting circuit who connects gradually, first impedance switching circuit, an attenuator circuit, an amplifier circuit and first comparator, two AD converting circuit, second impedance switching circuit, two attenuator circuit, two amplifier circuit and the second comparator of second group for connecting gradually, it is connected to the second comparator still to be equipped with a branch road between first amplifier and the first comparator, digital circuit part including PXI interface, clock circuit and FPGA, wherein, PXI interface and clock circuit are equallyd divide and are do not connected FPGA, FPGA is all connected to first comparator and second comparator. The utility model discloses the realization is to analog signal and data signal's measurement.

Description

Based on the timer conter of PXI bus

Technical field

The utility model relates to virtual instrument technique field, is specifically related to a kind of timer conter based on PXI bus.

Background technology

At present, the timer conter of the physical quantity such as domestic and international survey frequency, cycle counts master with desk-top frequency.Desk-top instrument not only volume is bigger than normal, and inconvenience is integrated in automatization test system.Domestic and international minority can only measure digital signal based on the timer conter module of PXI bus, cannot direct measure analog signals.

Summary of the invention

The utility model is intended to propose a kind of timer counter based on PXI bus can measuring digital signal and simulating signal.

The technical solution of the utility model is:

Based on a timer conter for PXI bus, comprise analog module and digital circuit blocks;

Described analog module comprises parallel two groups, and first group is the first A/D convertor circuit, the first impedance commutation circuit, the first attenuator circuit, the first amplifying circuit and the first comparer that connect successively; Second group is the second A/D convertor circuit, the second impedance commutation circuit, the second attenuator circuit, the second amplifying circuit and the second comparer that connect successively; Also be provided with a branch road between described first amplifying circuit and the first comparer and be connected to the second comparer;

Described digital circuit comprises PXI interface, clock circuit and FPGA; Wherein, PXI interface and clock circuit connect FPGA respectively;

First comparer and the second comparer all connect FPGA.

Described FPGA is also connected with a road GATE gate input channel.

Described PXI interface connects FPGA by PXI interface circuit.

The first described comparer and the second comparer are supper-fast comparer.

Described clock circuit is TCXO clock circuit.

Technique effect of the present utility model is:

The utility model comprises mimic channel and digital circuit two-way input channel, realizes the measurement to simulating signal and digital signal.Preferably, adopt the TCXO clock circuit of high stability, the frequency measurement of the highest 1000MHZ can be realized.

Accompanying drawing explanation

Fig. 1 is the total principle schematic of the utility model.

Fig. 2 is that the utility model always applies schematic diagram.

Fig. 3 is the utility model FPGA structural representation.

Fig. 4 is the utility model power circuit principle figure.

Wherein, 1-first A/D convertor circuit, 2-first impedance commutation circuit, 3-first attenuator circuit, 4-second A/D convertor circuit, 5-second impedance commutation circuit, 6-second attenuator circuit, 7-first amplifying circuit, 8-second amplifying circuit, 9-PXI interface, 10-PXI interface circuit, 11-clock circuit, 12-first comparer, 13-first comparer, 14-FPGA.

Embodiment

Based on a timer conter for PXI bus, comprise analog module and digital circuit blocks; Described analog module comprises parallel two groups, and first group is the first A/D convertor circuit 1, first impedance commutation circuit 2, first attenuator circuit 3, first amplifying circuit 7 and the first comparer 12 connected successively; Second group is the second A/D convertor circuit 4, second impedance commutation circuit 5, second attenuator circuit 6, second amplifying circuit 8 and the second comparer 13 connected successively; Also be provided with a branch road between described first amplifying circuit 7 and the first comparer 12 and be connected to the second comparer 13; Described digital circuit comprises PXI interface 9, clock circuit 11 and FPGA14; Wherein, PXI interface 9 and clock circuit 11 connect FPGA respectively; First comparer 12 and the second comparer 13 all connect FPGA14.Described FPGA14 is also connected with road GATE gate input channel 15, a GATE gate input channel 15 and connects FPGA14 by Buf.Described PXI interface 9 connects FPGA14 by PXI interface circuit 10.The first described comparer 12 and the second comparer 13 are supper-fast comparer, and the first comparer 12 and the second comparer 13 are also connected to ERIGCONTROL circuit.Described clock circuit 11 is TCXO clock circuit, and described PXI interface circuit 10 is PCI9054.

Analog module is by switching to input signal through AD conversion, 50 Ω/1M Ω impedances, decay, amplify thus make input signal meet the input voltage range of comparer.Signal after conditioning is input to comparer, and input signal is converted to digital signal and transfers to FPGA by comparator circuit.On comparer is selected, in order to improve the antijamming capability of comparer, effectively eliminate the error brought because of signal jitter, the utility model adopts the supper-fast comparer with lag function.

In digital circuit, PXI interface 9 completes the steering logic of PXI bus; TCXO clock circuit produces the clock signal of high stability; FPGA14 is the implementation center of digital circuit, completes PXI bus to the combination between each functional module, each functional module and time series stereodata and measurement function.

Power supply of the present utility model is provided by PXI interface 9, and supply voltage needed for digital circuit blocks is that+3.3V and+1.2V ,+3.3V voltage connects 9 mouthfuls by PXI and directly provides, and+1.2V voltage to be changed through LDO by+3.3V and realized; Mimic channel supply voltage is ± 5V, and+5V the voltage provided by PXI interface 9 realizes through power conversion chip conversion.

FPGA14 internal main will be divided into clock-reset control module, TRIGDA control module, HYSTDA control module, RELAY control module, LocalBus control module, EEPROM control module, COUNTER control module, route and other control module.FPGA14 each control module function is as follows: clock-reset control module produces clock, the reset signal of whole system, and manages it; TRIGDA control module arranges input signal triggering level by SPI Interface Controller DA output voltage; HYSTDA control module arranges the sluggish level of input signal by SPI Interface Controller DA output voltage; RELAY control module is carried out pilot relay by SPI Interface Controller relay driving chip and is switched; The realization of LocalBus control module LocalBus control module is mutual with processor, realizes the control to each function sub-modules; EEPROM control module stored waveform exports calibration data adjustment waveform parameter; COUNTER control module realizes the measurement functions such as frequency, cycle, the time interval, pulse width; Route and other control module arrange selection trigger source according to register, counting clock source, and GATE source also can arrange route output.

Claims (5)

1., based on a timer conter for PXI bus, comprise analog module and digital circuit blocks; It is characterized in that:

Described analog module comprises parallel two groups, and first group is the first A/D convertor circuit (1), the first impedance commutation circuit (2), the first attenuator circuit (3), the first amplifying circuit (7) and the first comparer (12) that connect successively; Second group is the second A/D convertor circuit (4), the second impedance commutation circuit (5), the second attenuator circuit (6), the second amplifying circuit (8) and the second comparer (13) that connect successively; Also be provided with a branch road between described first amplifying circuit (7) and the first comparer (12) and be connected to the second comparer (13);

Described digital circuit comprises PXI interface (9), clock circuit (11) and FPGA(14); Wherein, PXI interface (9) and clock circuit (11) connect FPGA respectively;

First comparer (12) and the second comparer (13) all connect FPGA(14).

2. a kind of timer conter based on PXI bus according to claim 1, is characterized in that: described FPGA(14) be also connected with road GATE gate input channel (15).

3. a kind of timer conter based on PXI bus according to claim 1, is characterized in that: described PXI interface (9) connects FPGA(14 by PXI interface circuit (10)).

4. a kind of timer conter based on PXI bus according to claim 1, is characterized in that: described the first comparer (12) and the second comparer (13) are supper-fast comparer.

5. a kind of timer conter based on PXI bus according to claim 1, is characterized in that: described clock circuit (11) is TCXO clock circuit.