CN202614836U - Wide voltage data acquisition device - Google Patents
Wide voltage data acquisition device Download PDFInfo
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- CN202614836U CN202614836U CN 201220108793 CN201220108793U CN202614836U CN 202614836 U CN202614836 U CN 202614836U CN 201220108793 CN201220108793 CN 201220108793 CN 201220108793 U CN201220108793 U CN 201220108793U CN 202614836 U CN202614836 U CN 202614836U
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Abstract
The utility model discloses a wide voltage data acquisition device. A gear selecting signal of a knob gear-selecting circuit is isolated by a photoelectric isolation circuit and then output to a CPLD control unit. The signal is then sent to a multi-path selector gear-selecting circuit through a digital isolator to achieve control on a channel. An analog voltage signal acquired externally is attenuated through a matched resistance input circuit and then sent to a channel selected by a multi-path selector through a clamping protective circuit. An output signal is sent to an operational amplifier of an amplifying buffer circuit and then sent to an analog/digital conversion circuit for data conversion while being protected by the clamping protective circuit. The converted digital signal is sent to the CPLD control unit through a digital isolation circuit for making data stored in a buffer memory and outputting a final measuring result. The wide voltage data acquisition device provided in the utility model can perform high-speed data acquisition on analog voltage signals within a range between minus 600 volts and 600 volts. The anti-interference capabilities of the whole device are significantly improved.
Description
Technical field
The utility model relates to a kind of wide voltage data harvester of high-speed isolated.
Background technology
In commercial production control field; Often need gather many-sided data as much as possible; And with data realization high speed, isolation and the conversion accurately of gathering, particularly in the demanding image processing system of data acquisition scope, speed and interference free performance, TT&C system.At present; On the market the input voltage range of general data acquisition equipment be tens volts even a few volt basically; Antijamming capability is not ideal enough; And mostly adopt be single-chip microcomputer or digital signal processor (DSP:Digital Signal Processor) as acp chip, the acquisition rate of system is lower, antijamming capability is relatively poor relatively, be difficult to the stability and the reliability of assurance system.Along with the progress of electronic technology, the scheme that adopts high-speed figure to isolate can solve the problem of interference well, and widening of input voltage range also will certainly make this harvester be applied to more areas.And aspect HSDA; CPLD (CPLD:Complex Programable Logic Device) has single-chip microcomputer and the incomparable advantage of DSP, can a large amount of logic functions be integrated in the monolithic integrated optical circuit, has the clock frequency height; Internal delay time is little; Characteristics such as speed is fast, and efficient is high, and composition form is flexible.
Summary of the invention
In order to overcome that prior art voltage-measurable scope is little, acquisition rate is low and deficiency such as poor anti jamming capability; The utility model provides a kind of wide voltage data harvester based on CPLD, can right-600V～+ analog voltage signal of 600V carries out data acquisition at a high speed.These device many places utilize isolating device, signal is isolated, thereby improved the antijamming capability of whole device greatly.
The utility model solves the technical scheme that its technical matters adopted: comprise build-out resistor input circuit, clamped holding circuit, MUX block selecting circuit, amplify buffer circuit, mould/number conversion circuit, digital buffer circuit, CPLD control module, photoelectric isolating circuit and knob block selecting circuit.The selected signal of the gear of said knob block selecting circuit outputs to the CPLD control module after isolating through photoelectric isolating circuit; Become MUX block selecting circuit control signal, deliver to MUX block selecting circuit through digital isolator again and realize control passage; The outside analog voltage signal of gathering carries out the decay of signal through the build-out resistor input circuit; Simulating signal after the decay is sent signal into the passage that MUX has been chosen through clamped holding circuit, and the output signal is delivered to the operational amplifier end of oppisite phase that amplifies buffer circuit.Through the feedback resistance of operational amplifier, different attenuation ratios is provided simultaneously, promptly the coupling of different feedback resistances is divided collectable input signal for some gears, thus realize outside can gather wide to-600V～+ function of the simulating signal of 600V.The reference voltage of mould/number conversion inside circuit 2V is through the resistors match of voltage follower and the forward end that power ascension is input to operational amplifier; Make the bipolar voltage conversion of signals become unipolarity; This signal is sent into the input end of analog signal of mould/number conversion circuit through the protection of clamped holding circuit, mould/number conversion circuit CPLD send into clock trigger under the realization data-switching.Digital signal after the conversion is delivered to the buffer memory that the CPLD control module carries out data through digital buffer circuit, and the output final measurement.
The external knob end Range1-Range4 of said knob block selecting circuit is respectively by the resistance of two 500 Ω and be connected to ground; Guarantee initially to be not selected state; Range1-Range4 connects the resistance of two 500 Ω of parallel connection; Be connected respectively to 2,4,6,8 pins of optocoupler isolator again, 2,4,6,8 pins respectively and utilize diode connected in parallel, electric capacity and resistive element circuit to disappear between power supply and tremble.
The build-out resistor value of said feedback resistance is respectively 100k, 20k, 4k, 1k, and precision is 1%.
The beneficial effect of the utility model is: the utility model from outside collection-600V～+ simulating signal in the 600V scope; Utilize knob, optocoupler isolator spare to design block selecting circuit cleverly, realize the electrical isolation between external knob block selecting circuit and CPLD control circuit and eliminated noise.The output signal of optocoupler isolator produces the control signal of MUX gear gating through the CPLD control module.The signal of gathering is sent into selected gear passage and is sent into the conditioning of carrying out signal in the accurate amplifier again so that it satisfies 0V～2V voltage signal that mould/sampling of number converter is allowed after overdamping; But the logic device (CPLD) that utilizes flexible programming is simply presorted frequency division and is gone out time clock to trigger the A/D conversion, and CPLD handles and buffer memory with real-time the sending into of digital signal after the conversion.
The characteristics of the utility model are: (1) the utility model is kernel processor chip with CPLD, and advantages such as its integrated level is high, volume is little, low in energy consumption, flexible design make this device have good dirigibility, adaptability and reliability.(2) can gather-600v is to the analog voltage signal of+600v relative broad range, remedied general harvester and gathered the narrow and limited shortcoming of voltage range, makes it can be applied to more areas.The utility model is divided into four gears to input signal, when measuring small-signal, can use-6V～+ the 6V gear, use-600V when measuring large-signal～+ 600V, this mode can improve the precision of measurement greatly; (3) isolating device has been adopted in many places; Numeral when carrying out data and clock transfer between photoelectricity coupling isolation, mould/number converter and the CPLD when knob block selecting is arranged is isolated; The use of these buffer circuits can not only be eliminated noise effectively; Reduce and disturb, can also protect device (or people) to avoid high-tension harm; (4) clamped holding circuit is adopted in many places, like the AFE(analog front end) voltage attenuation of MUX block selecting circuit, the clamped protection of amplification buffer circuit output voltage and the input end of entering analog to digital conversion circuit etc., has prevented that static discharge and surge from damaging other device; (5) adopted accurate operational amplifier (ADA4851), the 0.1dB flatness of its outstanding differential gain (0.08%) and differential phase (0.09 °) and 11MHz, 130MHz-three dB bandwidth and high pressure swing rate can change the data of gathering more accurately; (6) the chip cost performance that adopts is all very high, thereby makes whole device satisfying under the prerequisite of performance, has practiced thrift cost greatly.
Description of drawings
Fig. 1 is the structural representation of the said wide voltage data harvester of the utility model.
Among the figure, 1 build-out resistor input circuit; 2 clamped holding circuits; 3 MUX block selecting circuit; 4 amplify buffer circuit; 5 moulds/number conversion circuit; 6 digital buffer circuits; The 7CPLD control module; 8 photoelectric isolating circuits; 9 knob block selecting circuit.
Embodiment
The utility model comprises build-out resistor input circuit, clamped holding circuit, MUX block selecting circuit, amplifies buffer circuit, mould/number conversion circuit, digital buffer circuit, CPLD control module, photoelectric isolating circuit and knob block selecting circuit.The utility model adopts cheap knob to carry out gear and selects; External knob end (Range1-Range4) is by the resistance of two 500 Ω and be connected to ground; Guarantee initially to be not selected state; Range1-Range4 connects the resistance of two 500 Ω of parallel connection, is connected respectively to 2,4,6,8 pins of optocoupler isolator again, utilizes diode, electric capacity, resistive element parallel circuit to disappear and tremble between itself and 5V electricity.The selected signal of gear carries out Signal Spacing through optocoupler isolator (PS2801-4); If a certain gear of gating then inner the sending out of optocoupler isolator is managed not conducting of diode; Make its corresponding output end under the effect of pull-up resistor, export high level; If conducting is the output terminal output low level then; Promptly exported 4 binary signal and be input to the CPLD control module and handled, converted control signal S0, the S1 of a certain passage gating of control MUX four-way to, the enable signal EN of these two signals and MUX passes through digital isolator (ADUM1401) again and delivers to the control of MUX block selecting circuit realization to four-way; The outside analog voltage signal of gathering carries out the decay of signal through the build-out resistor input circuit; Simulating signal after the decay is sent signal into the passage that MUX has been chosen through clamped holding circuit, and the output signal is delivered to operational amplifier (AD4851) inverting input (2 pin) that amplifies buffer circuit.Be respectively 100k, 20k, 4k, 1k precision through the build-out resistor value simultaneously and be 1% resistance feedback resistance as operational amplifier; Four tunnel attenuation ratios (1/6,1/30,1/150,1/600) are provided; Be these four kinds of resistance coupling collectable input signal branch for four gears (6V～+ 6V ,-30V～+ 30V ,-150V～+ 150V and-600V～+ 600V), thereby realize outside can gather wide to-600V～+ function of the simulating signal of 600V.Reference voltage by the inner 2V of analog to digital converter (AD9200) output; Carry out the voltage of dividing potential drop generation 1V; Through the resistors match of voltage follower and the forward end (3 pin) that power ascension is input to operational amplifier; Make the bipolar voltage conversion of signals become unipolarity, promptly convert the simulating signal of the acceptable 0V～2V of AD9200 to, this signal is sent into the input end of analog signal of mould/number converter (AD9200) through clamped holding circuit protection; This mould/number converter utilizes the reference voltage of inner 2V; Carry out presorting frequently of clock signal by the CPLD control module, produce mould/needed time clock of number converter and start conversion, the digital signal after will changing is again delivered to processing and the buffer memory that the CPLD control module carries out data through digital buffer circuit.
Below in conjunction with accompanying drawing and embodiment the utility model is further specified.
The utility model comprises build-out resistor input circuit 1, clamped holding circuit 2, MUX block selecting circuit 3, amplification buffer circuit 4, mould/number conversion circuit 5, digital buffer circuit 6, CPLD control module 7, photoelectric isolating circuit 8, knob block selecting circuit 9 compositions.
But the utility model with acquisition range is-600V～+ the analog voltage signal AS of 600V, send into the build-out resistor input circuit 1 of 600K Ω, signal is decayed.
Clamped holding circuit 2, BAV99 forms by catching diode.Voltage signal to after 1 decay of above-mentioned build-out resistor input circuit is realized clamped protection, in case when high pressure occurring with it is clamped within the specific limits (± 5.7V), make peripheral devices avoid high voltage surges impact.The negative terminal input signal of following amplification buffer circuit, and the input end that is input to analog to digital conversion circuit also is provided with clamped holding circuit 2.
MUX block selecting circuit 3; Simulation MUX 74HC4052 by the two-way four-way forms, and it receives control signal S0, the S1 that CPLD control module 7 is sent into, the passage of gating AFE(analog front end) and amp.in when enable signal EN is low level; Be S0, S1 be 00 o'clock gating-6V～+ the 6V gear; 01 o'clock gating-30V～+ the 30V gear, 10 o'clock gating-150V～+ the 150V gear, 11 o'clock gating-600V～+ the 600V gear.Distinguish build-out resistor R1=100K Ω, R2=20K Ω, R3=4K Ω, R4=1K Ω as feedback resistance at the output four-way of MUX and the inverting input of amplifier, make it satisfy the attenuation ratio requirement of four gears respectively, promptly be divided into four gears.Thereby realization-600V～+ aanalogvoltage of 600V scope can gather.
Amplify buffer circuit 4, cooperate above-mentioned MUX block selecting circuit that simulating signal is further nursed one's health.It selects to constitute the numerical value that amplifies feedback resistance in the buffer circuit through the control to MUX, thereby realizes the variation of attenuation ratio.It is divided into 4 kinds of voltage ranges with the simulating signal of outside input, be respectively-6V～+ 6V ,-30V～+ 30V ,-150V～+ 150V and-600V～+ 600V, i.e. four gears described in the utility model.Owing to be still bipolar signal through amplifying the signal that produces behind the buffer circuit; This does not meet the input requirement of A/D converter; Event need be carried out the voltage translation; The utility model adopts the reference voltage with the inner 2V of analog to digital converter to carry out the voltage that dividing potential drop produces 1V, through the resistors match of voltage follower and the forward end that power ascension is input to the anti-phase proportional amplifier.Chip adopts high-precision operational amplifier A DA4851, it be a low cost, at a high speed, rail-to-rail output, twin-channel operational amplifier.Can realize in the high-speed data acquistion system data acquisition performance accurately.
Mould/number conversion circuit 5 receives from the simulating signal of amplifying 0～2V after buffer circuit is handled.The resistance current limliting of one 10 Ω of input signal serial connection, and use clamped holding circuit to surpass the scope of 0～2V to prevent input signal.Analog to digital converter adopts inner 2v reference voltage, sends under the clock triggering at CPLD and realizes data-switching.Sampling precision can reach 10, the nonlinearity erron of maximum 0.5LSB, and switching rate can reach 20MHz.Select AD9200 for use, this A/D chip has reference voltage source able to programme on the sheet, adopts single clock to import the internal conversion cycle of controlling.Have outrange (OTR) marking signal, situation is overflowed in expression.Sample/hold amplifier (SHA) both had been applicable to the multiplex system that in continuous passage, switches the full scale level, also was fit to adopt the highest Nyquist rate and higher frequency that single channel input is sampled.
The output signal OUT_6V that CPLD control module 7 is handled from the photoelectricity coupled circuit, OUT_30V, OUT_150V, OUT_600V four road shift signals are to produce MUX block selecting circuits needed control signal S0, S1 and enable signal EN; CPLD sends the clock signal clk of trigger mode/number conversion, and the digital signal Data that accepts after analog to digital conversion handles and buffer memory, accepts from analog-to-digital outrange marking signal OTR, and handles overflow or underflow situation.The utility model is selected the CPLD chip EPM3256AQC208 of U.S. altera corp for use; This chip is a high-performance, the Low-Power CMOS PLD based on EEPROM; 3.3v supply voltage, 5000 logic gates, 256 macroelements can be provided, the I/O mouth can reach 158; Maximum delay time is 7.5ns; 16 logic array blocks, these advantages make this harvester can expand more peripheral circuit to make it that more strong functions arranged, and have good data processing speed, antijamming capability strong.
Photoelectricity coupling buffer circuit 8 is connected with knob block selecting circuit 9, makes external signal and the complete electrical isolation of CPLD chip, not only reliable protection acp chip but also improve system's antijamming capability greatly.Specifically be that to get to range1 when knob be 6V retaining, getting to range2 is the 30V retaining, and getting to range3 is the 150V retaining, and getting to range4 is the 600V retaining, and each gear all inserts ground by the resistance parallel connection of two 500 Ω, guarantees to be initially not selected state.If selected 6V retaining; Because 1 pin of optically coupled isolator connects the 5v electricity, 2 pin connect 500 Ω resistance of two parallel connections by range1, and then the voltage difference of 1 of optically coupled isolator, 2 pins is not enough so that inner photodiode conducting; 16 pins of its output terminal are output as high level under the effect of pull-up resistor; Other not selected gear 4,6,8 pin voltages are 0, thus the reliable conducting of internal body diodes, thus make corresponding 14,12,10 pin all owing to the effect on ground all drags down.If the optocoupler isolator front end is 0111 digital signal when selecting the 6v gear; Then through isolating back output OUT_6V; OUT_30V, OUT_150V, OUT_600V are 1000 digital signal; And send into control signal S0, the S1 that CPLD control module 7 is treated as the selection of MUX block selecting circuit 3 four-ways, be respectively 00,01,10,11.
Can realize the wide voltage data collection of high-speed isolated through above-mentioned peripheral hardware circuit, gather voltage range can reach-600V～+ 600V.The utility model selects for use CPLD (CPLD) to carry out data processing at a high speed as core devices; Select accurate operational amplifier A DA4851 for use, guarantee the precision of data acquisition; Adopt high-speed AD converter AD9200, carry out high speed, reliable data-switching; Adopt catching diode BAV99 as electrostatic prevention, unrestrained holding circuit of gushing; Adopt high-speed figure isolating device ADUM1401, realize the insulation blocking of digital signal, filtering interfering, protection peripheral components; Utilize knob, optocoupler isolator spare to design block selecting circuit cleverly, realize the electrical isolation between external knob block selecting circuit and CPLD control circuit and eliminated noise.Characteristics such as the utlity model has that voltage-measurable wide ranges, acquisition rate are high, precision is high, antijamming capability is strong and cost is low can be applied to more areas.
Claims (3)
1. one kind wide voltage data harvester; Comprise build-out resistor input circuit, clamped holding circuit, MUX block selecting circuit, amplify buffer circuit, mould/number conversion circuit, digital buffer circuit, CPLD control module, photoelectric isolating circuit and knob block selecting circuit; It is characterized in that: the selected signal of the gear of said knob block selecting circuit outputs to the CPLD control module after isolating through photoelectric isolating circuit; Become MUX block selecting circuit control signal, deliver to MUX block selecting circuit through digital isolator again and realize control passage; The outside analog voltage signal of gathering carries out the decay of signal through the build-out resistor input circuit; Simulating signal after the decay is sent signal into the passage that MUX has been chosen through clamped holding circuit; The output signal is delivered to the operational amplifier end of oppisite phase that amplifies buffer circuit; Different feedback resistances through operational amplifier divide the input signal of gathering for some gears simultaneously; The reference voltage of mould/number conversion inside circuit 2V is through the resistors match of voltage follower and the forward end that power ascension is input to operational amplifier; Make the bipolar voltage conversion of signals become unipolarity, this signal is sent into the input end of analog signal of mould/number conversion circuit through the protection of clamped holding circuit, mould/number conversion circuit CPLD send into clock trigger under the realization data-switching; Digital signal after the conversion is delivered to the buffer memory that the CPLD control module carries out data through digital buffer circuit, and the output final measurement.
2. wide voltage data harvester according to claim 1; It is characterized in that: the external knob end Range1-Range4 of described knob block selecting circuit is respectively by the resistance of two 500 Ω and be connected to ground; Guarantee initially to be not selected state; Range1-Range4 connects the resistance of two 500 Ω of parallel connection; Be connected respectively to 2,4,6,8 pins of optocoupler isolator again, 2,4,6,8 pins respectively and utilize diode connected in parallel, electric capacity and resistive element circuit to disappear between power supply and tremble.
3. wide voltage data harvester according to claim 1 is characterized in that: the build-out resistor value of described feedback resistance is respectively 100k, 20k, 4k, 1k, and precision is 1%.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220108793 CN202614836U (en) | 2012-03-21 | 2012-03-21 | Wide voltage data acquisition device |
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| CN 201220108793 CN202614836U (en) | 2012-03-21 | 2012-03-21 | Wide voltage data acquisition device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102590604A (en) * | 2012-03-21 | 2012-07-18 | 西北工业大学 | Wide voltage data collection device based on complex programmable logic device (CPLD) |
| CN104678861A (en) * | 2015-02-26 | 2015-06-03 | 邓珊珊 | Circuit with adjustable threshold voltage for collecting digital signals |
| CN105242106A (en) * | 2015-11-04 | 2016-01-13 | 武汉精测电子技术股份有限公司 | Device and method for sampling and detecting multiple paths of voltages |
| CN111490772A (en) * | 2020-04-27 | 2020-08-04 | 云南拓普特种电源科技有限公司 | High-speed isolated acquisition and restoration system and time sequence control method |
-
2012
- 2012-03-21 CN CN 201220108793 patent/CN202614836U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102590604A (en) * | 2012-03-21 | 2012-07-18 | 西北工业大学 | Wide voltage data collection device based on complex programmable logic device (CPLD) |
| CN104678861A (en) * | 2015-02-26 | 2015-06-03 | 邓珊珊 | Circuit with adjustable threshold voltage for collecting digital signals |
| CN105242106A (en) * | 2015-11-04 | 2016-01-13 | 武汉精测电子技术股份有限公司 | Device and method for sampling and detecting multiple paths of voltages |
| CN105242106B (en) * | 2015-11-04 | 2019-04-30 | 武汉精测电子集团股份有限公司 | The device and method that plurality of voltages can be sampled and detected |
| CN111490772A (en) * | 2020-04-27 | 2020-08-04 | 云南拓普特种电源科技有限公司 | High-speed isolated acquisition and restoration system and time sequence control method |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121219 Termination date: 20150321 |
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| EXPY | Termination of patent right or utility model |