CN210572277U

CN210572277U - Chip with water quality detection interface

Info

Publication number: CN210572277U
Application number: CN201921319293.4U
Authority: CN
Inventors: 李智强
Original assignee: Shenzhen Yimu Technology Co ltd
Current assignee: Shenzhen Yimu Technology Co ltd
Priority date: 2019-08-15
Filing date: 2019-08-15
Publication date: 2020-05-19
Anticipated expiration: 2029-08-15

Abstract

The utility model provides a chip with water quality testing interface, includes simulation front end portion and main control unit portion, the simulation front end portion is including data acquisition interface, signal processing and sampling circuit, control logic circuit, clock circuit and the power that corresponds different water quality testing data input, data acquisition interface connection signal processing and sampling circuit's input, signal processing and sampling circuit's output transmits to main control unit portion through control logic circuit, and clock circuit is used for providing clock signal for signal processing and sampling circuit and control logic circuit. The utility model provides a multiple input interface who detects data concentrates them and gathers, is favorable to realizing fast the comprehensive detection to quality of water, and data is high at the transmission course accuracy, and chip packaging structure has realized small-size and low-power consumption, especially can satisfy the demand that domestic water quality testing equipment is miniaturized, low energy consumption.

Description

Chip with water quality detection interface

Technical Field

The utility model belongs to the technical field of electronic circuit, relate to water quality testing, specifically be a chip with water quality testing interface.

Background

Along with the development of economy, population increases, and city drinking water source pollutes seriously, and resident's life drinking water safety receives the threat, and people more and more pay more attention to drinking water quality.

Current water filtration equipment is mostly to keep the water purification effect through the mode of renew cartridge, and renew cartridge when, or how does not have corresponding special device at present drainage quality. Although a plurality of water quality detection devices are provided, most of the detection devices are independent, the detection results are difficult to be centrally and uniformly managed, the use is inconvenient, and the water quality cannot be rapidly and visually displayed.

Disclosure of Invention

The utility model discloses the problem that solves is: the water quality detection equipment is numerous, and detection data of various water quality detection equipment can be concentrated by the equipment, and the accuracy of the data is ensured.

The technical scheme of the utility model is that: the utility model provides a chip with water quality testing interface, the circuit of encapsulation in the chip includes simulation front end portion and main control unit portion, the simulation front end portion is including data acquisition interface, signal processing and sampling circuit, control logic circuit, clock circuit and the power that corresponds different water quality testing data input, data acquisition interface connection signal processing and sampling circuit's input, signal processing and sampling circuit's output transmit to main control unit portion through control logic circuit, and clock circuit is used for providing clock signal for signal processing and sampling circuit and control logic circuit.

Furthermore, the data acquisition interface is provided with a plurality of acquisition channels, the output of each channel is provided with a follower circuit, and the plurality of acquisition channels are connected to the signal processing and sampling circuit through a plurality of selectors with corresponding channel numbers.

Further, the data acquisition interface comprises a total dissolved solids TDS water quality test data acquisition interface, a residual chlorine data acquisition interface, a hardness data acquisition interface, a PH value data acquisition interface, a water temperature data acquisition interface and a liquid level data acquisition interface.

As a preferred mode, the signal processing and sampling circuit comprises a power frequency fundamental wave trap, a first follower, a power frequency first harmonic wave trap, a second follower, a programmable gain amplifier, a low-pass filter and an ADC (analog to digital converter) sampling circuit which are sequentially connected, the output of the ADC sampling circuit is sent to the control logic circuit, the programmable gain amplifier is used for adjusting the input of the ADC sampling circuit to be the reference voltage of the ADC sampling circuit, and the low-pass filter is used as an anti-aliasing filter.

Preferably, the first follower and the second follower are voltage followers.

Preferably, the control logic circuit and the main controller part are connected through an SPI interface or an 8080 parallel interface.

Preferably, the main controller part is a 32-bit MCU and a peripheral circuit thereof, the peripheral circuit comprises a clock circuit, a reset circuit, a storage circuit, a first peripheral bus, a second peripheral bus and a power supply, wherein the first peripheral bus is used for connecting the MCU with chip peripherals and comprises a GPIO (general purpose input/output), an SPI (universal asynchronous receiver/transmitter), a TIM (time value indicator), a watchdog, a DMA (direct memory access) and an ADC (analog to digital converter), and the second peripheral bus is used for being connected with a control logic circuit of the analog front end part.

As a preferred mode, an independent on-chip temperature sensor detection channel is also opened for the ADC on the first peripheral bus, and is used for detecting the chip temperature in real time, so as to ensure normal operation of the chip.

The utility model provides a chip with a water quality detection interface, which provides an input interface for a plurality of detection data, and after the detection data are collected and preprocessed, the detection data are input into a main controller part for centralized collection, thereby being beneficial to quickly realizing the comprehensive detection of water quality, and the accuracy of the data in the transmission process is considered by the design of a chip circuit; the utility model discloses a chip package has realized small-size and low-power consumption on circuit design, especially can satisfy the demand of domestic water quality testing equipment miniaturization, low energy consumption.

Drawings

Fig. 1 is a schematic diagram of the chip structure of the present invention.

Fig. 2 is a schematic circuit diagram of the analog front end of the chip of the present invention.

Fig. 3 is a schematic circuit diagram of the main controller of the chip of the present invention.

Detailed Description

The utility model provides a chip with water quality testing interface realizes a special chip, and the concrete description is as follows.

As shown in figure 1, the utility model discloses chip package circuit includes tip and main control unit portion before the simulation, tip is including data acquisition interface, signal processing and sampling circuit, control logic circuit, clock circuit and the power that corresponds different water quality testing data input before the simulation, data acquisition interface connection signal processing and sampling circuit's input, signal processing and sampling circuit's output transmit to main control unit portion through control logic circuit, and clock circuit is used for providing clock signal for signal processing and sampling circuit and control logic circuit, and the power is used for the power supply.

As shown in fig. 2, the analog front end of the present invention is specifically explained. The utility model provides a current water quality testing equipment is various, the utility model discloses the chip provides special acquisition circuit, the data acquisition interface has the multichannel collection passageway, the multichannel collection passageway is connected to signal processing and sampling circuit through the multiplexer that corresponds the channel number, realize the timesharing multiplexing technique through the multiplexer, the multiplexer has low on resistance and higher isolation, the data acquisition interface is at least including total dissolved solid TDS water quality testing data acquisition interface, chlorine residue data acquisition interface, hardness data acquisition interface, PH value data acquisition interface, temperature data acquisition interface and liquid level data acquisition interface etc.. The utility model discloses a under the structure, corresponding to different data signal sources, the user can dispose the chip through main control unit portion by oneself when implementing, and each passageway all can be disposed into one of these three kinds of modes of voltage amplifier, charge amplifier or current amplifier by main control unit portion through control logic circuit, and each route output is followed the output by the follower in order to keep apart the internal circuit in addition.

The signal processing and sampling circuit comprises a power frequency fundamental wave trap, a first follower, a power frequency first harmonic wave trap, a second follower, a controllable gain amplifier, a low-pass filter and an ADC (analog to digital converter) sampling circuit which are sequentially connected, and the output of the ADC sampling circuit is sent to the control logic circuit. The power frequency fundamental wave trap is used for inhibiting power frequency fundamental wave interference in signals. The power frequency first harmonic wave trap is used for inhibiting power frequency first harmonic waves so as to further improve the signal quality; also for the purpose of isolating the front and rear stages, voltage followers, i.e., first and second followers, which are essentially a one-time amplification in-phase amplifier having a high input resistance and a low output resistance, are inserted in the circuit to increase the driving capability.

In order to furthest's the word number that utilizes the ADC, the input value that requires the ADC is close to the full scale voltage of ADC as far as possible, generally is ADC's reference voltage, in order to realize this point, the utility model discloses added a programme-controlled gain amplifier, when the signal is low excessively, suitably increase the magnification to improve input voltage, variable gain amplifier's addition has not only increased ADC's precision, has also improved the detection range that this chip can be suitable for.

The utility model discloses added a low pass filter LPF as anti-aliasing filter for further improving signal quality before ADC sampling circuit, also can further reduce power frequency interference simultaneously, this wave filter adopts active filter technique, can be better satisfy the requirement.

The control logic circuit is used for realizing parameter configuration when the chip is used, and comprises acquisition channel configuration of a data acquisition interface, notch frequency configuration, gain configuration and the like in the signal processing and sampling circuit, and transmission of acquired data, and is realized by the control logic, and the control logic circuit realizes an SPI interface and an 8080 parallel port and is used for transmitting an analog front end command and data to the main controller part.

As shown in fig. 3, the main controller is a 32-bit MCU and its peripheral circuits, the peripheral circuits include a clock circuit, a reset circuit, a memory circuit, a first peripheral bus, a second peripheral bus and a power supply, wherein the first peripheral bus is an APB bus for the MCU to connect to the chip peripherals, including GPIO, SPI, UART, TIM, watchdog, DMA and ADC, the second peripheral bus is used to connect to the control logic circuit of the front end of the analog device, the second peripheral bus is equivalent to a bus switch, through which the main controller can communicate with the front end of the analog device in the form of SPI or 8080 parallel port. As an embodiment, the clock circuit is a PLL clock source with a high-stability crystal oscillator and a clock frequency divider, the storage circuit is a maximum 256K flash on a chip and a maximum 64KRAM, the power supply is a 3.3V digital and analog power supply and a 2.5V voltage reference. In addition, as a preferred mode, an independent on-chip temperature sensor detection channel is opened for the ADC on the first peripheral bus, and the on-chip temperature sensor detection channel can be used for detecting the temperature of a chip in real time and ensuring the normal work of the chip.

The above description is only a preferred embodiment of the present invention, and it should be noted that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A chip with a water quality detection interface is characterized in that a circuit packaged in the chip comprises a simulation front end portion and a main controller portion, the simulation front end portion comprises a data acquisition interface, a signal processing and sampling circuit, a control logic circuit, a clock circuit and a power supply, the data acquisition interface is connected with the input of the signal processing and sampling circuit, the output of the signal processing and sampling circuit is transmitted to the main controller portion through the control logic circuit, and the clock circuit is used for providing clock signals for the signal processing and sampling circuit and the control logic circuit.

2. The chip with the water quality detection interface as recited in claim 1, wherein the data acquisition interface has multiple acquisition channels, the output of each channel is provided with a follower circuit, and the multiple acquisition channels are connected to the signal processing and sampling circuit through a multiplexer with a corresponding number of channels.

3. The chip with the water quality detecting interface as recited in claim 1, wherein the data collecting interface comprises a Total Dissolved Solids (TDS) water quality testing data collecting interface, a residual chlorine data collecting interface, a hardness data collecting interface, a pH data collecting interface, a water temperature data collecting interface and a liquid level data collecting interface.

4. The chip with the water quality detection interface according to claim 1, wherein the signal processing and sampling circuit comprises a power frequency fundamental wave trap, a first follower, a power frequency first harmonic wave trap, a second follower, a programmable gain amplifier, a low pass filter and an ADC sampling circuit which are connected in sequence, the output of the ADC sampling circuit is sent to the control logic circuit, the programmable gain amplifier is used for adjusting the input of the ADC sampling circuit to be the reference voltage of the ADC sampling circuit, and the low pass filter is used as an anti-aliasing filter.

5. The chip with the water quality detecting interface as recited in claim 4, wherein the first follower and the second follower are voltage followers.

6. The chip with the water quality detection interface as claimed in claim 1, wherein the control logic circuit is connected with the main controller portion through an SPI interface or an 8080 parallel port.

7. The chip with the water quality detection interface according to claim 1, wherein the main controller part is a 32-bit MCU and peripheral circuits thereof, the peripheral circuits comprise a clock circuit, a reset circuit, a storage circuit, a first peripheral bus, a second peripheral bus and a power supply, wherein the first peripheral bus is used for connecting the MCU with the chip peripherals and comprises GPIO, SPI, UART, TIM, watchdog, DMA and ADC, and the second peripheral bus is used for being connected with a control logic circuit of the analog front end part.

8. The chip with the water quality detection interface as recited in claim 7, wherein an independent on-chip temperature sensor detection channel is further opened for the ADC on the first peripheral bus for detecting the chip temperature in real time to ensure the normal operation of the chip.