CN214476382U - Voice detection and recognition device - Google Patents

Abstract

The embodiment of the utility model discloses sound detection recognition device, sound detection recognition device includes sound acquisition unit, signal identification unit, first interface unit and second interface unit. The sound acquisition unit is used for acquiring sound signals and performing analog-to-digital conversion on the sound signals to obtain pulse density modulation signals; the signal identification unit is connected with the sound acquisition unit and is used for identifying the pulse code modulation signal to acquire sound information after converting the pulse density modulation signal into a pulse code modulation signal. The utility model provides a sound detection recognition device does not need solitary special audio ADC chip, has realized the detection discernment to sound through ordinary sound collection unit and general signal identification unit, has simplified the circuit, has reduced the sound detection recognition device volume, has reduced the cost of sound detection recognition device.

Description

Voice detection and recognition device

Technical Field

The utility model relates to a voice recognition technical field especially relates to a voice detection recognition device.

Background

The special voice detection and identification device is mainly used for detecting and identifying some special voice signals with certain characteristics. Such as a person's cough, snoring, baby crying, etc.

The human body itself and many diseases produce a wide variety of sounds. Common audio events associated with the respiratory system of a patient, such as respiratory ailments, are coughing, snoring, wheezing, breathing, and the like. It is important to monitor the status of a patient using a voice detection and identification device and to trigger an alarm to alert a nurse or family member when a particular audio event occurs. For another example, heart sound signals are important physiological signals in the human body which can reflect the operation conditions of the heart and the cardiovascular system. The heart sound signal is detected, identified and analyzed, early warning and early diagnosis of various heart diseases can be realized, and problems can be timely and effectively treated.

The voice detection and recognition technology is used for auxiliary diagnosis and treatment, the burden of doctors can be partially relieved, the benefit of patients can be brought, and the voice detection and recognition technology is an important application in the field of intelligent medical treatment.

The voice detection and recognition device in the prior art generally needs a special audio ADC chip and a special voice processing chip to complete voice recognition, and the cost is high.

Disclosure of Invention

In view of the above, it is necessary to provide a voice detection and recognition device.

The utility model discloses a technical means do: provided is a voice detection and recognition device including:

the sound acquisition unit is used for acquiring sound signals and performing analog-to-digital conversion on the sound signals to obtain pulse density modulation signals;

the signal identification unit is connected with the sound acquisition unit and is used for identifying the pulse code modulation signal to acquire sound information after converting the pulse density modulation signal into a pulse code modulation signal;

the first interface unit is connected with an external power supply device and used for supplying power to the voice detection and identification device by using a power supply of the external power supply device; and

and the second interface unit is connected with the signal identification unit and used for sending the sound information to external equipment.

Since the technical scheme is used, the utility model provides a sound detection recognition device, sound detection recognition device includes sound collection unit, signal identification unit, first interface unit and second interface unit. The sound acquisition unit is used for acquiring sound signals and performing analog-to-digital conversion on the sound signals to obtain pulse density modulation signals; the signal identification unit is connected with the sound acquisition unit and is used for identifying the pulse code modulation signal to acquire sound information after converting the pulse density modulation signal into a pulse code modulation signal. The utility model provides a sound detection recognition device does not need solitary special audio ADC chip, has realized the detection discernment to sound through ordinary sound collection unit and general signal identification unit, has simplified the circuit, has reduced the sound detection recognition device volume, has reduced the cost of sound detection recognition device.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Wherein:

FIG. 1 is a schematic diagram of an embodiment of a voice detection and recognition apparatus;

FIG. 2 is a schematic circuit diagram of a sound collection unit in one embodiment;

FIG. 3 is a schematic circuit diagram of a voice recognition unit in one embodiment;

fig. 4 is a circuit schematic of a first interface unit and a second interface unit in one embodiment.

In the figure: 100. a voice detection and recognition device; 200. an external power supply device; 300. an external device; 10. a sound collection unit; 20. a signal identification unit; 30. a first interface unit; 40. a second interface unit.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The terms first, second and the like in the description and in the claims, and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be practiced otherwise than as specifically illustrated.

The embodiment of the present invention provides a sound detection and recognition apparatus 100, in one embodiment, as shown in fig. 1, the sound detection and recognition apparatus 100 may include a sound collection unit 10, a signal recognition unit 20, a first interface unit 30 and a second interface unit 40. The sound collection unit 10 may be configured to collect a sound signal, and perform analog-to-digital conversion on the sound signal to obtain a Pulse Density Modulation (PDM) signal; the signal recognition unit 20 may be connected to the sound collection unit 10, and configured to convert the Pulse Density Modulation (Pulse Density Modulation) signal into a Pulse Code Modulation (Pulse Code Modulation) signal, which is referred to as a PCM signal for short, and recognize the Pulse Code Modulation (Pulse Code Modulation) signal to obtain sound information; the first interface unit 30 may be connected to an external power supply device 200, and is configured to supply power to the voice detection and recognition device 100 by using a power supply of the external power supply device 200; the second interface unit 40 may be connected to the signal recognition unit 20, and configured to transmit the sound information to an external device 300. The first interface unit 30 and the second interface unit 40 may share one interface terminal, or may respectively use different interface terminals, which is not particularly limited in this application.

The signal identification unit 20 may adopt a general MCU, which may be a single chip microcomputer, a DSP, an FPGA, or the like, and certainly, the signal identification unit 20 may also adopt other signal identification modules with equivalent functions, which is not particularly limited in this application.

The voice detection and identification device provided by the embodiment does not need an independent special audio ADC chip, realizes voice detection and identification through a common voice acquisition unit and a universal signal identification unit, simplifies a circuit, reduces the volume of the voice detection and identification device, and reduces the cost of the voice detection and identification device.

In one embodiment, as shown in fig. 2, the sound collection unit 10 may include a digital microphone chip U1, a first resistor R12, and a first capacitor C4. The first interface unit 30 has a positive output terminal VDD +3.3V and a negative output terminal GND. A working voltage VDD pin of the digital microphone chip U1 is connected with the positive output end VDD +3.3V, and is connected with the negative output end GND through the first capacitor C4; a grounding GND pin of the digital microphone chip U1 is connected with the negative output end GND; a left and right channel selection R/L pin of the digital microphone chip U1 is connected with the negative output end GND through the first resistor R12 to select a left channel; a pin of a synchronous input clock SCLK of the digital microphone chip U1 is connected to the signal identification unit 20, and is configured to receive a square wave clock signal within a certain frequency range; the serial audio data output SDATA pin of the digital microphone chip U1 is connected to the signal identification unit 20, and is configured to output the pulse density modulation signal to the signal identification unit 20.

In one embodiment, as shown in fig. 2, the digital microphone chip U1 may employ MP34DT 01. MP34DT01 is a single power supply, low power, omnidirectional, PDM output digital microphone chip from ST corporation.

Further, as shown in fig. 2 and 3, a first pin, namely VDD, of the digital microphone chip U1 is a working voltage of the U1 chip, is connected to the positive output terminal VDD +3.3V, and is connected to the negative output terminal GND through the first capacitor C4, and the first capacitor C4 is a patch capacitor and plays a role in energy storage and filtering. A fifth pin of the digital microphone chip U1 is connected with the negative output end GND; a second pin R/L of the digital microphone chip U1 is used for left and right channel selection, the negative output end GND is connected through the first resistor R12, and the second pin of the digital microphone chip U1 is set to be low level through the first resistor R12 to select the left channel; a third pin, namely SCLK, of the digital microphone chip U1 is a synchronous input clock and is connected to a thirty-fourth pin I2S2_ CK of the singlechip U2; the fourth pin SDATA of the digital microphone chip U1 is PDM data output and is connected to the thirty-sixth pin I2S2_ SD of the single chip U2.

The working principle of sound collection is as follows: as shown in fig. 2 and 3, when the sound detection and recognition apparatus 100 is powered on, the thirty-fourth pin I2S2_ CK of the single chip microcomputer U2 outputs a square wave clock signal in the range of 1MHz to 3.25MHz to the third pin SCLK of the digital microphone chip U1, an ADC (analog-to-digital converter) is integrated in the digital microphone chip U1, the acquired sound signal can be converted into a digital signal, the digital signal is output from the fourth pin SDATA of the digital microphone chip U1 in the form of a PDM signal, and the data of the left channel is effectively output during the low level period of each SCLK, the thirty-sixth pin I2S2_ SD of the single chip microcomputer U2 is connected to the fourth pin SDATA of the digital microphone chip U1, and the digital sound signal in the form is received from the fourth pin SDATA, thereby completing the acquisition of the sound signal.

In an embodiment, as shown in fig. 3, the signal identification unit may adopt a general MCU, for example, a single chip microcomputer, a DSP, an FPGA, or the like, and of course, the signal identification unit 20 may also adopt other signal identification modules with equivalent functions, which is not limited in this application.

In an embodiment, the signal identification unit in this embodiment employs a single chip microcomputer, as shown in fig. 3, the signal identification unit may include a single chip microcomputer U2; the single chip microcomputer U2 is connected with the sound acquisition unit 10 and the second interface unit 40 through a plurality of I/O interfaces.

In one embodiment, as shown in fig. 3, an on-chip peripheral I2S of the single chip microcomputer U2 is connected to the sound collection unit 10, and is configured to receive the pulse density modulation signal (PDM signal) and send a square wave clock signal with a certain frequency range to the sound collection unit 10.

In one embodiment, as shown in fig. 3, a serial port sending pin and a serial port receiving pin of the single chip microcomputer U2 are respectively connected to the second interface unit 40, and are configured to send the identified sound information to the second interface unit 40.

In one embodiment, as shown in fig. 3, the single-chip microcomputer U2 adopts AT32F403ARCT 6. AT32F403ARCT6 is an M4 kernel 32-bit single chip microcomputer produced by Yateli corporation, the operation speed can reach 240MHz, can support 256KB Flash memory (Flash) and 224KB Static Random Access Memory (SRAM), the excellent performance of zero wait is executed by the Flash memory, surpasses the level of chips AT the same level in the industry, and a built-in single-precision floating point operation unit (FPU) and a Digital Signal Processor (DSP) have very strong digital signal processing capability, are matched with abundant peripheral equipment and a flexible clock control mechanism, and can meet the application in various fields.

Further, as shown in fig. 3, the 6 pins, that is, the 1 st pin, the 13 th pin, the 19 th pin, the 32 th pin, the 48 th pin and the 64 th pin of the single chip microcomputer U2 are connected to the positive output terminal VDD + 3.3V. The 5 pins of the 12 th pin, the 18 th pin, the 31 th pin, the 47 th pin and the 63 rd pin of the singlechip U2 are connected to the negative output end GND. 5 capacitors C6, C9, C12, C13 and C16 play a role in energy storage and filtering, one end of each of the patch capacitors C6, C9, C12, C13 and C16 is connected to the positive output end VDD +3.3V, and the capacitors are respectively distributed to the power supply pins closest to the single chip U2, namely the power supply pins are close to the 64 th pin, the 48 th pin, the 13 th pin, the 19 th pin and the 32 th pin;

further, as shown in fig. 3, Y1 is a patch quartz crystal oscillator, and Y1, C17 and C18 constitute a quartz crystal oscillation circuit, and provide a stable clock source of 8MHz for the single chip microcomputer U2; one end of the Y1 is connected to the 5 th pin of the singlechip U2 and is connected with the negative output end GND through the C17, and the other end of the Y1 is connected to the 6 th pin of the singlechip U2 and is connected with the negative output end GND through the C18.

Further, as shown in fig. 3, a chip resistor R19 and a chip capacitor C10 constitute a power-on reset circuit of the single chip microcomputer U2, one end of the R19 is connected to the positive output terminal VDD +3.3V, and the other end of the R19 is connected to a 7 th pin, i.e., a reset pin, of the single chip microcomputer U2 and is connected to the negative output terminal GND through a C10.

Further, as shown in fig. 3, the connector CN3, the resistor R17, and the resistor R18 constitute a program downloading circuit of the single chip microcomputer U2, and the 1 st pin of the connector CN3 is connected to the positive output terminal VDD + 3.3V; a 2 nd pin of the connector CN3 is connected with a 46 th pin, namely a SWDIO pin, of the singlechip U2, and is connected with the positive output end VDD +3.3V through a resistor R17; the 3 rd pin of the connector CN3 is connected to the negative output terminal GND and connected to the positive output terminal VDD +3.3V through a resistor R18; the 4 th pin of the connector CN3 is connected with the 49 th pin of the singlechip U2, namely the SWCLK pin.

Further, as shown in fig. 3, one end of the resistor R20 is connected to the 28 th pin of the single chip microcomputer U2, and the other end of the resistor R20 is connected to the negative output terminal GND; one end of the resistor R13 is connected with the 60 th pin of the singlechip U2, and the other end of the resistor R13 is connected with the negative output end GND.

The working principle of the voice recognition is as follows: as shown in fig. 2 and 3, when the sound detection and recognition device 100 normally operates, the single chip microcomputer U2 uses its on-chip peripheral I2S interface to receive the PDM signal output by the digital microphone chip U1, the single chip microcomputer U2 receives the sound signal expressed in the form of pulse density, that is, the sound signal has a large amplitude when the pulse density is dense and a small amplitude when the pulse density is sparse, and the single chip microcomputer U2 converts the pulse density modulation signal (PDM signal) into a pulse code modulation signal (PCM signal), that is, into an amplitude value corresponding to the sound signal, and then recognizes the pulse code modulation signal (PCM signal) to obtain sound information.

In one embodiment, as shown in fig. 4, the first interface unit 30 and the second interface unit 40 commonly employ one interface terminal CN 1; the interface terminal CN1 may be used for connecting the external power supply apparatus 200 and the external device 300 for serial communication; the first pin and the fourth pin of the interface terminal CN1 are used as the first interface unit 30; the second pin and the third pin of the interface terminal are used as the second interface unit 40; the first interface unit 30 has a positive output terminal VDD +3.3V and a negative output terminal GND, the first pin is the positive output terminal VDD +3.3V, and the fourth pin is the negative output terminal GND.

In one embodiment, as shown in fig. 4, the first interface unit 30 may further include a second capacitor C1; the second capacitor C1 is a large-capacity patch capacitor, and is used for storing energy and filtering the external power supply device 200; specifically, the first pin of the interface terminal is connected to the negative output terminal GND via the second capacitor C1.

In one embodiment, as shown in fig. 4, the second interface unit 40 may further include a first pull-up resistor R3, a second pull-up resistor R4, a first ESD3 and a second ESD 4; the first pull-up resistor R3 and the second pull-up resistor R4 are chip resistors and are used as pull-up resistors of the communication serial port line of the external device 300. The first ESD3 and the second ESD4 are patch ESD diodes, and are used for ESD protection of the communication serial port of the external device 300.

Specifically, the second pin of the interface terminal CN1 is connected to the positive output terminal VDD +3.3V through the first pull-up resistor R3, and is connected to the cathode of the first ESD protection tube ESD3, and the anode of the first ESD protection tube ESD3 is connected to the negative output terminal GND; the third pin of the interface terminal CN1 is connected to the positive output terminal VDD +3.3V through the second pull-up resistor R4, and is connected to the cathode of the second ESD protection tube ESD4, and the anode of the second ESD protection tube ESD4 is connected to the negative output terminal GND. Further, as shown in fig. 3 and 4, a second pin of the interface terminal CN1 is connected to the serial port transmission line USART1_ TX of the single chip microcomputer U2, and a third pin of the interface terminal CN1 is connected to the serial port reception line USART1_ RX of the single chip microcomputer U2.

In this embodiment, by providing the electrostatic protection diode, when the connection line of the interface terminal CN1 is plugged or pulled, or touched by a human hand, an instantaneous high-voltage electrostatic may be generated on the connection line of the interface terminal CN1 and conducted into the internal circuit of the sound detection and recognition device 100, and if the protection is not performed, the internal components of the sound detection and recognition device 100 are easily damaged. When instant high-voltage static electricity is generated, the electrostatic protection diode is conducted, the high-voltage static electricity is clamped to a very low voltage value by the electrostatic protection diode, and a generated large current flows back to the negative electrode output end GND through the electrostatic protection diode, so that an internal circuit of the sound detection and identification device 100 is protected from being damaged by the high-voltage static electricity.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A voice detection and recognition apparatus, comprising:

the sound acquisition unit is used for acquiring sound signals and performing analog-to-digital conversion on the sound signals to obtain pulse density modulation signals;

the signal identification unit is connected with the sound acquisition unit and is used for identifying the pulse code modulation signal to acquire sound information after converting the pulse density modulation signal into a pulse code modulation signal;

the first interface unit is connected with an external power supply device and used for supplying power to the voice detection and identification device by using a power supply of the external power supply device; and

and the second interface unit is connected with the signal identification unit and used for sending the sound information to external equipment.

2. The sound detection and recognition device according to claim 1, wherein the sound collection unit includes: the microphone comprises a digital microphone chip, a first resistor and a first capacitor;

the first interface unit is provided with a positive electrode output end and a negative electrode output end;

a working voltage pin of the digital microphone chip is connected with the anode output end and is connected with the cathode output end through the first capacitor;

the grounding pin of the digital microphone chip is connected with the negative electrode output end;

a left sound channel and a right sound channel selection pin of the digital microphone chip are connected with the negative output end through the first resistor so as to select a left sound channel;

a synchronous input clock pin of the digital microphone chip is connected with the signal identification unit and is used for receiving a square wave clock signal in a certain frequency range;

and a serial audio data output pin of the digital microphone chip is connected with the signal identification unit and is used for outputting the pulse density modulation signal to the signal identification unit.

3. The sound detection and recognition device according to claim 2,

the digital microphone chip adopts MP34DT 01.

4. The sound detection and recognition device of claim 1, wherein the signal recognition unit comprises a single chip microcomputer;

the single chip microcomputer is connected with the sound acquisition unit and the second interface unit through a plurality of I/O interfaces.

5. The sound detection and recognition device according to claim 4,

and an I2S interface of the on-chip peripheral of the singlechip is connected with the sound acquisition unit and is used for receiving the pulse density modulation signal and sending a square wave clock signal with a certain frequency range to the sound acquisition unit.

6. The sound detection and recognition device according to claim 4,

and the serial port sending pin and the serial port receiving pin of the singlechip are respectively connected with the second interface unit and used for sending the identified sound information to the second interface unit.

7. The sound detection and recognition device according to claim 4,

the single chip microcomputer adopts AT32F403ARCT 6.

8. The sound detection and recognition device according to claim 1,

the first interface unit and the second interface unit commonly adopt an interface terminal;

a first pin and a fourth pin of the interface terminal are used as the first interface unit; the second pin and the third pin of the interface terminal are used as the second interface unit;

the first interface unit is provided with a positive electrode output end and a negative electrode output end, the first pin is used as the positive electrode output end, and the fourth pin is used as the negative electrode output end.

9. The apparatus according to claim 8, wherein the first interface unit further comprises a second capacitor;

and the first pin of the interface terminal is connected with the negative output end through the second capacitor.

10. The apparatus according to claim 8, wherein the second interface unit further comprises: the first pull-up resistor, the second pull-up resistor, the first electrostatic protection diode and the second electrostatic protection diode;

the second pin of the interface terminal is connected with the positive electrode output end through the first pull-up resistor and is connected with the cathode of the first static protection tube, and the anode of the first static protection tube is connected with the negative electrode output end;

the third pin of the interface terminal is connected with the positive electrode output end through the second pull-up resistor and is connected with the cathode of the second static protection tube, and the anode of the second static protection tube is connected with the negative electrode output end.

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