CN206725659U - Based on high ratio compared with wideband pulse signal parameter acquisition unit - Google Patents
Based on high ratio compared with wideband pulse signal parameter acquisition unit Download PDFInfo
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- CN206725659U CN206725659U CN201720438947.XU CN201720438947U CN206725659U CN 206725659 U CN206725659 U CN 206725659U CN 201720438947 U CN201720438947 U CN 201720438947U CN 206725659 U CN206725659 U CN 206725659U
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Abstract
The utility model provide it is a kind of based on high ratio compared with wideband pulse signal parameter acquisition unit, including high-speed buffer, automatic gain controller AGC, high-speed comparator, complicated programmable logic device CPLD, single-chip microcomputer and display screen；Pulse signal is sent to automatic gain controller AGC conditionings after being decayed by high-speed buffer, it is then sent to high-speed comparator, the two-way magnitude of voltage exported by high-speed comparator is sent to complicated programmable logic device CPLD, two-way magnitude of voltage is respectively the 10% and 90% of automatic gain controller AGC output voltages, single-chip microcomputer is sent to after complicated programmable logic device CPLD acquisition pulse signal parameters, is shown on a display screen after being changed by single-chip microcomputer.
Description
Technical field
The utility model is related to it is a kind of based on high ratio compared with wideband pulse signal parameter acquisition unit.
Background technology
At present, the measurement of pulse signal parameter is more using the scheme for reprocessing analog signal digital.Master control uses
FPGA, utilize the analog/digital converter part of high speed（ADC）The amplitude of acquisition pulse signal, the data of ADC collections send FPGA to enter
Row processing, calculate the parameter of pulse signal.Requirement of this scheme to ADC is higher.When pulse signal frequency is higher, it is desirable to higher
Sampling rate.And the cost of high-speed ADC is higher.
Patent " a kind of equally accurate digital frequency meter "（ZL201620427213.7）Propose measurement pulse signal frequency
Method, such as equal precision frequency meter.But measured is mostly cycle and the frequency of pulse signal, does not measure its rising edge and decline
Along the time.And it is extremely of short duration for high-frequency pulse signal, its rising edge and trailing edge time, measurement is more difficult.
Utility model content
The utility model is in order to solve drawbacks described above present in prior art and deficiency, there is provided one kind is based on high ratio
Compared with wideband pulse signal parameter acquisition unit.
In order to solve the above technical problems, the utility model provide it is a kind of based on high ratio compared with wideband pulse signal parameter adopt
Storage, including high-speed buffer, automatic gain controller AGC, high-speed comparator, complicated programmable logic device CPLD, single-chip microcomputer
And display screen；Pulse signal is sent to automatic gain controller AGC conditionings after being decayed by high-speed buffer, then send
To high-speed comparator, the two-way magnitude of voltage exported by high-speed comparator is sent to complicated programmable logic device CPLD, two-way voltage
The 10% and 90% of value respectively automatic gain controller AGC output voltages, complicated programmable logic device CPLD acquisition pulse signals
Single-chip microcomputer is sent to after parameter, is shown on a display screen after being changed by single-chip microcomputer；
The complicated programmable logic device CPLD includes frequency divider, d type flip flop, counter 1, counter 2, data selector
1st, data selector 2 and data selector 3；The frequency divider divides to standard signal, the pulse signal after being divided,
Pulse signal after frequency dividing is triggered by d type flip flop produces signal strobe, and signal strobe is transferred to counter 1 and counter 2 respectively,
Meanwhile measured signal is inputted to counter 1, data selector 1 is transferred to after the counting of counter 1, standard signal is inputted to meter
Number device 2, data selector 2 is transferred to after the counting of counter 2, the signal from data selector 1 and data selector 2 out
Data selector 3 is transferred to, data selector 3 is transferred to single-chip microcomputer by I/O interface, and single-chip microcomputer is changed after reading, aobvious
Show screen display.
Further, the high-speed buffer includes high speed amplifier chip THS3001, the high speed amplifier chip THS3001
In-phase end connecting terminal P1, over the ground series resistance R1 in succession, connection terminal P1 shielding line ground connection, high speed amplifier chip
Connect a resistance R3 between THS3001 end of oppisite phase and output end between parallel connection one resistance R2, output end and connection terminal P2, together
When connection terminal P2 shielding line ground connection, high speed amplifier chip THS3001 use+12V and -12V dual power supplies.
Further, the automatic gain controller AGC includes controllable gain amplifier chip VCA810, high speed amplifier chip
OPA690, comparator chip TLV3501, amplifier chip LM324；Wherein, controllable gain amplifier chip VCA810 use+5V and-
5V dual power supplies, connect connecting resistance R25 between its end of oppisite phase and ground, and in-phase end is connected defeated as signal with connection terminal P20
Enter series resistance R26 between end and ground, output end is connected with resistance R24, and gain control end G connects amplifier chip LM324 output
Voltage Vg；High speed amplifier chip OPA690 in-phase end connecting resistance R24, parallel resistance R23 between end of oppisite phase and output, output is in succession
Connecting terminal P21；Comparator chip TLV3501 anti-phase termination adjustable resistance R27 middle pin, in-phase end pass through resistance R29
Be connected with high speed amplifier chip OPA690 in-phase end, output end tandem tap type diode IN4148, IN4148 diode with
Resistance R21 connects；The discharge and recharge of amplifier chip LM324 in-phase end connecting resistance R21 while connecting resistance R30 and electric capacity C20 composition
Circuit, end of oppisite phase are connected to variable resistor R28 middle pin by resistance R22 with output terminating resistor R20, end of oppisite phase.
Further, the high-speed comparator includes high speed comparable chip TLV3501, wherein, high speed comparable chip TLV3501
Pin 1 it is hanging；Pin 2 is joined directly together with signal input port P3, connect a resistance R31 between ground；Between pin 3 and reference voltage
Connect a resistance R33, and connect a resistance R32 between reference voltage and ground；Pin 4 is grounded；Pin 5 is hanging；Connected between pin 6 and pin 3
One resistance R34, directly it is connected with signal output port P4；Pin 7 is connected with+5V power supplys, two electric capacity C31 in parallel between ground
And C32；Pin 8 is grounded.
Further, the resistance value size of the resistance R1 is 50 Ω.
Further, the resistance value size of the resistance R2 is 1K Ω.
Further, the resistance value size of the resistance R3 is 100 Ω.
Further, resistance R26 resistance value size is 50 Ω.
The advantageous effects that the utility model is reached：The utility model provide it is a kind of based on high ratio compared with broadband arteries and veins
Signal parameter collector is rushed, high-speed comparator uses TI chip TLV3051, and the response time is 4.5ns rail to rail
Output, it is ensured that the processing and realization of high-frequency pulse signal.Using CPLD plus the framework of single-chip microcomputer, and it is aided with AGC stabilizing circuits,
The parameter such as the frequency of acquisition pulse signal, dutycycle, rise time exactly.
Brief description of the drawings
Fig. 1 the utility model composition frame charts；
The complicated programmable logic device CPLD composition frame charts of Fig. 2 the utility model；
The high-speed buffer circuit diagram of Fig. 3 the utility model；
The automatic gain controller agc circuit figure of Fig. 4 the utility model；
The high-speed comparator circuit diagram of Fig. 5 the utility model.
Embodiment
With reference to specific embodiment, the invention will be further described.Following examples are only used for clearly illustrating
Technical scheme, and can not be limited the scope of the invention with this.
The utility model patent is further illustrated with reference to the accompanying drawings and examples.
As shown in Figure 1-2, the utility model provide it is a kind of based on high ratio compared with wideband pulse signal parameter acquisition unit, bag
Include high-speed buffer, automatic gain controller AGC, high-speed comparator, complicated programmable logic device CPLD, single-chip microcomputer and display
Screen；Pulse signal is sent to automatic gain controller AGC conditionings after being decayed by high-speed buffer, be then sent at a high speed
Comparator, the two-way magnitude of voltage exported by high-speed comparator are sent to complicated programmable logic device CPLD, two-way magnitude of voltage difference
For the 10% and 90% of automatic gain controller AGC output voltages, after complicated programmable logic device CPLD acquisition pulse signal parameters
Single-chip microcomputer is sent to, is shown on a display screen after being changed by single-chip microcomputer；
The complicated programmable logic device CPLD includes frequency divider, d type flip flop, counter 1, counter 2, data selector
1st, data selector 2 and data selector 3；The frequency divider divides to standard signal, the pulse signal after being divided,
Pulse signal after frequency dividing is triggered by d type flip flop produces signal strobe, and signal strobe is transferred to counter 1 and counter 2 respectively,
Meanwhile measured signal is inputted to counter 1, data selector 1 is transferred to after the counting of counter 1, standard signal is inputted to meter
Number device 2, data selector 2 is transferred to after the counting of counter 2, the signal from data selector 1 and data selector 2 out
Data selector 3 is transferred to, data selector 3 is transferred to single-chip microcomputer by I/O interface, and single-chip microcomputer is changed after reading, aobvious
Show screen display.
As shown in figure 3, the high-speed buffer includes high speed amplifier chip THS3001, the high speed amplifier chip
THS3001 in-phase end in succession connecting terminal P1, the resistance R1 that resistance is 50 Ω of connecting over the ground to realize and the impedance matching of prime,
Connection terminal P1 shielding line ground connection, a resistance in parallel is 1K between high speed amplifier chip THS3001 end of oppisite phase and output end
A resistance of being connected between Ω resistance R2, output end and connection terminal P2 is 100 Ω resistance R3, while connection terminal P2 screen
Cover line ground connection, high speed amplifier chip THS3001 use+12V and -12V dual power supplies.
As shown in figure 4, the automatic gain controller AGC includes controllable gain amplifier chip VCA810, high speed amplifier core
Piece OPA690, comparator chip TLV3501, amplifier chip LM324；Wherein, controllable gain amplifier chip VCA810 uses+5V
With -5V dual power supplies, connect connecting resistance R25 between its end of oppisite phase and ground, and in-phase end is connected with connection terminal P20 is used as signal
Series resistance R26 between input and ground, output end are connected with resistance R24, and gain control end G connects the defeated of amplifier chip LM324
Go out voltage Vg；High speed amplifier chip OPA690 in-phase end connecting resistance R24, parallel resistance R23 between end of oppisite phase and output, output connect
Connection terminal P21；Comparator chip TLV3501 anti-phase termination adjustable resistance R27 middle pin, in-phase end pass through resistance
R29 is connected with high speed amplifier chip OPA690 in-phase end, output end tandem tap type diode IN4148, IN4148 diode
Connected with resistance R21；The charge and discharge of amplifier chip LM324 in-phase end connecting resistance R21 while connecting resistance R30 and electric capacity C20 composition
Circuit, end of oppisite phase are connected to variable resistor R28 middle pin by resistance R22 with output terminating resistor R20, end of oppisite phase.
To meet pulse signal parameter measurement precision, the situation of other specification of the measured signal in addition to amplitude is not being influenceed
Under, the CPLD amplitude stabilization of signal is will enter into a fixed value, when realizing the frequency of pulse signal, dutycycle, rising
Between etc. parameter collection.Using controllable gain amplifier chip VCA810 as core, it is aided with comparator chip TLV3501 and high speed amplifier
Chip OPA690, amplifier chip LM324；Controllable gain amplifier chip VCA810 gain can pass through the voltage at adjustment pin G ends
To change, and there is the advantages of broadband amplification.High-speed comparator chip TLV3016 is by controllable gain amplifier chip VCA810's
With the voltage of end of oppisite phase compared with, result of the comparison controls detecting circuit for output, and the magnitude of voltage of detecting circuit feeds back to controllable
Gain amplifier chip VCA810 gain control end Vg.What high-speed comparator chip TLV3016 compared is controllable gain amplifier core
The setting voltage of piece VCA810 output signals and its end of oppisite phase, diode IN4148 and RC is to high-speed comparator chip TLV3016
Output signal carry out detection, finally, it is stable after signal exported by high speed amplifier chip OPA690, main function is to realize
Buffering and impedance matching
As shown in figure 5, the high-speed comparator includes high speed comparable chip TLV3501, wherein, high speed comparable chip
TLV3501 pin 1 is hanging；Pin 2 is joined directly together with signal input port P3, connect a resistance R31 between ground；Pin 3 and reference
Connect a resistance R33 between voltage, and connect a resistance R32 between reference voltage and ground；Pin 4 is grounded；Pin 5 is hanging；Pin 6 and pin 3
Between connect a resistance R34, be directly connected with signal output port P4；Pin 7 is connected with+5V power supplys, in parallel two between ground
Individual electric capacity C31 and C32；Pin 8 is grounded.
The high speed comparable chip TLV3501 pin of inverting input 2 connects measured pulse signal, and the pin of in-phase end 3 connects reference voltage,
And hysteretic characteristic is formed by resistance R32 and R34 partial pressure, to improve its jamproof ability.Reference voltage is set respectively
For the 10% and 90% of automatic gain controller AGC output voltages, after comparison, two pulse signals are obtained, are linked into CPLD, profit
Delay between counting to get two pulse signals with CPLD, i.e. measured signal amplitude rise to for 90% time difference from 10%, i.e.,
Gather the rise time of measured signal.Meanwhile CPLD can obtain frequency to wherein certain pulse signal progress equally accurate collection all the way
The parameters such as rate, dutycycle.
The utility model is disclosed with preferred embodiment above, so itself and be not used to limit the utility model, it is all to take
The technical scheme that equivalent substitution or the scheme of equivalent transformation are obtained, all falls within the scope of protection of the utility model.
Claims (8)
1. based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：Including high-speed buffer, automatic gain
Controller AGC, high-speed comparator, complicated programmable logic device CPLD, single-chip microcomputer and display screen；Pulse signal passes through speed buffering
Device is sent to automatic gain controller AGC conditionings after being decayed, be then sent to high-speed comparator, exported by high-speed comparator
Two-way magnitude of voltage be sent to complicated programmable logic device CPLD, two-way magnitude of voltage is respectively automatic gain controller AGC outputs
The 10% of voltage and 90%, single-chip microcomputer is sent to after complicated programmable logic device CPLD acquisition pulse signal parameters, is entered by single-chip microcomputer
Shown on a display screen after row conversion；
The complicated programmable logic device CPLD includes frequency divider, d type flip flop, counter 1, counter 2, data selector 1, number
According to selector 2 and data selector 3；The frequency divider divides to standard signal, the pulse signal after being divided, frequency dividing
Pulse signal afterwards is triggered by d type flip flop and produces signal strobe, and signal strobe is transferred to counter 1 and counter 2 respectively, together
When, measured signal is inputted to counter 1, is transferred to data selector 1 after the counting of counter 1, standard signal is inputted to counting
Device 2, data selector 2 is transferred to after the counting of counter 2, the signal from data selector 1 and data selector 2 out passes
Data selector 3 is defeated by, data selector 3 is transferred to single-chip microcomputer by I/O interface, and single-chip microcomputer is changed after reading, shown
Screen display.
2. it is according to claim 1 based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：It is described
The in-phase end of high-speed buffer including high speed amplifier chip THS3001, high speed amplifier chip THS3001 connecting terminal in succession
P1, over the ground series resistance R1, connection terminal P1 shielding line ground connection, high speed amplifier chip THS3001 end of oppisite phase and output end
Between connected between parallel connection one resistance R2, output end and connection terminal P2 a resistance R3, while connection terminal P2 shielding line connects
Ground, high speed amplifier chip THS3001 use+12V and -12V dual power supplies.
3. it is according to claim 1 based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：It is described
Automatic gain controller AGC includes controllable gain amplifier chip VCA810, high speed amplifier chip OPA690, comparator chip
TLV3501, amplifier chip LM324；Wherein, controllable gain amplifier chip VCA810 use+5V and -5V dual power supplies, its is anti-
Connect connecting resistance R25 between phase end and ground, and in-phase end is connected as signal input part with connection terminal P20, connected between ground
Resistance R26, output end are connected with resistance R24, and gain control end G meets amplifier chip LM324 output voltage Vg；High speed amplifier core
Piece OPA690 in-phase end connecting resistance R24, parallel resistance R23 between end of oppisite phase and output, export connecting terminal P21 in succession；Comparator
Chip TLV3501 anti-phase termination adjustable resistance R27 middle pin, in-phase end pass through resistance R29 and high speed amplifier chip
OPA690 in-phase end is connected, and output end tandem tap type diode IN4148, IN4148 diode is connected with resistance R21；Fortune
Put chip LM324 in-phase end connecting resistance R21 while connecting resistance R30 and electric capacity C20 composition charge-discharge circuit, end of oppisite phase with
Terminating resistor R20 is exported, end of oppisite phase is connected to variable resistor R28 middle pin by resistance R22.
4. it is according to claim 1 based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：It is described
High-speed comparator includes high speed comparable chip TLV3501, wherein, high speed comparable chip TLV3501 pin 1 is hanging；Pin 2 and signal
Input port P3 is joined directly together, connect a resistance R31 between ground；Connect a resistance R33 between pin 3 and reference voltage, reference
Connect a resistance R32 between voltage and ground；Pin 4 is grounded；Pin 5 is hanging；Connected between pin 6 and pin 3 resistance R34, directly with
Signal output port P4 is connected；Pin 7 is connected with+5V power supplys, two electric capacity C31 and C32 in parallel between ground；Pin 8 is grounded.
5. it is according to claim 2 based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：It is described
Resistance R1 resistance value size is 50 Ω.
6. it is according to claim 2 based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：It is described
Resistance R2 resistance value size is 1K Ω.
7. it is according to claim 2 based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：It is described
Resistance R3 resistance value size is 100 Ω.
8. it is according to claim 3 based on high ratio compared with wideband pulse signal parameter acquisition unit, it is characterised in that：Resistance
R26 resistance value size is 50 Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201720438947.XU CN206725659U (en) | 2017-04-24 | 2017-04-24 | Based on high ratio compared with wideband pulse signal parameter acquisition unit |
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| CN201720438947.XU CN206725659U (en) | 2017-04-24 | 2017-04-24 | Based on high ratio compared with wideband pulse signal parameter acquisition unit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110470388A (en) * | 2019-08-22 | 2019-11-19 | 合肥利弗莫尔仪器科技有限公司 | A kind of high speed acquisition circuit quasi real time monitored for pulse laser mean power |
-
2017
- 2017-04-24 CN CN201720438947.XU patent/CN206725659U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110470388A (en) * | 2019-08-22 | 2019-11-19 | 合肥利弗莫尔仪器科技有限公司 | A kind of high speed acquisition circuit quasi real time monitored for pulse laser mean power |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171208 Termination date: 20190424 |