CN114062905B - Chip abrupt voltage testing method and device and storage medium - Google Patents
Chip abrupt voltage testing method and device and storage medium Download PDFInfo
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- CN114062905B CN114062905B CN202210046262.6A CN202210046262A CN114062905B CN 114062905 B CN114062905 B CN 114062905B CN 202210046262 A CN202210046262 A CN 202210046262A CN 114062905 B CN114062905 B CN 114062905B
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Abstract
The invention discloses a chip sudden change voltage testing method, a device and a storage medium, wherein the chip sudden change voltage testing method comprises the following steps: acquiring a capacitance mutation related value of a preset standard chip, wherein the capacitance mutation related value is acquired by scanning the preset standard chip by a preset scanning step length; acquiring a preset total step number of a test chip; and determining the sudden change voltage value of the test chip by adopting a preset algorithm according to the capacitance sudden change correlation value and the preset total step number. Compared with the traditional mode of scanning the voltage one by one, the method has the advantages of simple test process, greatly reduced scanning times, shortened test time, greatly improved test efficiency of the sudden change voltage of the chip, and even faster test yield of the whole card lot, is suitable for large-scale mass production, and is suitable for the MEMS to test the sudden change capacitor product.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a chip sudden change voltage testing method, a device and a storage medium.
Background
When a MEMS capacitor product is subjected to a wafer test (Chip bonding, CP), whether a capacitor of each Chip on the wafer has a sudden change (pullin) is a criterion for measuring the yield of the Chip. The traditional method is that a chip is scanned successively by adding scanning voltage, the capacitance value of a current point is tested, whether the variation of the capacitance value of the current point and the capacitance value of a previous point is larger than a preset capacitance threshold value or not is calculated, if the variation is larger than the preset capacitance threshold value, the current point capacitance is considered to have sudden change, and the current voltage is sudden change voltage; and if the variation is smaller than the preset capacitance threshold, increasing the scanning voltage until the sudden change of the capacitance is detected or the scanning is carried out to the end voltage.
The scanning voltage successive scanning test mode has the advantages of more scanning times, long time and low efficiency, and even if the scanning voltage range is reduced, the scanning times are still more, so the scanning voltage successive scanning test mode is not suitable for large-scale mass production.
Disclosure of Invention
Therefore, it is necessary to provide a method, an apparatus and a storage medium for testing a chip voltage jump for solving the above-mentioned problems in the background art, and by adopting a preset bisection method to test the voltage jump, the number of scanning times is greatly reduced, the testing time is shortened, and the testing efficiency is greatly improved compared with the conventional successive scanning method.
In order to solve the above technical problem, a first aspect of the present application provides a method for testing a chip abrupt voltage, including:
acquiring a capacitance mutation related value of a preset standard chip, wherein the capacitance mutation related value is acquired by scanning the preset standard chip by a preset scanning step length;
acquiring a preset total step number of a test chip;
and determining the sudden change voltage value of the test chip by adopting a preset algorithm according to the capacitance sudden change correlation value and the preset total step number.
In the chip sudden change voltage testing method provided in the above embodiment, a capacitance sudden change related value of a preset standard chip and a preset total step number of a test chip are obtained, where the capacitance sudden change related value is obtained by scanning the preset standard chip with a preset scanning step length; and a preset algorithm is adopted according to the capacitance mutation correlation value and the preset total step number, so that the mutation voltage value of the test chip is determined, the test process is simple, the scanning times are greatly reduced, the test time is shortened, the test efficiency of the chip mutation voltage is greatly improved compared with the traditional successive voltage scanning mode, and the method is suitable for large-scale mass production.
In one embodiment, the determining the sudden change voltage value of the test chip according to the capacitance sudden change related value and the preset total number of steps by using a preset algorithm includes:
acquiring a zero capacitance value and a target abrupt voltage value;
and obtaining the mutation voltage value by adopting a preset bisection method according to the zero capacitance value, the target mutation voltage value, the preset scanning step length, the capacitance mutation related value and the preset total step number.
In one embodiment, the preset total step number is n, n > 2, n is an integer, and the preset scanning step length is step; the step-out voltage value is obtained by adopting a preset bisection method, and the step-out voltage value comprises the following steps:
determining the target abrupt voltage value as a first scanning voltage value, and acquiring a first scanning capacitance value corresponding to the first scanning voltage value;
according to the comparison result of the first scanning capacitance value and the product of the capacitance mutation correlation value and the zero capacitance value, determining the ith scanning voltage value, wherein i is more than 1 and less than or equal to n, and is an integer;
acquiring an ith scanning capacitance value corresponding to the ith scanning voltage value;
and determining the sudden change voltage value according to the comparison result of the ith scanning capacitance value and the product of the capacitance sudden change related value and the zero point capacitance value.
In one embodiment, the determining the ith scan voltage value includes:
judging whether the (i-1) th scanning capacitance value is larger than the product of the capacitance mutation correlation value and the zero capacitance value;
if yes, determining the ith scanning voltage value as Vi=Vi-1-step*2(n-i)；
If not, determining that the ith scanning voltage value is Vi=Vi-1+step*2(n-i)。
In one embodiment, the determining the abrupt voltage value according to the comparison result of the ith scan capacitance value and the product of the capacitance abrupt change correlation value and the zero capacitance value includes:
judging whether the ith scanning capacitance value is larger than the product of the capacitance mutation correlation value and the zero capacitance value;
if yes, determining that the mutation voltage value is CV = Vn；
If not, determining that the mutation voltage value is CV = Vn+ step, where VnThe voltage value is scanned for i = n.
In one embodiment, the obtaining of the sudden change related value of the capacitance of the preset standard chip includes:
acquiring preset standard mutation capacitance values, preset standard zero capacitance values and preset standard mutation pre-capacitance values of a plurality of preset standard chips on a preset standard wafer;
determining a preset standard range of each preset standard chip according to preset standard mutation capacitance values, preset standard zero capacitance values and preset standard pre-mutation capacitance values of each preset standard chip by adopting a preset standard relation;
and determining the overlapping part of the preset standard range according to each preset standard range, wherein the capacitance mutation related value is positioned in the overlapping part of the preset standard range.
In one embodiment, the predetermined standard relationship is:
C’ f/C’ 0<x<C’ s/C’ 0
wherein x is the capacitance mutation correlation value, C’ sFor presetting standard abrupt change capacitance value, C’ 0To preset standard zero capacitance, C’ fThe pre-mutation capacitance value is a preset standard.
In one embodiment, the obtaining the preset total number of steps of the test chip includes:
acquiring a preset first voltage value, a preset second voltage value and a target mutation voltage value; the target abrupt voltage value is greater than the preset first voltage value and less than the preset second voltage value;
and determining the preset total step number by adopting a preset rule according to the preset first voltage value, the preset second voltage value, the preset scanning step length and the target mutation voltage value.
In one embodiment, the preset rule satisfies the following relationship:
Vtarget-step*（20 + 21 + 22 +…+2(n-2)）＜VA(ii) a And is
Vtarget+step*（20 + 21 + 22 +…+2(n-2)）＞VB；
Wherein, VtargetStep is a preset scanning step length, n is a preset total step number, n is more than 2, and n is an integer; vATo preset a first voltage value, VBThe second voltage value is preset.
A second aspect of the present application provides a chip sudden change voltage testing apparatus, including:
the device comprises a capacitance sudden change correlation value acquisition module, a capacitance sudden change correlation value acquisition module and a capacitance sudden change correlation value acquisition module, wherein the capacitance sudden change correlation value acquisition module is used for acquiring a capacitance sudden change correlation value of a preset standard chip, and the capacitance sudden change correlation value is acquired by scanning the preset standard chip by a preset scanning step length;
the preset total step number obtaining module is used for obtaining the preset total step number of the test chip;
and the abrupt voltage determining module is used for determining the abrupt voltage value of the test chip by adopting a preset algorithm according to the capacitance abrupt correlation value and the preset total step number.
In the chip abrupt voltage testing apparatus provided in the above embodiment, the capacitance abrupt change related value of the preset standard chip is obtained by setting the capacitance abrupt change related value obtaining module, the capacitance abrupt change related value is obtained by scanning the preset standard chip with the preset scanning step length, the preset total step number obtaining module is set to obtain the preset total step number of the test chip, and the preset algorithm is adopted by the set abrupt voltage determining module according to the capacitance abrupt change related value and the preset total step number, so as to determine the abrupt voltage value of the test chip.
A third aspect of the application provides a computer-readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method as described above.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 is a schematic flowchart of a method for testing a chip abrupt voltage according to an embodiment of the present disclosure;
fig. 2 is a schematic partial flowchart of a method for testing a chip abrupt voltage according to another embodiment of the present disclosure;
fig. 3 is a partial schematic flow chart of a chip abrupt voltage testing method according to another embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a comparison between a conventional successive scanning and a chip break voltage test method provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of a capacitor voltage curve scanned by the chip break voltage testing method provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of a chip abrupt voltage testing apparatus provided in an embodiment of the present application.
Description of reference numerals: 100. a chip sudden change voltage testing device; 10. a capacitance sudden change correlation value acquisition module; 20. presetting a total step number acquisition module; 30. and an abrupt voltage determination module.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application.
In this application, unless otherwise expressly stated or limited, the terms "connected" and "connecting" are used broadly and encompass, for example, direct connection, indirect connection via an intermediary, communication between two elements, or interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In order to explain the technical solution of the present application, the following description will be given by way of specific examples.
In an embodiment of the present application, a method for testing a chip abrupt voltage, as shown in fig. 1, includes the following steps:
step S10: acquiring a capacitance sudden change related value, wherein the capacitance sudden change related value is acquired by scanning the preset standard chip by a preset scanning step length;
step S20: acquiring a preset total step number of a test chip;
step S30: and determining the sudden change voltage value of the test chip by adopting a preset algorithm according to the capacitance sudden change correlation value and the preset total steps.
In the chip sudden change voltage testing method provided in the above embodiment, a capacitance sudden change related value of a preset standard chip and a preset total step number of a test chip are obtained, where the capacitance sudden change related value is obtained by scanning the preset standard chip with a preset scanning step length; and a preset algorithm is adopted according to the capacitance mutation correlation value and the preset total step number, so that the mutation voltage value of the test chip is determined, the test process is simple, the scanning times are greatly reduced, the test time is shortened, the test efficiency of the chip mutation voltage is greatly improved compared with the traditional successive voltage scanning mode, and the method is suitable for large-scale mass production.
As an example, the capacitance discontinuity associated value is greater than 0, either a non-integer or an integer; the preset standard chip and the test chip are the same product chip, and the preparation process, the size and other related parameters of the preset standard chip and the test chip are the same. The test chip is a chip which needs to test the sudden change voltage at present.
As an example, the capacitance jump correlation value is obtained by scanning a preset standard chip with a preset scanning step in a conventional successive scanning manner, and the specific obtaining manner is described in detail below.
As an example, the preset algorithm includes a preset dichotomy (BSA).
In one embodiment, step S10: the method for obtaining the capacitance mutation correlation value of the preset standard chip comprises the following steps:
step S11: acquiring preset standard mutation capacitance values, preset standard zero capacitance values and preset standard mutation pre-capacitance values of a plurality of preset standard chips on a preset standard wafer;
step S12: determining a preset standard range of each preset standard chip according to preset standard mutation capacitance values, preset standard zero capacitance values and preset standard pre-mutation capacitance values of each preset standard chip by adopting a preset standard relation;
step S13: and determining the overlapping part of the preset standard range according to each preset standard range, wherein the capacitance mutation related value is positioned in the overlapping part of the preset standard range.
Specifically, preparation parameters of a preset standard chip are the same as those of a chip for a sudden change voltage test in the application, and the preset standard chip is used as a standard chip; in the engineering stage, scanning (sweep) the preset standard chip by taking the scanning voltage as 0.2V as an example and every time when the scanning voltage is increased by 0.2V through a traditional successive scanning mode so as to obtain a preset standard sudden change capacitance value, a preset standard zero capacitance value and a preset standard sudden change pre-capacitance value of the preset standard chip.
Specifically, the preset standard pre-mutation capacitance value is a capacitance value corresponding to a previous scanning voltage of the preset standard pre-mutation voltage value, taking the scanning voltage of 0.2V as an example, and if the preset standard pre-mutation voltage value corresponding to the preset standard pre-mutation capacitance value is 14.4V, the preset standard pre-mutation capacitance value is a capacitance value of the chip scanned when the scanning voltage is 14.2V.
For example, when a plurality of predetermined standard chips on a predetermined standard wafer are tested by a conventional successive scanning method, each predetermined standard chip may have a different predetermined standard sudden change capacitance value, a different predetermined standard zero capacitance value, and a different predetermined standard before sudden change capacitance value.
In a further embodiment, the predetermined standard relationship is: c’ f/C’ 0<x< C’ s/C’ 0(ii) a WhereinX is the capacitance jump correlation value, C’ sFor presetting standard abrupt change capacitance value, C’ 0To preset standard zero capacitance, C’ fThe pre-mutation capacitance value is a preset standard.
Specifically, regarding the determination of the capacitance jump related value x, the capacitance value C may be suddenly changed according to the predetermined standard of each predetermined standard chip’ sPreset standard zero capacitance C’ 0Presetting a standard before-mutation capacitance value C’ fDetermining a predetermined standard range (C) for each predetermined standard chip’ f/C’ 0，C’ s/C’ 0）。
The overlapping portion of the predetermined standard range of the plurality of predetermined standard chips on the predetermined standard wafer is selected, for example, the overlapping portion range is (1.1, 1.2), and any value in this range can be used as the value of the capacitance mutation related value x, such as 1.15, 1.16, or 1.17, and so on.
The following test steps are all steps for testing the test chip.
In one embodiment, step S20: the method for acquiring the preset total steps of the test chip comprises the following steps:
step S21: acquiring a preset first voltage value, a preset second voltage value and a target abrupt change voltage value;
step S22: determining a preset total step number by adopting a preset rule according to a preset first voltage value, a preset second voltage value, a preset scanning step length and a target mutation voltage value;
in particular, a first voltage value V is presetAPresetting a second voltage value VBPreset scanning step length and target abrupt change voltage value VtargetAre known and can be determined directly by engineers; testing the sudden change voltage and the target sudden change voltage value V of the chiptargetAre all located at a preset first voltage value VAAnd a preset second voltage value VBWherein the target abrupt voltage value VtargetGreater than a preset first voltage value VAAnd is less than a predetermined second voltagePressure value VB。
As an example, the target abrupt voltage value VtargetGreater than a preset first voltage value VAAnd is less than a predetermined second voltage value VB。
In addition, the target abrupt voltage value VtargetThe target sudden change voltage value V is close to the voltage value of the test chip which has sudden changetargetVoltage values known in advance to engineers.
Specifically, the preset rule satisfies the following relation:
Vtarget-step*（20 + 21 + 22 +…+2(n-2)）＜VA(ii) a And is
Vtarget+step*（20 + 21 + 22 +…+2(n-2)）＞VB；
Wherein, VtargetStep is a preset scanning step length, n is a preset total step number, n is more than 2, and n is an integer; vATo preset a first voltage value, VBThe second voltage value is preset.
As an example, a value of the preset total number of steps n, for example, n =6 or n =7, is selected and substituted into the above relational expression, and the preset total number of steps satisfies the above relational expression through calculation for a limited number of times. Vtarget-step*（20 + 21 + 22 +…+2(n-2)) Is marked as VC，Vtarget+step*（20 + 21 + 22 +…+2(n-2)) Is marked as VD，VC＜VA，VD＞VBRange (V)C，VD) Greater than range (V)A，VB) To ensure that the voltage of the chip which changes suddenly in real time falls into a range (V)C，VD) And the accuracy of the chip mutation voltage test is improved.
As an example, for example, a first voltage value V is presetATaking 10V, presetting a first voltage value VBTaking 20V, and obtaining a target mutation voltage value VtargetThe preset scanning step size is 0.2V at 14V, and when the preset total step number n is 5, V isC=14 – 0.2*(1+2+4+8)=11V＞10V，VD(ii) =14 + 0.2 = (1+2+4+8) =17V < 20V, and when n is 5, the above relational expression is not satisfied; when the preset total step number n is 6, VC=14 – 0.2*(1+2+4+8+16)=7.8V＜10V，VD(ii) =14 + 0.2 = (1+2+4+8+16) =20.2V > 20V, when n takes 6, the above relational expression is satisfied; when the preset total step number n is 7, when VC=14 – 0.2*(1+2+4+8+16+32)=1.4V＜10V，VDWhere (= 14 + 0.2) = 1+2+4+8+16+32) =26.6V > 20V, it is obvious that the range (7.8V, 20.2V) when the preset total step number n takes 6 is smaller than the range (1.4V, 26.6V) when the preset total step number n takes 7, and the search range when the preset algorithm is adopted is smaller, so that the number of scans is further reduced, the test time is shortened, and the test efficiency is improved.
In one embodiment, as shown in FIG. 2, step S30: the method for determining the sudden change voltage value of the test chip by adopting a preset algorithm according to the capacitor sudden change correlation value and the preset total steps comprises the following steps of:
step S31: obtaining zero point capacitance C0And a target abrupt voltage value Vtarget；
Step S32: according to zero point capacitance C0Target abrupt voltage value VtargetAnd obtaining a mutation voltage value CV by adopting a preset bisection method according to the preset scanning step length, the capacitance mutation related value x and the preset total step number n.
Specifically, the preset total step number is n, n is more than 2, and n is an integer; zero point capacitance value C0The capacitance value when the chip scanning voltage is 0V can be used.
In one embodiment, as shown in FIG. 3, step S32: obtaining a sudden change voltage value CV by adopting a preset bisection method, comprising the following steps of:
step S321: the target abrupt change voltage value VtargetIs determined as a first scanning voltage value V1And obtaining a first scanning voltage value V1Corresponding first scanning capacitance value C1；
Step S322: according to the first scanning capacitance value C1And a capacitorAbrupt correlation value x and zero point capacitance value C0Determines the ith scan voltage value V as a result of the comparison of the products ofiI is more than 1 and less than or equal to n, and i is an integer;
step S323: obtaining and ith scanning voltage value ViCorresponding ith scanning capacitance value Ci；
Step S324: according to ith scanning capacitance value CiAnd comparing the product of the capacitance sudden change related value and the zero capacitance value to determine a sudden change voltage value CV.
As an example, the target abrupt voltage value V is settargetAs a first scanning voltage value V1The scanning voltage of the subsequent preset dichotomy in the scanning process can be ensured to approach to the chip mutation voltage continuously, the chip mutation voltage is ensured to be always within the preset dichotomy scanning voltage range, and the accuracy of the preset dichotomy is improved.
Specifically, step S322: determining ith scanning voltage value ViThe method comprises the following steps:
step S3221: determine the i-1 th scanning capacitance value Ci-1Whether the value is larger than the related value x of the sudden change of the capacitance and the zero-point capacitance value C0The product of (a);
step S3222: if yes, determining the ith scanning voltage value as Vi=Vi-1-step*2(n-i)；
Step S3223: if not, determining that the ith scanning voltage value is Vi=Vi-1+step*2(n- i)。
Specifically, step S324: according to ith scanning capacitance value CiAnd comparing the product of the capacitance sudden change related value and the zero capacitance value to determine a sudden change voltage value CV, and the method comprises the following steps:
step S3241: determining the ith scanning capacitance value CiWhether the value is larger than the related value x of the sudden change of the capacitance and the zero-point capacitance value C0The product of (a);
step S3241: if yes, determining that the sudden change voltage value is CV = Vi；
Step S3241: if not, determining that the mutation voltage value is CV = Vi+ step, where VnThe voltage value is scanned for i = n.
Specifically, the preset dichotomy is explained in detail as follows:
step 1: vtarget= V1Obtaining the capacitance C corresponding to V11Judgment of C1＞x* C0；
If C1＞x* C0Then V is2= V1-step*2(n-2)；
If C1≤x* C0Then V is2= V1+step*2(n-2)；
Step 2: test chip at V2Time corresponding capacitance value C2Judgment of C2＞x* C0；
If C2＞x* C0Then V is3= V2-step*2(n-3)；
If C2≤x* C0Then V is3= V2+step*2(n-3)；
And 3, step 3: test chip at V3Time corresponding capacitance value C3Judgment of C3＞x* C0；
If C3＞x* C0Then V is4= V3-step*2(n-4)；
If C3≤x* C0Then V is4= V3+step*2(n-4)；
And 4, step 4: test chip at V4Capacitance C of time-dependent4Judgment of C4＞x* C0；
If C4＞x* C0Then V is5= V4-step*2(n-5)；
If C4≤x* C0Then V is5= V4+step*2(n-5)；
By analogy …
In the (n-2) th step, the test chip is at Vn-2Time corresponding capacitance value C n-2Judgment of C n-2＞x* C0；
If C n-2＞x* C0Then V isn-1= V n-2-step*21；
If C n-2≤x* C0Then V isn-1= V n-2+step*21；
In the step (n-1), the test chip is at Vn-1Time corresponding capacitance value C n-1Judgment of C n-1＞x* C0；
If C n-1＞x* C0Then V isn= V n-1-step*20；
If C n-1≤x* C0Then V isn= V n-1+step*20；
In the nth step, the test chip is at VnTime corresponding capacitance value C nJudgment of C n＞x* C0；
If C n＞x* C0Then CV = Vn；
If C n≤x* C0Then CV = Vn +step。
In the above embodiment, based on the obtained target abrupt voltage value, the zero-point capacitance value, the preset total step number and the preset scanning step length, the preset bisection method is adopted, and the voltage value of each step and the corresponding capacitance value are sequentially calculated according to the preset total step number until the nth scanning voltage value corresponding to the nth step and the nth scanning voltage value V are obtainednCorresponding to the n-th scan capacitance value CnJudging the nth scanning capacitance CnWhether the value is larger than the related value x of the sudden change of the capacitance and the zero-point capacitance value C0X C of0And determining the sudden change voltage value CV of the test chip. Compared with the traditional mode of scanning the voltage of the chip one by one, the method has the advantages that the preset dichotomy test process is simple, the scanning times are greatly reduced, the test time is shortened, the test efficiency of all chip sudden change voltages on the whole wafer is greatly improved, the yield of the whole wafer can be tested more quickly, the method is suitable for large-scale mass production, and the MEMS sudden change capacitor product is suitable for being tested.
In one embodiment, fig. 4 shows a conventional successive scan and a predetermined dichotomy scan of the same chip, respectively, and fig. 5 shows a detailed graph of the predetermined dichotomy test performed in fig. 4; wherein, the set scanning step length is 0.2V, and the scanning range is (10V, 20V). In the traditional successive scanning method, scanning is carried out in sequence from 10V every time when 0.2V is added, corresponding capacitance values are tested, chip abrupt voltage is found when scanning is carried out to 14.4V, and scanning is carried out for 22 times in total; in addition, even if the scan range is reduced, for example, to (13V, 18V), the number of times of testing the capacitor still needs to be 25. Scanning by using a preset bisection method for 6 times in total (as shown in figure 5); the preset dichotomy scanning times are far smaller than the traditional successive scanning times, the preset dichotomy testing process is simple, the scanning times are greatly reduced, the testing time is shortened, the testing efficiency of the chip sudden change voltage is greatly improved, and the method is suitable for large-scale mass production.
In an embodiment of the present application, as shown in fig. 6, a chip sudden change voltage testing apparatus is further provided, where the chip sudden change voltage testing apparatus 100 includes a capacitance sudden change related value obtaining module 10, a preset total step number obtaining module 20, and a sudden change voltage determining module 30, and executes the steps of the chip sudden change voltage testing method.
Specifically, the capacitance sudden change related value obtaining module 10 is configured to obtain a capacitance sudden change related value of a preset standard chip, where the capacitance sudden change related value is obtained by scanning the preset standard chip with a preset scanning step length; the preset total step number obtaining module 20 is configured to obtain a preset total step number of the test chip; the abrupt voltage determination module 30 is configured to determine an abrupt voltage value of the test chip by using a preset algorithm according to the capacitance abrupt change correlation value and a preset total step number.
In the chip abrupt voltage testing apparatus provided in the above embodiment, the capacitance abrupt correlation value of the preset standard chip is obtained by setting the capacitance abrupt correlation value obtaining module, the capacitance abrupt correlation value is obtained by scanning the preset standard chip with the preset scanning step length, the preset total step number of the test chip is obtained by setting the preset total step number obtaining module, and the abrupt voltage determining module adopts the preset algorithm according to the capacitance abrupt correlation value and the preset total step number, so as to determine the abrupt voltage value of the test chip.
In an embodiment of the present application, there is also provided a storage medium having a computer program stored thereon. Which when executed by a processor implements the steps of any of the methods described above.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (Synchlink) DRAM (SLDRAM), Rambus (Rambus) direct RAM (RDRAM), direct bused dynamic RAM (DRDRAM), and bused dynamic RAM (RDRAM). The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A chip sudden change voltage testing method is characterized by comprising the following steps:
acquiring a capacitance mutation related value of a preset standard chip, wherein the capacitance mutation related value is acquired by scanning the preset standard chip by a preset scanning step length;
acquiring a preset total step number of a test chip;
determining the sudden change voltage value of the test chip by adopting a preset algorithm according to the capacitance sudden change correlation value and the preset total steps;
the acquiring of the capacitance mutation correlation value of the preset standard chip comprises the following steps:
acquiring preset standard mutation capacitance values, preset standard zero capacitance values and preset standard mutation pre-capacitance values of a plurality of preset standard chips on a preset standard wafer;
determining a preset standard range of each preset standard chip according to preset standard mutation capacitance values, preset standard zero capacitance values and preset standard pre-mutation capacitance values of each preset standard chip by adopting a preset standard relation;
determining the overlapping part of the preset standard range according to each preset standard range, wherein the capacitance mutation related value is positioned in the overlapping part of the preset standard range;
the preset standard relation is as follows:
C’ f/C’ 0<x< C’ s/C’ 0
wherein x is the capacitance mutation related value, C'sFor said predetermined standard sudden change of capacitance value, C’ 0Is that it isPresetting a standard zero capacitance value, C’ fThe preset standard pre-mutation capacitance value is obtained;
the acquiring of the preset total steps of the test chip comprises the following steps:
acquiring a preset first voltage value, a preset second voltage value and a target abrupt change voltage value; the target abrupt voltage value is greater than the preset first voltage value and less than the preset second voltage value;
determining the preset total step number by adopting a preset rule according to the preset first voltage value, the preset second voltage value, the preset scanning step length and the target mutation voltage value;
wherein the preset rule satisfies the following relation:
Vtarget-step*（20 +21+ 22+ …+2(n-2)）＜VA(ii) a And is
Vtarget+step*（20+ 21+ 22+ …+2(n-2)）＞VB；
Wherein, VtargetFor the target abrupt voltage value, the target abrupt voltage value VtargetThe step is the preset value in the allowable voltage value range when the test chip generates mutation, step is the preset scanning step length, n is the preset total step number, n is more than 2, and n is an integer; vAFor the preset first voltage value, VBAnd setting the preset second voltage value.
2. The method for testing the sudden chip voltage according to claim 1, wherein the step of determining the sudden chip voltage according to the sudden capacitor voltage related value and the preset total number of steps by using a preset algorithm comprises:
acquiring a zero capacitance value and a target abrupt voltage value; the zero capacitance is the capacitance when the scanning voltage of the chip is 0V;
and obtaining the mutation voltage value by adopting a preset bisection method according to the zero capacitance value, the target mutation voltage value, the preset scanning step length, the capacitance mutation related value and the preset total step number.
3. The method for testing the chip abrupt voltage according to claim 2, wherein the obtaining the abrupt voltage value by adopting a preset bisection method comprises:
determining the target abrupt voltage value as a first scanning voltage value, and acquiring a first scanning capacitance value corresponding to the first scanning voltage value;
according to the comparison result of the first scanning capacitance value and the product of the capacitance mutation correlation value and the zero capacitance value, determining the ith scanning voltage value, wherein i is more than 1 and less than or equal to n, and is an integer;
acquiring an ith scanning capacitance value corresponding to the ith scanning voltage value;
and determining the sudden change voltage value according to the comparison result of the ith scanning capacitance value and the product of the capacitance sudden change related value and the zero point capacitance value.
4. The chip sudden change voltage testing method according to claim 3, wherein the determining the ith scanning voltage value comprises:
judging whether the (i-1) th scanning capacitance value is larger than the product of the capacitance mutation correlation value and the zero capacitance value;
if yes, determining the ith scanning voltage value as Vi=Vi-1-step*2(n-i)；
If not, determining that the ith scanning voltage value is Vi=Vi-1+step*2(n- i)。
5. The method for testing the voltage of the sudden change of the chip according to claim 4, wherein the step of determining the voltage value of the sudden change according to the comparison result of the ith scanning capacitance value and the product of the sudden change related value of the capacitance and the zero capacitance value comprises:
judging whether the ith scanning capacitance value is larger than the product of the capacitance mutation correlation value and the zero capacitance value;
if yes, determining that the mutation voltage value is CV = Vn；
If not, determining that the mutation voltage value is CV = Vn+ step, where VnThe voltage value is scanned for i = n.
6. The chip sudden change voltage testing method according to any one of claims 1 to 5, wherein the capacitance sudden change related value is a non-integer or an integer greater than 0.
7. The method for testing the chip abrupt voltage according to any one of claims 1 to 5, wherein the preset standard chip and the test chip are the same product chip.
8. The chip abrupt voltage test method according to any one of claims 1 to 5, wherein the preset first voltage value VAIs 10V, the preset second voltage value VBThe target abrupt voltage value is 14V, and the preset scanning step is 0.2V.
9. A chip sudden change voltage testing device is characterized by comprising a capacitance sudden change related value acquisition module, a preset total step number acquisition module and a sudden change voltage determination module; wherein
The capacitance sudden change related value obtaining module is used for obtaining a capacitance sudden change related value of a preset standard chip, the capacitance sudden change related value is obtained by scanning the preset standard chip by using a preset scanning step length, and the obtaining of the capacitance sudden change related value of the preset standard chip includes:
acquiring preset standard mutation capacitance values, preset standard zero capacitance values and preset standard mutation pre-capacitance values of a plurality of preset standard chips on a preset standard wafer;
determining a preset standard range of each preset standard chip according to preset standard mutation capacitance values, preset standard zero capacitance values and preset standard pre-mutation capacitance values of each preset standard chip by adopting a preset standard relation;
determining the overlapping part of the preset standard range according to each preset standard range, wherein the capacitance mutation related value is positioned in the overlapping part of the preset standard range;
the preset standard relation is as follows:
C’ f/C’ 0<x< C’ s/C’ 0
wherein x is the capacitance mutation related value, C'sFor said predetermined standard sudden change of capacitance value, C’ 0For said predetermined standard zero capacitance value, C’ fThe preset standard pre-mutation capacitance value is obtained;
the preset total step number obtaining module is used for obtaining the preset total step number of the test chip, and the obtaining of the preset total step number of the test chip comprises the following steps:
acquiring a preset first voltage value, a preset second voltage value and a target abrupt change voltage value; the target abrupt voltage value is greater than the preset first voltage value and less than the preset second voltage value;
determining the preset total step number by adopting a preset rule according to the preset first voltage value, the preset second voltage value, the preset scanning step length and the target mutation voltage value;
wherein the preset rule satisfies the following relation:
Vtarget-step*（20+ 21+ 22+ …+2(n-2)）＜VA(ii) a And is
Vtarget+step*（20+21+22+…+2(n-2)）＞VB；
Wherein, VtargetFor the target abrupt voltage value, the target abrupt voltage value VtargetWhen the test chip is subjected to sudden change, the preset value in the allowable voltage value range is obtained, step is the preset scanning step length, n is the preset total step number, n is more than 2, and n is an integer; vAFor the preset first voltage value, VBSetting the preset second voltage value;
and the sudden change voltage determining module is used for determining the sudden change voltage value of the test chip by adopting a preset algorithm according to the capacitance sudden change related value and the preset total step number.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 8.
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