CN103217640A - Judgment method for test conditions of internal analog signals of chip - Google Patents
Judgment method for test conditions of internal analog signals of chip Download PDFInfo
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- CN103217640A CN103217640A CN2013101031750A CN201310103175A CN103217640A CN 103217640 A CN103217640 A CN 103217640A CN 2013101031750 A CN2013101031750 A CN 2013101031750A CN 201310103175 A CN201310103175 A CN 201310103175A CN 103217640 A CN103217640 A CN 103217640A
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Abstract
The invention provides a judgment method for test conditions of internal analog signals of a chip. The method comprises the following steps of: providing a plurality of different drive voltages to obtain a plurality of output signals; and according to a comparison result of a difference value of the output signals and a reference value, judging whether the current test conditions are reliable or not. A principle that when the test conditions are reliable, an obtained test result is also reliable, and the reliable test result is directed to a stable test result is utilized, so that whether the current test conditions are reliable or not can be judged, and the reliability on testing the internal analog signals of the chip is further ensured.
Description
Technical field
The present invention relates to the ic manufacturing technology field, particularly a kind of decision method of chip internal simulating signal test condition.
Background technology
The whole manufacturing process of integrated circuit (IC) chip mainly comprises: chip design, chip production (mainly realizing the production of chip by the wafer manufacturing) and chip testing.Wherein, each process is all being brought into play crucial effects in the manufacture process of integrated circuit (IC) chip.The function of chip design and chip production is self-evident, and the two is the elementary process that chip produces, and is also determining the quality of chip functions.And chip testing, it is also bringing into play important effect in the manufacture process of integrated circuit (IC) chip.Chip testing can be found problem/defective of existing in chip design or chip production, thereby prevents that bad product from coming into the market; Simultaneously, can also correct the problem that is present in chip design and the chip production as early as possible, produce qualified integrated circuit (IC) chip.
In the test process of integrated circuit (IC) chip, the testing apparatus of use mainly comprises: and test machine (Automatic Test Equipment, ATE) and probe station (prober).Wherein, test machine is a kind of specialized equipment that is used for chip and other finished product tests, can realize the measurement of various electrical parameters, to detect the electrical functionality of integrated circuit (IC) chip.Probe station is a kind of equipment that is used for chip testing in the integrated circuit (IC) chip manufacture process, and the fixedly step pitch of mainly finishing wafer moves, to detect the different chips on the wafer.
When utilizing above-mentioned testing apparatus that integrated circuit (IC) chip is tested, test machine will be to chip to be measured (also being wafer to be measured) output one driving voltage.Under this driving voltage, chip to be measured will produce a plurality of electrical parameters, reference voltage V bg/Vep/Vee etc. for example, and test machine detects/obtains these electrical parameters.According to these electrical parameters, just can judge the quality of chip to be measured, chip promptly to be measured is qualified or defective.
In existing integrated circuits chip testing process, the driving voltage of test machine output is a fixed value.But, along with chip integrated on the wafer become increasingly complex, meticulous, especially, the integrated interference after the more intense RFIP chip on the wafer, the test result that such test mode (test machine is exported the driving voltage of a fixed value) is drawn is more and more unreliable.In some chip testings, occurred: the chip yield is less than 30%; And in 70% the bad chip, there is 50% chip to be because the underproof test result of reference voltage V bg.But further test experience is but found: the underproof conclusion of those reference voltage V bg has very that major part is wrong, and promptly a lot of qualified chips are surveyed by mistake and are defective chip.Hence one can see that, special in the existing chip test, and the signal testing condition of chip internal simulation exists error.
Therefore, judge the whether reliable a great problem that has become those skilled in the art to need to be resolved hurrily of chip internal simulating signal test condition.
Summary of the invention
The object of the present invention is to provide a kind of decision method of chip internal simulating signal test condition, unreliable to solve existing chip internal simulation signal testing condition, cause the inaccurate problem of chip testing.
For solving the problems of the technologies described above, the invention provides a kind of decision method of chip internal simulating signal test condition, the decision method of described chip internal simulating signal test condition comprises:
A plurality of different driving voltages are provided;
Under a plurality of different driving voltages, obtain a plurality of output signals;
When the difference between these a plurality of output signals during, judge that current test condition is reliable less than a reference value.
Optionally, in the decision method of described chip internal simulating signal test condition, described output signal is reference voltage V bg.
Optionally, in the decision method of described chip internal simulating signal test condition, described reference value is 2mV～10mV.
Optionally, in the decision method of described chip internal simulating signal test condition, described reference value is 3mV～6mV.
Optionally, in the decision method of described chip internal simulating signal test condition, the driving voltage quantity that provides is 3～5.
Optionally, in the decision method of described chip internal simulating signal test condition, the magnitude of voltage span of described driving voltage is 1.8V～3.3V.
Optionally, in the decision method of described chip internal simulating signal test condition, the difference range between adjacent two driving voltages of magnitude of voltage size is 0.1V～0.8V.
Optionally, in the decision method of described chip internal simulating signal test condition, the driving voltage quantity that provides is 3, and the magnitude of voltage of 3 driving voltages is respectively 1.8V, 2.5V and 3.3V; Perhaps the magnitude of voltage of 3 driving voltages is respectively 1.8V, 2.6V and 3.3V.
Optionally, in the decision method of described chip internal simulating signal test condition, the driving voltage quantity that provides is 5, and the magnitude of voltage of 5 driving voltages is respectively 1.8V, 2.2V, 2.6V, 3.0V and 3.3V.
Optionally, in the decision method of described chip internal simulating signal test condition,, judge that current test condition is reliable when these a plurality of output signals difference between any two during all less than a reference value; Perhaps when surpassing half less than a reference value in these a plurality of output signals difference between any two, judge that current test condition is reliable.
In the decision method of chip internal simulating signal test condition provided by the invention, by a plurality of different driving voltages are provided, thereby obtain a plurality of output signals,, thereby judge that reliably whether current test condition according to the difference between these a plurality of output signals and the comparative result of reference value.At this, utilized when test condition is reliable, the test result that is drawn also will be reliable, and test result will point to this principle of stable test result reliably, thereby reliably whether can judge current test condition, and then guarantee reliability the test of chip internal simulating signal.
Description of drawings
Fig. 1 is the schematic flow sheet of decision method of the chip internal simulating signal test condition of the embodiment of the invention.
Embodiment
Be described in further detail below in conjunction with the decision method of the drawings and specific embodiments the chip internal simulating signal test condition of the present invention's proposition.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Please refer to Fig. 1, it is the schematic flow sheet of decision method of the chip internal simulating signal test condition of the embodiment of the invention.As shown in Figure 1, the decision method of described chip internal simulating signal test condition comprises:
S10: a plurality of different driving voltages are provided;
S11: under a plurality of different driving voltages, obtain a plurality of output signals;
S12:, judge that current test condition is reliable when the difference between these a plurality of output signals during less than a reference value.
At this, by a plurality of different driving voltages are provided, thereby obtain a plurality of output signals, according to the difference between these a plurality of output signals and the comparative result of reference value, thereby judge that reliably whether current test condition.At this, utilized when test condition is reliable, the test result that is drawn also will be reliable, and test result will point to this principle of stable test result reliably, thereby reliably whether can judge current test condition, and then guarantee reliability the test of chip internal simulating signal.
Subsequent, further specified in conjunction with two specific embodiments.
[embodiment one]
In the present embodiment, provide three different driving voltages, the magnitude of voltage of these three driving voltages is respectively 1.8V, 2.5V and 3.3V.At this, the rated voltage of considering chip to be measured is between 1.8V～3.3V, and therefore, selected three different driving voltages are all between 1.8V～3.3V.Certainly, as if the improvement along with chip design, the rated voltage of chip to be measured changes, and for example the range of nominal tension of chip to be measured becomes 2.0V～5.0V, and then this moment, preferably the span of driving voltage was between 2.0V～5.0V.Further, in order to ensure the reliability that test condition is judged, the difference between selected three driving voltages is big as much as possible.Preferably, the difference range between adjacent two driving voltages of magnitude of voltage size is 0.1V～0.8V, and for example difference is 0.1V, 0.2V, 0.3V, 0.4V, 0.5V, 0.6V, 0.7V, 0.8V etc.In the present embodiment, the magnitude of voltage of these three driving voltages is respectively 1.8V, 2.5V and 3.3V, and the difference between adjacent two driving voltages of magnitude of voltage size is respectively 0.7V and 0.8V.As can be known, obtained maximum difference between three driving voltages at this.In other embodiments of the invention, described three driving voltages also can be got other values, for example, are respectively 1.8V, 2.6V and 3.3V, at this moment, and the same maximum difference of having obtained between three driving voltages; In addition, also can get the value of other combinations such as 2.0V, 2.6V and 3.2V respectively, not enumerate one by one at this.
Then, under a plurality of different driving voltages, obtain a plurality of output signals.In the present embodiment, the output signal of being obtained is reference voltage V bg.At this, consider to cause the reason of chip erroneous judgement to be measured to be that mainly the output of reference voltage V bg is inaccurate, therefore, in the output signal that present embodiment provides, mainly consider this parameter of reference voltage V bg.Concrete, be under the situation of 1.8V at driving voltage, obtain the value of reference voltage V bg; Then, driving voltage is changed to 2.5V, under this magnitude of voltage, obtain the value of reference voltage V bg; Follow again, driving voltage is changed to 3.3V, under this magnitude of voltage, obtain the value of reference voltage V bg.Under above-mentioned three driving voltages, just can obtain three reference voltage V bg.
Then, these three reference voltage V bg are carried out the difference computing, obtain the difference of three reference voltage V bg,, judge that current test condition is reliable when the difference of this three reference voltage V bg during less than a reference value.According to the strict degree difference to test condition, described reference value can be got different values, and preferred, described reference value is 2mV～10mV, and for example, described reference value value is 2mV, 3mV, 4mV, 5mV, 6mV, 7mV, 8mV, 9mV, 10mV etc.In the present embodiment, described reference value value is 3mV, promptly when the difference of this three reference voltage V bg during less than 3mV, judges that current test condition is reliable.
In the present embodiment, when these a plurality of output signals difference between any two during, judge that current test condition is reliable all less than a reference value (being 3mV).In other embodiments of the invention, also can be when surpassing half less than a reference value (being 3mV) in these a plurality of output signals difference between any two, judge that current test condition is reliable.For example, in the difference of three reference voltage V bg two during, judge that promptly current test condition is reliable less than 3mV.
According to the decision method of said chip internal simulation signal testing condition just decidable whether go out current test condition reliable, if current test condition is reliable, just can further carry out chip testing; If test condition is unreliable, just can carry out the test condition adjustment, for example adjust for the condition of work of the testing tool of using (mainly comprising test machine and probe station), the voltage of test machine is heightened; Probe station is cleaned, thus the contact reliability between assurance and the chip to be measured etc.
[embodiment two]
In the present embodiment, the driving voltage quantity that provides is five, and the magnitude of voltage of these five driving voltages is respectively 1.8V, 2.2V, 2.6V, 3.0V and 3.3V.Then, under these five driving voltages, obtain five reference voltage V bg respectively, and then obtain five reference voltage V bg differences.These five reference voltage V bg differences and a reference value are compared,, judge that current test condition is reliable when this five reference voltage V bg differences during less than reference value.
Compared to embodiment one, in present embodiment two, owing to selected more a plurality of driving voltages for use, thus the judgement of resulting test condition will be more reliable.In other embodiments of the invention, can also select more a plurality of driving voltages or less driving voltage for use, for example choose four different driving voltages and carry out the test condition judgement, perhaps choose six different driving voltages and carry out the test condition judgement.Preferably, consider in conjunction with the accuracy requirement of judging and the complexity of decision method, the driving voltage quantity that provides is 3～5.
By the decision method of chip internal simulating signal test condition provided by the invention, be judged to be test condition reliable after, carry out again in the chip testing, resulting chip yield is greater than 85%; And in 15% bad chip, only have 1.02% chip to be because reference voltage V bg is defective.I.e. decision method by chip internal simulating signal test condition provided by the invention, filtering in the chip testing, for the erroneous judgement of reference voltage V bg, improved the accuracy and the reliability of chip testing.
Foregoing description only is the description to preferred embodiment of the present invention, is not any qualification to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure all belong to the protection domain of claims.
Claims (10)
1. the decision method of a chip internal simulating signal test condition is characterized in that, comprising:
A plurality of different driving voltages are provided;
Under a plurality of different driving voltages, obtain a plurality of output signals;
When the difference between these a plurality of output signals during, judge that current test condition is reliable less than a reference value.
2. the decision method of chip internal simulating signal test condition as claimed in claim 1 is characterized in that, described output signal is reference voltage V bg.
3. the decision method of chip internal simulating signal test condition as claimed in claim 2 is characterized in that, described reference value is 2mV～10mV.
4. the decision method of chip internal simulating signal test condition as claimed in claim 3 is characterized in that, described reference value is 3mV～6mV.
5. as the decision method of each the described chip internal simulating signal test condition in the claim 1 to 4, it is characterized in that the driving voltage quantity that provides is 3～5.
6. the decision method of chip internal simulating signal test condition as claimed in claim 5 is characterized in that, the magnitude of voltage span of described driving voltage is 1.8V～3.3V.
7. the decision method of chip internal simulating signal test condition as claimed in claim 6 is characterized in that, the difference range between adjacent two driving voltages of magnitude of voltage size is 0.1V～0.8V.
8. the decision method of chip internal simulating signal test condition as claimed in claim 5 is characterized in that, the driving voltage quantity that provides is 3, and the magnitude of voltage of 3 driving voltages is respectively 1.8V, 2.5V and 3.3V; Perhaps the magnitude of voltage of 3 driving voltages is respectively 1.8V, 2.6V and 3.3V.
9. the decision method of chip internal simulating signal test condition as claimed in claim 5 is characterized in that, the driving voltage quantity that provides is 5, and the magnitude of voltage of 5 driving voltages is respectively 1.8V, 2.2V, 2.6V, 3.0V and 3.3V.
10. as the decision method of each the described chip internal simulating signal test condition in the claim 1 to 4, it is characterized in that,, judge that current test condition is reliable when these a plurality of output signals difference between any two during all less than a reference value; Perhaps when surpassing half less than a reference value in these a plurality of output signals difference between any two, judge that current test condition is reliable.
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| CN2013101031750A CN103217640A (en) | 2013-03-27 | 2013-03-27 | Judgment method for test conditions of internal analog signals of chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103809111A (en) * | 2014-03-05 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Chip test circuit and test method thereof |
| CN111615635A (en) * | 2018-01-17 | 2020-09-01 | 罗伯特·博世有限公司 | Circuit for testing main internal signal of ASIC |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0395471A (en) * | 1989-09-08 | 1991-04-19 | Toshiba Corp | Testing apparatus of electronic part |
| US5742177A (en) * | 1996-09-27 | 1998-04-21 | Intel Corporation | Method for testing a semiconductor device by measuring quiescent currents (IDDQ) at two different temperatures |
| US6230293B1 (en) * | 1998-07-24 | 2001-05-08 | Lucent Technologies Inc. | Method for quality and reliability assurance testing of integrated circuits using differential Iddq screening in lieu of burn-in |
| CN101996856A (en) * | 2009-08-26 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Real-time monitoring method of acceptance test of wafer |
| CN102928761A (en) * | 2012-11-20 | 2013-02-13 | 上海宏力半导体制造有限公司 | Wafer test system and wafer test method |
-
2013
- 2013-03-27 CN CN2013101031750A patent/CN103217640A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0395471A (en) * | 1989-09-08 | 1991-04-19 | Toshiba Corp | Testing apparatus of electronic part |
| US5742177A (en) * | 1996-09-27 | 1998-04-21 | Intel Corporation | Method for testing a semiconductor device by measuring quiescent currents (IDDQ) at two different temperatures |
| US6230293B1 (en) * | 1998-07-24 | 2001-05-08 | Lucent Technologies Inc. | Method for quality and reliability assurance testing of integrated circuits using differential Iddq screening in lieu of burn-in |
| CN101996856A (en) * | 2009-08-26 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Real-time monitoring method of acceptance test of wafer |
| CN102928761A (en) * | 2012-11-20 | 2013-02-13 | 上海宏力半导体制造有限公司 | Wafer test system and wafer test method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103809111A (en) * | 2014-03-05 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Chip test circuit and test method thereof |
| CN103809111B (en) * | 2014-03-05 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | The test circuit of chip and method of testing thereof |
| CN111615635A (en) * | 2018-01-17 | 2020-09-01 | 罗伯特·博世有限公司 | Circuit for testing main internal signal of ASIC |
| CN111615635B (en) * | 2018-01-17 | 2023-11-28 | 罗伯特·博世有限公司 | Circuit for testing main internal signals of ASIC |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140507 |
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Effective date of registration: 20140507 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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Application publication date: 20130724 |