CN105119600B - A kind of automatic band calibration method for making phase-locked loop systems quick lock in - Google Patents

A kind of automatic band calibration method for making phase-locked loop systems quick lock in Download PDF

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CN105119600B
CN105119600B CN201510601133.9A CN201510601133A CN105119600B CN 105119600 B CN105119600 B CN 105119600B CN 201510601133 A CN201510601133 A CN 201510601133A CN 105119600 B CN105119600 B CN 105119600B
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frequency
dividing ratio
frequency dividing
window comparator
data
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CN105119600A (en
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吴建辉
丁欣
陈超
黄成�
李红
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Southeast University
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02—Automatic frequency control
    • H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
    • H03J7/06—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

The invention discloses a kind of automatic band calibration method for making phase-locked loop systems quick lock in, AFC module is corrected to VCO frequency band, and automatically selects frequency band according to target frequency, realizes the quick lock in of phaselocked loop.The present invention is using closed-loop corrected, the frequency dividing ratio saltus step of frequency divider is controlled, Vctrl voltages is locked using cycle of phase-locked loop, obtains the feature frequency dividing ratio of every frequency band successively, the correction of every frequency band corresponding characteristic frequency in actual circuit is realized, and feature frequency dividing ratio control word is preserved with register.Based on the feature frequency dividing ratio result latched in said process, under normal operating conditions, the external world provides the frequency dividing ratio corresponding to target frequency, extrapolates the frequency band residing for frequency automatically, directly puts frequencyband coding, realizes the quick lock in of phaselocked loop.The AFC algorithms proposed in the present invention only need the less register of number just to can record, calculate the correction datas of a large amount of frequencies, have not only economized on resources but also can realize the quick lock in of phaselocked loop.

Description

A kind of automatic band calibration method for making phase-locked loop systems quick lock in
Technical field
The present invention relates to the automatic frequency that one kind makes phaselocked loop (Phase Locked Loop, abbreviation PLL) system quick lock in Band calibration (abbreviation AFC) method, belongs to the communication technology.
Background technology
Phaselocked loop is the important component of radio-frequency system, frequency of the increasing application to transceiver in work Switch speed has higher requirement, and this just needs phaselocked loop energy quick lock in.
In the design process, the tuning of voltage controlled oscillator (Voltage-Controlled Oscillator, abbreviation VCO) Curve is often designed to a plurality of, and the tuning gain of every curve is smaller, can thus take into account loop stability and enough Big frequency coverage.The quick lock in of phaselocked loop is realized, in addition to improving the performance of loop in itself, seeks to realize soon The accurate frequency band selection of speed.Being influenceed by factors such as technique, temperature, the frequency band of the VCO in phase-locked loop systems can shift, this It is very unreliable to allow for the direct result judged in advance based on emulation, it is necessary to seek it is a kind of in the case of loop foundation can gram The interference for taking the factors such as technique, temperature automatically determines the control method of frequency band.Traditional scans under mode, is locked to specific It is the time that frequency expends, most of all to consume in the searching of frequency band, it is just no longer suitable for the application for needing quick lock in With.We must probe into more rapidly effective frequency band selection mode.
The content of the invention
Goal of the invention：In order to overcome the deficiencies in the prior art, the present invention, which provides one kind, contributes to phase-locked loop systems The automatic band calibration method of quick lock in.
Technical scheme：To achieve the above object, the technical solution adopted by the present invention is：
A kind of automatic band calibration method for making phase-locked loop systems quick lock in, carried out certainly using automatic band calibration system Dynamic band calibration, automatic band calibration system are in correction mode at the beginning of starting, mode of operation are in after the completion of correction mode；
Course of work during correction mode comprises the following steps：
1.1) complement mark signal mark=0 is corrected；Frequency band sum is n, i=0, into step 1.2)；
1.2) frequency band i frequencyband coding is Fre_data [i], and frequency band i feature frequency dividing ratio discreet value is Eva_data [i], into step 1.3)；
1.3) judge whether control voltage signal Vctrl is locked in stop voltage by the output valve of correcting window comparator In the range of：If not locking, frequency dividing ratio saltus step is until locking；If locking, into step 1.4)；
1.4) control voltage signal Vctrl locking time-frequency bands i feature frequency dividing ratio actual value Div_data [i] is preserved, is entered Enter step 1.5)；
If 1.5) i ＜ n, the feature frequency dividing ratio that frequency band i+1 is adjusted according to Eva_data [i] and Div_data [i] is estimated Value Eva_data [i+1], into step 1.6)；If i >=n, into step 1.7)；
1.6) i=i++, return to step 1.2)；
1.7) all frequency bands all correct completion, correction complement mark signal mark=1；
Course of work during mode of operation comprises the following steps：
2.1) complement mark signal mark=1, the given target frequency dividing ratio Div_in for needing to lock in outside are corrected；
2.2) the feature frequency dividing ratio actual value Div_data [i] determined when being completed according to correction mode and frequencyband coding Fre_ Data [i] relation, frequencyband coding corresponding with the feature frequency dividing ratio actual value that target frequency dividing ratio Div_in is closest is made Fre_data is encoded for preset frequency bands；
2.3) output valve of operation window comparator judges whether preset frequency bands coding Fre_data is correct：If incorrect It is modified；Correcting window comparator output valve bound is in the range of operation window comparator output valve bound.
Preferably, in the step 1.3), the method for frequency dividing ratio saltus step is：If control voltage signal Vctrl is higher than correction The upper voltage limit of window comparator, the then downward saltus step of frequency dividing ratio；If control voltage signal Vctrl is less than correcting window comparator Lower voltage limit, the then upward saltus step of frequency dividing ratio.
Preferably, in the step 2.3), if preset frequency bands coding is incorrect, it is modified, the method for amendment is：Will Frequencyband coding corresponding with the feature frequency dividing ratio actual value that target frequency dividing ratio Div_in distances time are near encodes as preset frequency bands, directly It is correct to preset frequency bands coding.
Preferably, the digital processing part in this method is realized by Verilog language, correcting window comparator and work Window comparator is realized by analog circuit；In order to ensure the ageing of the stabilization of sequential and sampling, what analog circuit was realized The clock for the numerical portion that window comparator and Verilog language are realized uniformly provides by numerical portion.Numerical portion when Clock slightly lags than the clock of window comparator, to ensure that control voltage signal Vctrl deals with time after sampling, ensures simultaneously Sequential is accurate.
In the inventive method, automatic band calibration system is in correction mode at the beginning of starting, now the work shape of phaselocked loop State is different from traditional approach, and the thinking that traditional phaselocked loop uses is fixed frequency dividing ratio, feedback control control voltage signal Vctrl Change, locking frequency.This method feature under correction mode is：Fixed frequency band, pass through the output control of correcting window comparator The saltus step of frequency dividing ratio processed, search out a suitable frequency so that control voltage signal Vctrl can be locked in less voltage In the range of.Obtain the feature frequency dividing ratio of every frequency band successively using cycle of phase-locked loop locking control voltage signal Vctrl, realize every The correction of bar frequency band corresponding characteristic frequency in actual circuit.
In this method, the property of the determination of the upper lower limit value of correcting window comparator to phaselocked loop in itself is related, window model Usual smaller (near the median of control voltage signal Vctrl excursions) is enclosed, but is to ensure that wherein at least one The reachable frequency of phase-locked loop systems precision.In order to shorten correction time, discreet value is provided to the feature frequency dividing ratio of each frequency band, and And the discreet value of the correction next frequency band of modified result according to previous frequency band.
After the completion of correction, according to correction result, according to external target frequency, frequency band residing for automatic decision is directly preset Accurate frequencyband coding, shorten locking time.During control voltage signal Vctrl is locked in by the correcting window comparator of this method Between value near, the feature frequency dividing ratio of frequency band is also about the median of all frequencies on frequency band.According to the frequency dividing ratio of outside offer certainly The reckoning process of dynamic selection frequency band, exactly judge target frequency apart from which characteristic frequency closer to then this characteristic frequency pair The frequency band answered is frequency band where target frequency.
In actual circuit of the present invention, digital processing part is realized by Verilog language, correcting window comparator and work Window comparator is realized by analog circuit.Window comparator is made up of two analog computing amplifiers, with Hyblid Buffer Amplifier Level and sampling keep logic circuit, sample by clock control.Window comparator is used to turn control voltage signal Vctrl size Turn to two digits coding：If control voltage signal Vctrl is higher than upper voltage limit, export " 10 "；If control voltage signal Vctrl Less than lower voltage limit, export " 01 "；If control voltage signal Vctrl is between upper and lower voltage limit, export " 11 ".Two digits Coding input is to numerical portion, for controlling the saltus step of frequency dividing ratio or frequencyband coding.
Beneficial effect：The automatic band calibration method provided by the invention for making phase-locked loop systems quick lock in, with existing skill Art is compared, it is only necessary to using the correcting algorithm for being different from conventional thought, subsequent normal operation state at the beginning of whole system starts Frequency band just can be directly and accurately found down, realize the quick lock in of phaselocked loop.The locking control voltage signal Vctrl used Bearing calibration, key point is corrected, overcomes adverse effect caused by the factors such as technique, temperature, it is only necessary to which number is less Register just can record, calculate the correction data of a large amount of frequencies, for the more phase-locked loop systems of target frequency, both save Resource can be realized again is switched fast locking.
Brief description of the drawings
Fig. 1 is the overall structure block diagram of AFC module in the present invention；
Fig. 2 is the schematic diagram of AFC module in the present invention；
Fig. 3 is numerical portion algorithm flow chart；
Fig. 4 is that window voltage sets schematic diagram；
Fig. 5 numerical portions inside and comparator clock simulation result (4 road clocks have been reserved during design)；
Fig. 6 .1 calibration phases, frequencyband coding automatic switchover digital-to-analogue associative simulation (analog signal result)；
Fig. 6 .2 calibration phases, frequencyband coding automatic switchover digital-to-analogue associative simulation (data signal result)；
Fig. 7 .1 calibration phases, frequency dividing ratio coding saltus step locking digital-to-analogue associative simulation (analog signal result)；
Fig. 7 .2 calibration phases, frequency dividing ratio coding saltus step locking digital-to-analogue associative simulation (data signal result)；
Fig. 8 normal work stages, automatic calculate put frequencyband coding emulation.
Embodiment
The present invention is further described below in conjunction with the accompanying drawings.
A kind of automatic band calibration method for making phase-locked loop systems quick lock in, AFC module carry out school to VCO frequency band Just, and according to target frequency frequency band is automatically selected, realizes the quick lock in of phaselocked loop.The present invention is using closed-loop corrected, control The frequency dividing ratio saltus steps of frequency divider, Vctrl voltages are locked using cycle of phase-locked loop, obtain the feature frequency dividing ratio of every frequency band successively, The correction of every frequency band corresponding characteristic frequency in actual circuit is realized, and feature frequency dividing ratio control word is preserved with register. Based on the feature frequency dividing ratio result latched in said process, under normal operating conditions, the external world provides point corresponding to target frequency Frequency ratio, the frequency band residing for frequency is extrapolated automatically, directly puts frequencyband coding, realize the quick lock in of phaselocked loop.Carried in the present invention The AFC algorithms gone out are using the calibration thought for being different from conventional thought, it is only necessary to which the less register of number just can record, calculate largely The correction data of frequency, not only economized on resources but also can realize the quick lock in of phaselocked loop.
The above-mentioned automatic band calibration method for making phase-locked loop systems quick lock in, carried out certainly using automatic band calibration system Dynamic band calibration, automatic band calibration system are in correction mode at the beginning of starting, mode of operation are in after the completion of correction mode.It is real In the circuit of border, window comparator 1 (correcting window comparator) and window comparator 2 (operation window comparator) are real with analog circuit Existing, digital processing part is described with Verilog language.It is the block diagram of AFC module basic structure as shown in Figure 1, Fig. 2 is shown The schematic diagram of AFC module, Fig. 3 show the flow chart that numerical portion Verilog language describes in schematic diagram.PFD/CP is in figure Phase frequency detector and charge pump, LPF are low pass filter, and VCO is voltage controlled oscillator, and DIV is frequency divider, window comparator 1 Export as cmp1, the output of window comparator 2 is cmp2；Rst_n is reset signal, and clk is clock signal, after clk0 is frequency dividing Internal clock signal, clk_out are external clock after frequency dividing；Div_in is the outside given target frequency dividing ratio for needing to lock, Div_out is the frequency dividing ratio of output control frequency divider, and fre_out is the frequencyband coding of output control voltage controlled oscillator.
Circuit start initial stage, switch S1, S2 are in frequency band correction pattern all in 0 position, circuit.VCO frequencyband coding A fixed value is placed in, Vctrl signal state in which is changed into dibit encoding, controls the jump of frequency dividing ratio by window comparator 1 Become：If Vctrl is higher than upper voltage limit, the downward saltus step of frequency dividing ratio；If Vctrl is less than lower voltage limit, the upward saltus step of frequency dividing ratio.If Vctrl is in the range of window voltage, and frequency dividing ratio is kept, and now thinks that frequency band Vctrl is locked, calibration is completed, and is now corresponded to Frequency dividing ratio be the frequency band feature frequency dividing ratio, preserve in a register, used for follow-up reckoning.Feature frequency dividing ratio initial value Provided according to the simulation result of VCO design phases, reduce the time that lock-out state is found in saltus step.One frequency band locking is completed Afterwards, system carries out the calibration of next frequency band automatically, and until all band calibrations are completed, system enters armed state, Ke Yizheng Often work.Property of the window ranges of window comparator 1 to phaselocked loop in itself is related, and window ranges are generally smaller, still Ensure the reachable frequency of wherein at least one phase-locked loop systems precision.As shown in figure 4, wherein V1.1And V1.2Compare for window The limit of voltage up and down of device 1.
Under normal operating conditions, switch S1, S2 is all in 1 position, and the target frequency that the external world locks as needed is to frequency dividing Than carrying out directly putting number.It is read in the feature frequency dividing ratio control word for each frequency band that calibration phase preserves in this stage, and For judging that frequency band residing for target frequency, AFC system directly put frequencyband coding after calculating to VCO.As shown in figure 4, in the present invention The limit of the voltage up and down V of window comparator 11.1And V1.2Vctrl is locked near median, the feature frequency dividing ratio of frequency band is also about The median of all frequencies on frequency band.The frequency dividing ratio provided according to outside automatically selects the reckoning process of frequency band, exactly judges mesh Frequency is marked apart from which characteristic frequency closer to then frequency band corresponding to this characteristic frequency is then target frequency place frequency band.By In in the design process, leaving enough coincidence scopes between all frequency bands, so this projectional technique can ensure to calculate Preset frequency band coverage goal frequency.In Fig. 4, V2.1And V2.2Limited for the voltage up and down of window comparator 2, window comparator 2 Whether window width is very big, and its effect is that Vctrl is limited in effective scope, while correct for the reckoning to frequency band It is further to be verified.
Two used window comparator circuit structures are identical in the present invention, and the window voltage simply referred to is different.Window Mouth comparator is made up of two analog computing amplifiers, is kept logic circuit with class buffer amplifier and sampling, is sampled by clock Control.In addition, all data processings and computing are all realized by Verilog language.In order to ensure the stabilization of sequential and What is sampled is ageing, and the clock of analogue window comparator and the clock of digital processing part are uniformly provided by numerical portion.Such as Fig. 5 It is shown, it is clock signal waveform, analogue window comparator drives down-sampling, digital processing after a bit of time that is only delayed in clock Partial clock driving numerical portion work.4 tunnel frequency different clocks are reserved during design, it is therefore an objective to can be with test Speed is improved as far as possible in the case where not influenceing sequential.
Fig. 6 .1, Fig. 6 .2, Fig. 7 .1, Fig. 7 .2 are calibration phase simulation result, and mould is carried out to the situation of change of Vctrl signals Intend.When Vctrl is higher than the upper voltage limit of window comparator, frequencyband coding is kept, and frequency dividing ratio is encoded to the less side of frequency dividing ratio To saltus step；When Vctrl is less than lower voltage limit, frequencyband coding is kept, and frequency dividing ratio is encoded to the bigger direction saltus step of frequency dividing ratio；When When Vctrl is in window ranges, it is believed that present band calibration is completed, and frequencyband coding is to next frequency band saltus step.Simulation result table Bright, the switching of frequencyband coding and the saltus step of frequency dividing ratio coding are consistent with design, logically true.Fig. 8 is to put number to automatic reckoning The simulation result of stage frequencyband coding, simulation result show that system, which can be calculated correctly, puts number.(note：For the frequency band of multidigit Coding and frequency dividing ratio coding, in order that result is more directly perceived, show only the numerical value change on the position of feature in simulation result.)
Described above is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims (4)

  1. A kind of 1. automatic band calibration method for making phase-locked loop systems quick lock in, it is characterised in that：Using automatic band calibration System carries out automatic band calibration, and automatic band calibration system is in correction mode at the beginning of starting, is in after the completion of correction mode Mode of operation；
    Course of work during correction mode comprises the following steps：
    1.1) complement mark signal mark=0 is corrected；Frequency band sum is n, i=0, into step 1.2)；
    1.2) frequency band i frequencyband coding is Fre_data [i], and frequency band i feature frequency dividing ratio discreet value is Eva_data [i], is entered Enter step 1.3)；
    1.3) judge whether control voltage signal Vctrl is locked in stop voltage scope by the output valve of correcting window comparator It is interior：If not locking, frequency dividing ratio saltus step is until locking；If locking, into step 1.4)；
    1.4) control voltage signal Vctrl locking time-frequency bands i feature frequency dividing ratio actual value Div_data [i] is preserved, into step It is rapid 1.5)；
    If 1.5) i ＜ n, frequency band i+1 feature frequency dividing ratio discreet value is adjusted according to Eva_data [i] and Div_data [i] Eva_data [i+1], into step 1.6)；If i >=n, into step 1.7)；
    1.6) i=i++, return to step 1.2)；
    1.7) all frequency bands all correct completion, correction complement mark signal mark=1；
    Course of work during mode of operation comprises the following steps：
    2.1) complement mark signal mark=1, the given target frequency dividing ratio Div_in for needing to lock in outside are corrected；
    2.2) the feature frequency dividing ratio actual value Div_data [i] determined when being completed according to correction mode and frequencyband coding Fre_data The relation of [i], using frequencyband coding corresponding with the feature frequency dividing ratio actual value that target frequency dividing ratio Div_in is closest as pre- Put frequencyband coding Fre_data；
    2.3) output valve of operation window comparator judges whether preset frequency bands coding Fre_data is correct：Carried out if incorrect Amendment；Correcting window comparator output valve bound is in the range of operation window comparator output valve bound.
  2. 2. the automatic band calibration method according to claim 1 for making phase-locked loop systems quick lock in, it is characterised in that：Institute State in step 1.3), the method for frequency dividing ratio saltus step is：If control voltage signal Vctrl on correcting window comparator higher than rationing the power supply Pressure, the then downward saltus step of frequency dividing ratio；If control voltage signal Vctrl is less than the lower voltage limit of correcting window comparator, frequency dividing ratio Upward saltus step.
  3. 3. the automatic band calibration method according to claim 1 for making phase-locked loop systems quick lock in, it is characterised in that：Institute State in step 2.3), if preset frequency bands coding is incorrect, be modified, the method for amendment is：Will be with target frequency dividing ratio Div_ Frequencyband coding corresponding to the near feature frequency dividing ratio actual value of in distances time encodes as preset frequency bands, until preset frequency bands coding is just Really.
  4. 4. the automatic band calibration method according to claim 1 for making phase-locked loop systems quick lock in, it is characterised in that：Should Realize that correcting window comparator and operation window comparator pass through by Verilog language in digital processing part in method Analog circuit is realized；In order to ensure the ageing of the stabilization of sequential and sampling, window comparator that analog circuit is realized and The clock for the numerical portion that Verilog language is realized uniformly provides by numerical portion.
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PCT/CN2016/073264 WO2017045338A1 (en) 2015-09-18 2016-02-03 Automatic frequency band calibration method for rapid lock of phase-locked loop system

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CN105119600B (en) * 2015-09-18 2017-11-17 东南大学 A kind of automatic band calibration method for making phase-locked loop systems quick lock in
CN106774629B (en) * 2016-12-09 2019-07-16 建荣半导体（深圳）有限公司 Direct Digital Frequency Synthesizers and its frequency combining method, modulated transmitting device
CN107809238B (en) * 2017-09-27 2021-03-23 珠海格力电器股份有限公司 Phase-locked loop locking detection method based on MCU and MCU
CN113285712B (en) * 2021-04-25 2022-05-17 中国电子科技集团公司第二十九研究所 Multi-stage VCO (voltage controlled oscillator) frequency calibration method applied to phase-locked loop
CN113541683B (en) * 2021-06-08 2022-11-25 西安电子科技大学 Phase-locked loop automatic frequency calibrator based on programmable three-frequency divider
CN116436459B (en) * 2023-06-12 2024-03-01 牛芯半导体(深圳)有限公司 Calibration circuit

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