CN106774629B

CN106774629B - Direct Digital Frequency Synthesizers and its frequency combining method, modulated transmitting device

Info

Publication number: CN106774629B
Application number: CN201611131809.3A
Authority: CN
Inventors: 陈文捷
Original assignee: ZHUHAI HUANGRONG INTEGRATED CIRCUIT TECHNOLOGY Co Ltd; Jian Rong Semiconductor (shenzhen) Co Ltd; Jianrong Integrated Circuit Technology Zhuhai Co Ltd
Current assignee: BUILDWIN INTERNATIONAL (ZHUHAI) LTD.
Priority date: 2016-12-09
Filing date: 2016-12-09
Publication date: 2019-07-16
Anticipated expiration: 2036-12-09
Also published as: CN106774629A

Abstract

The invention discloses Direct Digital Frequency Synthesizers and its frequency combining methods, modulated transmitting device.Power Direct Digital Frequency Synthesis includes: to obtain working clock frequency and frequency control word；According to the maximum length value, working clock frequency and frequency control word of memory, the corresponding target frequency dividing ratio of frequency error, look-up table length and the phase stepping value for meeting preset requirement are determined；Look-up table is generated according to look-up table length and phase stepping value；Trigger signal is generated according to working clock frequency, target frequency dividing ratio；The corresponding amplitude of count value is obtained from look-up table according to the corresponding count value of trigger signal, and digital-to-analogue conversion is carried out to amplitude and exports sine wave signal.By the above-mentioned means, the length of look-up table can be effectively reduced.

Description

Direct Digital Frequency Synthesizers and its frequency combining method, modulated transmitting device

Technical field

The invention belongs to electronic technology field more particularly to a kind of Direct Digital Frequency Synthesizers and its frequency synthesis sides Method, modulated transmitting device.

Background technique

Frequency synthesis technique is one of the key technology that modern communication electronic system realizes high performance index, and many electronics are set Standby function realizes the performance for all depending directly on frequency synthesizer used, for the communication system of continuous frequency conversion, such as wirelessly Local area network (Wireless LAN), Digital Cellular System, electronic warfare system etc., frequency synthesis technique are aobvious in application wherein It obtains particularly important.

The prior art provides a kind of Direct Digital Frequency Synthesizers.The Direct Digital Frequency Synthesizers include: phase-accumulated Device, phase-magnitude conversion module and digital analog converter.In general, phase-magnitude conversion module is a storage sin/cos data Sine lookup table read-only memory (ROM).

Its working principle is that: at work under the driving of clock, phase accumulator carries out linear superposition to frequency control word, obtains To phase angle size, and by phase angle size input phase-amplitude conversion module, phase-magnitude conversion module according to phase angle size into Capable addressing of tabling look-up obtains the corresponding signal amplitude of phase angle size；Finally by this, it inputs digital analog converter, turns through digital analog converter The signal of sinusoidal frequency is got in return, to obtain an output amplitude with the waveform signal of phase change.

Since phase-magnitude conversion module needs 2^DA address stores look-up table, and D is the bit wide of digital analog converter, that is, looks into The size of table and the bit wide exponent function relation of digital analog converter are looked for, so look-up table is very big, committed memory is larger.

Summary of the invention

The present invention provides a kind of Direct Digital Frequency Synthesizers and its frequency combining method, modulated transmitting device, Neng Gouyou Effect reduces the length of look-up table, reduces the memory that look-up table occupies.

To solve the above problems, first aspect present invention provides a kind of power Direct Digital Frequency Synthesis, the direct number Word frequency synthetic method includes:

Obtain working clock frequency and frequency control word；

According to the maximum length value of memory, the working clock frequency and the frequency control word, determines and meet in advance If it is required that the corresponding target frequency dividing ratio of frequency error, look-up table length and phase stepping value；

Look-up table is generated according to the look-up table length and the phase stepping value；

Trigger signal is generated according to the working clock frequency, the target frequency dividing ratio；

The corresponding amplitude of the count value is obtained from the look-up table according to the corresponding count value of the trigger signal, and right The amplitude carries out digital-to-analogue conversion and exports sine wave signal.

To solve the above problems, second aspect of the present invention provides a kind of Direct Digital Frequency Synthesizers, the Direct Digital Frequency synthesizer includes:

Module is obtained, for obtaining working clock frequency and frequency control word；

Determining module, for being controlled according to the maximum length value, the working clock frequency and the frequency of memory Word determines the corresponding target frequency dividing ratio of frequency error, look-up table length and the phase stepping value for meeting preset requirement；

Generation module, for generating look-up table according to the look-up table length and the phase stepping value；

Trigger module, for generating trigger signal according to the working clock frequency, the target frequency dividing ratio；

Frequency synthesis module, for obtaining the counting from the look-up table according to the corresponding count value of the trigger signal It is worth corresponding amplitude, and digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

To solve the above problems, third aspect present invention provides a kind of modulated transmitting device, a kind of FM transmission dress It sets including above-mentioned Direct Digital Frequency Synthesizers.

Above scheme, Direct Digital Frequency Synthesizers are according to the maximum length value, working clock frequency and frequency of memory Rate control word determines the corresponding target frequency dividing ratio of frequency error, look-up table length and the phase stepping value for meeting preset requirement； Look-up table is generated according to look-up table length and phase stepping value；Triggering letter is generated according to working clock frequency, target frequency dividing ratio Number；The corresponding amplitude of count value is obtained from look-up table according to the corresponding count value of trigger signal, and digital-to-analogue conversion is carried out to amplitude Export sine wave signal.Since Direct Digital Frequency Synthesizers are according to the corresponding target point of the frequency error for meeting preset requirement Frequency ratio, look-up tables'implementation direct digital synthesis technique, can precalculate the range value for including in look-up table, effectively reduce frequency Error reduces look-up table institute so as to effectively reduce the look-up table length obtained according to the frequency error of preset requirement is met The memory space of occupancy improves memory usage.

Detailed description of the invention

Fig. 1 is the flow chart of one embodiment of power Direct Digital Frequency Synthesis of the present invention；

Fig. 2 is the flow chart of another embodiment of power Direct Digital Frequency Synthesis of the present invention；

Fig. 3 is the flow chart of power Direct Digital Frequency Synthesis another embodiment of the present invention；

Fig. 4 is the structural schematic diagram of one embodiment of Direct Digital Frequency Synthesizers of the present invention；

Fig. 5 is the structural schematic diagram of another embodiment of Direct Digital Frequency Synthesizers of the present invention；

Fig. 6 is the structural schematic diagram of Direct Digital Frequency Synthesizers another embodiment of the present invention；

Fig. 7 is the structural schematic diagram of the another embodiment of Direct Digital Frequency Synthesizers of the present invention.

Specific embodiment

In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.

Referring to Fig. 1, Fig. 1 is the flow chart of one embodiment of power Direct Digital Frequency Synthesis of the present invention.In the present embodiment Power Direct Digital Frequency Synthesis executing subject be Direct Digital Frequency Synthesizers.Direct Digital frequency in the present embodiment Synthetic method the following steps are included:

S101: working clock frequency and frequency control word are obtained.

Direct Digital Frequency Synthesizers obtain working clock frequency and frequency control word.Working clock frequency can be directly Connect the corresponding frequency of digital frequency synthesizer internal crystal oscillator or its frequency multiplication.Frequency control word is to control the word that frequency occurs (to need The frequency of output), change the content of frequency control word, frequency variation can be changed, it is corresponding that frequency control word can be pilot signal Frequency.

For example, in frequency modulation, (in the sound emission of (Frequency Modulation, FM) solid, stereo coding needs one The pilot signal of 19KHz.Assuming that system on chip has only used the crystal oscillator of a 32.768KHz, and 32 times of frequency multiplication are arrived 1.048576MHz being input in Direct Digital Frequency Synthesizers as work clock；So, working clock frequency is at this time 1.048576MHz frequency control word 19KHz.

S102: it according to the maximum length value of memory, the working clock frequency and the frequency control word, determines full The corresponding target frequency dividing ratio of the frequency error of sufficient preset requirement, look-up table length and phase stepping value.

Direct Digital Frequency Synthesizers obtain memory most after getting working clock frequency, frequency control word Angle value is greatly enhanced, frequency dividing ratio is carried out according to the maximum length value, working clock frequency and frequency control word of memory and phase walks Into the search of value, and corresponding frequency error of all search cycles of each frequency dividing ratio is calculated, determination meets preset requirement The corresponding target frequency dividing ratio of frequency error, look-up table length and phase stepping value.

S103: look-up table is generated according to the look-up table length and the phase stepping value.

Direct Digital Frequency Synthesizers look-up table length and phase stepping value calculate the corresponding amplitude of each storage address Value, to generate look-up table.

S104: trigger signal is generated according to the working clock frequency, the target frequency dividing ratio.

Direct Digital Frequency Synthesizers are according to working clock frequency according to one triggering letter of generation after target frequency dividing ratio frequency dividing Number, and the trigger signal of generation is counted, count value is added 1 by one trigger signal of every generation.Wherein, when count value is equal to It is zeroed after the corresponding look-up table length of target frequency dividing ratio.

S105: the corresponding width of the count value is obtained from the look-up table according to the corresponding count value of the trigger signal Degree, and digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

Direct Digital Frequency Synthesizers obtain count value from the look-up table of production according to the corresponding count value of trigger signal Corresponding amplitude, and digital-to-analogue conversion output sine wave signal is carried out to the amplitude that gets, to realize direct digital synthesis technique.

It is understood that Direct Digital Frequency Synthesizers when determine frequency control word send change when, return step S101 executes S101~S105.

Referring to Fig. 2, Fig. 2 is the flow chart of another embodiment of power Direct Digital Frequency Synthesis of the present invention.The present embodiment In power Direct Digital Frequency Synthesis executing subject be Direct Digital Frequency Synthesizers.Direct Digital frequency as shown in Figure 2 Rate synthetic method the following steps are included:

S201: working clock frequency and frequency control word are obtained.

S202: it is determined and is divided according to the maximum length value of memory, the working clock frequency and the frequency control word The search cycle number of the corresponding search range value of frequency ratio and each frequency dividing ratio.

Direct Digital Frequency Synthesizers obtain the maximum length value of memory, according to the maximum length value of access to memory, work Make clock frequency and frequency control word calculates minimum frequency dividing ratio and maximum frequency dividing ratio, thus according to minimum frequency dividing ratio and maximum Frequency dividing ratio determines the search range of frequency dividing ratio.Wherein, the frequency dividing ratio of initialization is minimum frequency dividing ratio.

Direct Digital Frequency Synthesizers are controlled also according to the maximum length value, working clock frequency and frequency of access to memory Word calculates the number of cycles that each frequency dividing ratio needs to search for.Wherein, Direct Digital Frequency Synthesizers calculate each frequency dividing ratio and need The maximum cycle number of search, and need the number of cycles searched for be initialized as 1 each frequency dividing ratio.

S203: according to described search range and the search cycle number of each frequency dividing ratio, described each point is obtained Corresponding frequency error of all search cycles of frequency ratio.

For example, the search range of Direct Digital Frequency Synthesizers traversal frequency dividing ratio, determines the corresponding needs of each frequency dividing ratio The number of cycles of search, and each frequency dividing ratio corresponding week for needing to search for is traversed according to the search cycle number of each frequency dividing ratio It phase, obtains corresponding frequency error of all search cycles of each frequency dividing ratio, and all is searched from each frequency dividing ratio is corresponding In rope period corresponding frequency error, the frequency error for meeting preset requirement is determined.

It is understood that Direct Digital Frequency Synthesizers can be by from minimum frequency dividing ratio to the sequence time of maximum frequency dividing ratio Go through the search range of frequency dividing ratio, can also by the search range of the order traversal frequency dividing ratio of maximum frequency dividing ratio to minimum frequency dividing ratio, Random search can also be carried out, herein with no restrictions.

Specifically, the search range of frequency dividing ratio is [minimum frequency dividing ratio, maximum frequency dividing ratio], and any two are continuous and adjacent The absolute value of the difference of frequency dividing ratio is 1.

Direct Digital Frequency Synthesizers are corresponding according to the first frequency dividing ratio (can be minimum frequency dividing ratio) and the first frequency dividing ratio The number of cycles searched for of needs, obtain the corresponding all search cycle corresponding frequency errors of the first frequency dividing ratio, and from In the corresponding all search cycle corresponding frequency errors of first frequency dividing ratio, the frequency error for meeting preset requirement is determined.

Direct Digital Frequency Synthesizers have stepped through all search cycles of the first frequency dividing ratio in confirmation, and determine and meet in advance If it is required that frequency error when, according to the second frequency dividing ratio (value of the second frequency dividing ratio on the basis of the first frequency dividing ratio be incremented by 1) with And second frequency dividing ratio it is corresponding need the number of cycles searched for, obtaining the second frequency dividing ratio corresponding all search cycles respectively corresponds to Frequency error, and from the corresponding all search cycle corresponding frequency errors of the second frequency dividing ratio, determine meet it is default It is required that frequency error.

The corresponding all search cycle corresponding frequencies of each frequency dividing ratio are successively obtained one by one according to the method described above to miss Difference, and from the corresponding all search cycle corresponding frequency errors of each frequency dividing ratio, determine the frequency for meeting preset requirement Rate error meets preset requirement until all frequency dividing ratios in the search range that confirmation has got frequency dividing ratio are corresponding Frequency error.

In another embodiment, Direct Digital Frequency Synthesizers can also traverse the search range of frequency dividing ratio, determine each The corresponding number of cycles for needing to search for of frequency dividing ratio, and each frequency dividing ratio pair is traversed according to the search cycle number of each frequency dividing ratio The period that the needs answered are searched for obtains corresponding frequency error of all search cycles of each frequency dividing ratio.

S204: the corresponding target frequency dividing ratio of the frequency error, the mark in target search period for meeting preset requirement are determined Know.

All frequency dividing ratios in search range are corresponding to meet default want to Direct Digital Frequency Synthesizers getting When the frequency error asked, then therefrom determine the corresponding target frequency dividing ratio of frequency error, the target search period for meeting preset requirement Mark.

In another embodiment, when Direct Digital Frequency Synthesizers get each frequency dividing ratio in search range respectively Corresponding frequency error of all search cycles when, determination meets preset requirement from all frequency errors got Frequency error, and record the corresponding target frequency dividing ratio of frequency error, the mark in target search period for meeting preset requirement.

It is understood that preset requirement is used for identification frequency error within an acceptable error range, can be current Frequency error be less than or equal to predeterminated frequency error threshold, being also possible to current frequency error is all frequencies got Error intermediate value is minimum.

The number of the frequency error for meeting preset requirement finally determined can be one, or at least two.When When the number for meeting the frequency error of preset requirement is two, wherein any one it can will be identified as target frequency error, The smallest frequency error of its intermediate value can be identified as target frequency error, herein with no restrictions.Target frequency error is in target Frequency dividing ratio, the mark in target search period correspond.

S205: according to the mark in the target search period calculate the corresponding look-up table length of the target frequency dividing ratio and Phase stepping value.

Direct Digital Frequency Synthesizers are according to the mark in target search period, working clock frequency and frequency control word meter Calculate the corresponding look-up table length of target frequency dividing ratio and phase stepping value.

S206: look-up table is generated according to the look-up table length and the phase stepping value.

S207: trigger signal is generated according to the working clock frequency, the target frequency dividing ratio.

S208: the corresponding width of the count value is obtained from the look-up table according to the corresponding count value of the trigger signal Degree, and digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

It is understood that Direct Digital Frequency Synthesizers when determine frequency control word send change when, return step S201 executes S201~S208.

Above scheme, Direct Digital Frequency Synthesizers are according to the maximum length value, working clock frequency and frequency of memory Rate control word determines the search cycle number of the corresponding search range of frequency dividing ratio and each frequency dividing ratio；According to search range and The search cycle number of each frequency dividing ratio obtains corresponding frequency error of all search cycles of each frequency dividing ratio；It determines Meet the corresponding target frequency dividing ratio of frequency error, the mark in target search period of preset requirement；According to the target search period Mark calculates the corresponding look-up table length of target frequency dividing ratio and phase stepping value；According to look-up table length and phase stepping value Generate look-up table；Trigger signal is generated according to working clock frequency, target frequency dividing ratio；According to the corresponding count value of trigger signal from Look-up table obtains the corresponding amplitude of count value, and carries out digital-to-analogue conversion to amplitude and export sine wave signal.Due to Direct Digital frequency Rate synthesizer is according to the corresponding target frequency dividing ratio of frequency error, the conjunction of look-up tables'implementation Direct Digital frequency for meeting preset requirement At can precalculate the range value for including in look-up table, effectively reduce frequency error, so as to effectively reduce according to meeting The look-up table length that the frequency error of preset requirement obtains reduces the occupied memory space of look-up table, improves memory usage.

Referring to Fig. 3, Fig. 3 is the flow chart of power Direct Digital Frequency Synthesis another embodiment of the present invention.The present embodiment In power Direct Digital Frequency Synthesis executing subject be Direct Digital Frequency Synthesizers.Direct Digital frequency as shown in Figure 3 Rate synthetic method the following steps are included:

S301: working clock frequency and frequency control word are obtained.

Direct Digital Frequency Synthesizers obtain working clock frequency and frequency control word.Working clock frequency can be directly Connect the corresponding frequency of digital frequency synthesizer internal crystal oscillator or its frequency multiplication.Frequency control word is to control the word that frequency occurs (to need The frequency of output), change the content of frequency control word, whether changeable frequency occurs and can be changed frequency variation, frequency control Word can be the corresponding frequency of pilot signal.

S302: it is determined and is divided according to the maximum length value of memory, the working clock frequency and the frequency control word The search cycle number of the corresponding search range value of frequency ratio and each frequency dividing ratio.

Further, step S302 may comprise steps of:

S3021: according to the maximum length value meter of the working clock frequency, the frequency control word and the memory Calculate the corresponding minimum frequency dividing ratio of the frequency control word.

The calculation formula of minimum frequency dividing ratio div_min are as follows: div_min=ceil (fc/ (fo*mem_len))；Wherein, Div_min indicates minimum frequency dividing ratio, ceil (x) indicate for x to be rounded to infinite general orientation (for example, as x=2.1, ceil (x) =3), fc indicates that working clock frequency, fo indicate frequency control word (frequency to be exported), and mem_len indicates memory most Angle value is greatly enhanced, frequency accuracy as desired determines that memory length is bigger, and frequency is more accurate.Empirically data mem_ When len is 64, the frequency error of a ten thousandth can achieve.

Assuming that working clock frequency fc is 1.048576MHz, frequency control word fo=19KHz, the maximum length of memory Value is 128, then, div_min=ceil (1.048576MHz/ (19KHz*128))=1.

S3022: it is corresponding that the frequency control word is calculated according to the working clock frequency and the frequency control word Maximum frequency dividing ratio.

The calculation formula of maximum frequency dividing ratio div_max is div_max=floor (fc/ (fo*2)).Wherein, floor (x) It indicates x being rounded (for example, as x=2.8, floor (x)=2) to infinitely small direction.

Assuming that working clock frequency fc=1.048576MHz, frequency control word fo=19KHz, then maximum frequency dividing ratio Div_max=floor (1.048576MHz/ (19KHz*2))=27.

S3023: the corresponding search model of the frequency dividing ratio is determined according to the minimum frequency dividing ratio and the maximum frequency dividing ratio It encloses.

Direct Digital Frequency Synthesizers when determining minimum frequency dividing ratio and maximum frequency dividing ratio, according to minimum frequency dividing ratio and Maximum frequency dividing ratio determines the corresponding search range of frequency dividing ratio.The corresponding search range of frequency dividing ratio is [minimum frequency dividing ratio, maximum frequency dividing Than].Frequency dividing ratio is positive integer, and the absolute value of the difference between the continuous and adjacent frequency dividing ratio of any two is 1.

S3024: according to the working clock frequency, the maximum length value of the memory, the frequency control word and Search value in the corresponding search range of each frequency dividing ratio calculates the search cycle number of each frequency dividing ratio.

Specifically, according to the search value meter in the working clock frequency, the corresponding search range of each frequency dividing ratio Calculate the corresponding sample rate of search value of each frequency dividing ratio；According to the maximum length value of memory, the search of each frequency dividing ratio It is worth corresponding sample rate, frequency control word calculates the search cycle number of each frequency dividing ratio.

For example, when the search value of current frequency dividing ratio is less than or equal to maximum frequency dividing ratio, Direct Digital Frequency Synthesizers according to Working clock frequency calculates the corresponding sample rate of search value of each frequency dividing ratio, the corresponding sample rate f s=fc/ of current frequency dividing ratio N, N are the search value (current frequency dividing ratio) in the corresponding search range of current frequency dividing ratio.

Work as fc=1.048576MHz, when N is 25, fs=1.048576MHz/25=41.94304KHz.

Calculate the corresponding maximum cycle number for needing to search for of current frequency dividing ratio are as follows:

Max_period=floor (mem_len/ (fs/fo))；Wherein, the corresponding search cycle range of current frequency dividing ratio For [1, max_period], initialization cycle number i=1.

Work as fs=41.94304KHz, when fo=19KHz, mem_len=128, max_period=floor (128/ (41.94304KHz/19KHz))=57.

S303: according to described search range and the search cycle number of each frequency dividing ratio, described each point is obtained Corresponding frequency error of all search cycles of frequency ratio.

Direct Digital Frequency Synthesizers are obtained according to the search range of frequency dividing ratio and the search cycle number of each frequency dividing ratio Current frequency dividing ratio is taken, and frequency dividing ratio is less than or equal to maximum frequency dividing ratio, and the current search period of current frequency dividing ratio before confirmation Value be less than current frequency dividing ratio maximum search number of cycles when, calculate current frequency dividing ratio and the frequency under the current search period Error.

Wherein, the frequency error under current frequency dividing ratio and current period number is calculated, frequency error computing formula can be with are as follows: Freq_delta=abs (fs/ (round (fs/fo*i)/i)-fo)；Wherein, abs (x) refers to the absolute value for taking x, round (x) Refer to and be rounded x to immediate integer, i is the value in current search period, i=1,2 ... ..., max_period (maximum search The number in period).Assuming that i=53, fs=41.94304KHz, fo=19KHz, then,

Freq_delta=abs (41.94304KHz/ (round (41.94304KHz/19KHz*53)/53) -19KHz) ≈ 0.000161367521KHz。

Direct Digital Frequency Synthesizers in the frequency error being calculated under current frequency dividing ratio and current search period, Search cycle (being incremented by 1 on the basis of the current search period) is adjusted, the search cycle pair adjusted under current frequency dividing ratio is calculated The frequency error answered, to calculate corresponding frequency error of all search cycles of current frequency dividing ratio.

Direct Digital Frequency Synthesizers are in maximum cycle of the value greater than current frequency dividing ratio for confirming the search cycle adjusted When number, adjustment frequency dividing ratio (is incremented by 1) on the basis of current frequency dividing ratio, and return step S3024, and execution step S3024~ S303 stops search when confirming that frequency dividing ratio adjusted is greater than maximum frequency dividing ratio.

Direct Digital Frequency Synthesizers execute step S304 when executing the step S303.

S304: the corresponding target frequency dividing ratio of the frequency error, the mark in target search period for meeting preset requirement are determined Know.

Direct Digital Frequency Synthesizers are respectively right in all search cycles for getting all frequency dividing ratios in search range When that answers meets the frequency error of preset requirement, then therefrom determine the target frequency error for meeting preset requirement, record target frequency The corresponding target frequency dividing ratio of rate error, the mark in target search period.

It is understood that Direct Digital Frequency Synthesizers can be to get a frequency error more primary, it can also Be compared again getting all frequency errors, herein with no restrictions.

Further, if step S304 may include: current frequency dividing ratio current search period corresponding frequency error it is small In within the scope of described search, the historical search period of all frequency dividing ratios corresponding historical frequency error, then by the current frequency dividing Than being identified as target frequency dividing ratio, by the mark for being identified as the target search period in the current search period.

For example, Direct Digital Frequency Synthesizers are each in all search cycles for getting all frequency dividing ratios in search range When the self-corresponding frequency error for meeting preset requirement, all frequency errors got are respectively compared, to judge current frequency dividing Whether the current search period corresponding frequency error of ratio is less than in search range, and the historical search period of all frequency dividing ratios is corresponding Historical frequency error.

Direct Digital Frequency Synthesizers are less than in the current search period corresponding frequency error of the current frequency dividing ratio of determination searches Within the scope of rope, when the historical search period of all frequency dividing ratios corresponding historical frequency error, by the current search of current frequency dividing ratio Period, corresponding frequency error was identified as target frequency error, to determine that the smallest frequency of value is missed from the frequency error got Difference is target frequency error, and the corresponding current frequency dividing ratio of target frequency error is identified as target frequency dividing ratio, and target is divided Than the mark for being identified as the target search period in corresponding current search period.

Further, if step S304 can also include: the current search period corresponding frequency error of current frequency dividing ratio Less than predeterminated frequency error threshold, then the current frequency dividing ratio is identified as target frequency dividing ratio, by the mark in the current search period It is identified as the mark in target search period.

For example, Direct Digital Frequency Synthesizers are each in all search cycles for getting all frequency dividing ratios in search range When the self-corresponding frequency error for meeting preset requirement, all frequency errors got are respectively compared, to judge current frequency dividing Whether the current search period corresponding frequency error of ratio is less than predeterminated frequency error threshold.Direct Digital Frequency Synthesizers are true When the current search period corresponding frequency error of settled preceding frequency dividing ratio is less than predeterminated frequency error threshold, current frequency dividing ratio identification For target frequency dividing ratio, by the mark for being identified as the target search period in current search period.

Predeterminated frequency error threshold can be obtained according to the frequency error computing got, can be carried out according to actual needs Setting, herein with no restrictions.When being less than the number of frequency error of predeterminated frequency error threshold is two, will can wherein appoint Meaning one is identified as target frequency error, the smallest frequency error of its intermediate value can also be identified as target frequency error, herein With no restrictions.Target frequency error is corresponded in target frequency dividing ratio, the mark in target search period.

S305: according to the mark in the target search period calculate the corresponding look-up table length of the target frequency dividing ratio and Phase stepping value.

Wherein, look-up table length search_table_len calculation formula are as follows: search_table_len=round (fs/ fo*i)。

Phase stepping phase_step calculation formula are as follows: phase_step=1/ (round (fs/fo*i)/i) * 2*pi, pi It is pi.

Assuming that mark i=53, fs=41.94304KHz, the fo=19KHz in target search period, then,

Search_table_len=round (41.94304KHz/19KHz*53)=117

Phase_step=1/ (round (41.94304KHz/19KHz*53)/53) * 2*3.1415926

=2.8462291931623931623931623931624 (rad)

S306: look-up table is generated according to the look-up table length and the phase stepping value.

Direct Digital Frequency Synthesizers look-up table length and phase stepping value calculate the corresponding sine of each storage address The amplitude of value, to generate look-up table.

According to searching for the phase stepping calculating sine value obtained and being that lookup table memories are written in address by k, need to calculate The quantity of sine value is exactly the look-up table length that search obtains, and sine value calculation formula is as follows, wherein amp=2^(D-1)- 1 is maximum Amplitude is determined by amplitude word length D, wherein search_table_out [k] refers to write-in k-th of address of memory: search_ Table_out [k]=round (amp*sin (phase_step*k))；(k=0,1,2 ... .., (search_table_len- 1))。

Assuming that amplitude word length is 16bit, then amp is 32768-1, then search_table_out [k]=round (32767*sin(2.8462291931623931623931623931624*k))；(k=0,1,2 ... .., (search_ table_len-1))。

As k=0, there is search_table_out [0]=0；Storage address 0 is written；

As k=1, there is search_table_out [1]=9538；Storage address 1 is written；

As k=2, there are search_table_out [2]=- 18251；Storage address 2 is written；

As k=3, there are search_table_out [3]=25382；Storage address 3 is written；

……

As k=116, there are search_table_out [3]=- 9538；Storage address 116 is written.

Direct Digital Frequency Synthesizers will finally be exported with the parameter combination of minimum frequency error, wherein target frequency dividing ratio It is 53；Look-up table length is 117, and above-mentioned sine value is output to memory and forms look-up table, completes look-up table precomputation.

By above-mentioned calculated result it is recognised that the present invention, which has only used 117 look-up tables, can be thus achieved 16Bit or more The precision of high word length is much smaller than in the prior art 2^DA look-up table length, and final frequency error is less than 0.001KHz.

Being scaled percentage is 0.000161367521KHz/19KHz~=8.4931*10^-6。

S307: trigger signal is generated according to the working clock frequency, the target frequency dividing ratio.

S308: the corresponding width of the count value is obtained from the look-up table according to the corresponding count value of the trigger signal Degree, and digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

It is understood that Direct Digital Frequency Synthesizers when determine frequency control word send change when, return step S301 executes S301~S308.

Above scheme, Direct Digital Frequency Synthesizers are according to the maximum length value, working clock frequency and frequency of memory Rate control word determines the search cycle number of the corresponding search range of frequency dividing ratio and each frequency dividing ratio；According to search range and The search cycle number of each frequency dividing ratio obtains corresponding frequency error of all search cycles of each frequency dividing ratio；It determines Meet the corresponding target frequency dividing ratio of frequency error, the mark in target search period of preset requirement；According to the target search period Mark calculates the corresponding look-up table length of target frequency dividing ratio and phase stepping value；According to look-up table length and phase stepping value Generate look-up table；Trigger signal is generated according to working clock frequency, target frequency dividing ratio；According to the corresponding count value of trigger signal from Look-up table obtains the corresponding amplitude of count value, and carries out digital-to-analogue conversion to amplitude and export sine wave signal.Due to Direct Digital frequency Rate synthesizer is according to the corresponding target frequency dividing ratio of frequency error, the conjunction of look-up tables'implementation Direct Digital frequency for meeting preset requirement At frequency error can be effectively reduced, so as to effectively reduce according to meeting the lookup that the frequency error of preset requirement obtains Table length reduces the occupied memory space of look-up table, improves memory usage.

Referring to Fig. 4, Fig. 4 is the structural schematic diagram of one embodiment of Direct Digital Frequency Synthesizers of the present invention.Direct Digital Each module included by frequency synthesizer is used to execute each step in the corresponding embodiment of Fig. 1, referring specifically to Fig. 1 and figure Associated description in 1 corresponding embodiment, does not repeat herein.The Direct Digital Frequency Synthesizers 400 of the present embodiment include obtaining Module 410, determining module 420, generation module 430, trigger module 440 and frequency synthesis module 450.

Module 410 is obtained for obtaining working clock frequency and frequency control word.For example, obtaining module 310 obtains work Make clock frequency and frequency control word.Module 410 is obtained by working clock frequency and frequency control word to determining module 420 It sends, obtains module 410 and send working clock frequency to trigger module 440.

Determining module 420 is used to receive the working clock frequency and frequency control word for obtaining the transmission of module 410, according to depositing The maximum length value of reservoir, the working clock frequency and the frequency control word determine that the frequency for meeting preset requirement is missed The corresponding target frequency dividing ratio of difference, look-up table length and phase stepping value.

For example, determining module 420, which receives, obtains working clock frequency and frequency control word that module 410 is sent, according to The maximum length value of memory, the working clock frequency and the frequency control word determine the frequency for meeting preset requirement The corresponding target frequency dividing ratio of error, look-up table length and phase stepping value.

Determining module 420 sends target frequency dividing ratio to trigger module 440, by look-up table length and it is phase stepping be worth to Generation module 430 is sent.

Generation module 430 is used to receive the look-up table length and phase stepping value of the transmission of determining module 420, according to described Look-up table length and the phase stepping value generate look-up table.

For example, generation module 430 receives the look-up table length and phase stepping value that determining module 420 is sent, according to institute It states look-up table length and the phase stepping value generates look-up table.

Generation module 430 sends look-up table to frequency synthesis module 450.

Trigger module 440 is used to receive the working clock frequency and the transmission of determining module 420 for obtaining that module 410 is sent Target frequency dividing ratio, according to the working clock frequency, the target frequency dividing ratio generate trigger signal.

For example, trigger module 440 receives the working clock frequency and the transmission of determining module 420 for obtaining that module 410 is sent Target frequency dividing ratio, according to the working clock frequency, the target frequency dividing ratio generate trigger signal.Trigger module 440 will touch It signals to send to frequency synthesis module 450.

Trigger signal and generation module 430 of the frequency synthesis module 450 for receiving the transmission of trigger module 440 are sent Look-up table obtains the corresponding amplitude of the count value from the look-up table according to the corresponding count value of the trigger signal, and right The amplitude carries out digital-to-analogue conversion and exports sine wave signal.

For example, frequency synthesis module 450 receives the trigger signal that trigger module 440 is sent and generation module 330 is sent Look-up table, the corresponding amplitude of the count value is obtained from the look-up table according to the corresponding count value of the trigger signal, and Digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

Referring to Fig. 5, Fig. 5 is the structural schematic diagram of another embodiment of Direct Digital Frequency Synthesizers of the present invention.Directly number Each module included by word frequency synthesizer is used to execute each step in the corresponding embodiment of Fig. 2, referring specifically to Fig. 2 and Associated description in the corresponding embodiment of Fig. 2, does not repeat herein.The Direct Digital Frequency Synthesizers 500 of the present embodiment include obtaining Modulus block 510, determining module 520, generation module 530, trigger module 540 and frequency synthesis module 550.Wherein it is determined that mould Block 520 includes the first determining module 521, frequency error acquisition module 522, the second determining module 523, computing module 524.

Module 510 is obtained for obtaining working clock frequency and frequency control word.Module 510 is obtained by work clock frequency Rate and frequency control word are sent to the first determining module 521, and working clock frequency is sent to trigger module 540.

First determining module 521, which is used to receive, obtains working clock frequency and frequency control word that module 510 is sent, root The corresponding search model of frequency dividing ratio is determined according to the maximum length value of memory, the working clock frequency and the frequency control word It encloses and the search cycle number of each frequency dividing ratio.First determining module 521 by the determining corresponding search range of frequency dividing ratio with And the search cycle number of each frequency dividing ratio obtains module 522 to frequency error and sends.

Frequency error obtains the corresponding search range of frequency dividing ratio that module 522 is used to receive the transmission of the first determining module 521 And the search cycle number of each frequency dividing ratio, according to the search cycle number of described search range and each frequency dividing ratio Mesh obtains corresponding frequency error of all search cycles of each frequency dividing ratio.Frequency error, which will obtain module 522, each to be divided Corresponding frequency error of all search cycles of frequency ratio is sent to the second determining module 523.

Second determining module 523 obtains all search for each frequency dividing ratio that module 522 is sent for receiver frequency error Period corresponding frequency error determines that the corresponding target frequency dividing ratio of the frequency error, the target that meet preset requirement are searched The mark in rope period.Second determining module 523 sends target frequency dividing ratio, the mark in target search period to computing module 524.

Computing module 524 is used to receive the target frequency dividing ratio of the second determining module 523 transmission, the mark in target search period Know, the corresponding look-up table length of the target frequency dividing ratio and phase stepping is calculated according to the mark in the target search period Value.Computing module 524 by the corresponding look-up table length of target frequency dividing ratio and it is phase stepping be worth to generation module 530 send.

Generation module 530 is used to receive the corresponding look-up table length of target frequency dividing ratio and phase of the transmission of computing module 524 Position step value generates look-up table according to the look-up table length and the phase stepping value.Generation module 530 divides target The information of ratio is sent to trigger module 540, and look-up table is sent to frequency synthesis module 550.

Trigger module 540 is used to receive the working clock frequency and the transmission of generation module 530 for obtaining that module 510 is sent Target frequency dividing ratio information, according to the working clock frequency, the target frequency dividing ratio generate trigger signal.Trigger module 540 send trigger signal to frequency synthesis module 550.

Frequency synthesis module 550 is used to receive the look-up table of the transmission of generation module 530, receives what trigger module 540 was sent Trigger signal obtains the corresponding amplitude of the count value from the look-up table according to the corresponding count value of the trigger signal, and Digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

Referring to Fig. 6, Fig. 6 is the structural schematic diagram of Direct Digital Frequency Synthesizers another embodiment of the present invention.Directly number Each module included by word frequency synthesizer is used to execute each step in the corresponding embodiment of Fig. 3, referring specifically to Fig. 3 and Associated description in the corresponding embodiment of Fig. 3, does not repeat herein.The Direct Digital Frequency Synthesizers 600 of the present embodiment include: to obtain Modulus block 610, determining module 620, generation module 630, trigger module 640 and frequency synthesis module 650.Wherein, wherein really Cover half block 620 obtains module 622, the second determining module 623, computing module 624 including the first determining module 621, frequency error, First determining module 621 includes computing unit 6211, the first determination unit 6212, the second determination unit 6213.

Module 610 is obtained for obtaining working clock frequency and frequency control word.Module 610 is obtained by work clock frequency Rate and frequency control word are sent to the first determining module 621, and working clock frequency is sent to trigger module 640.

First determining module 621, which is used to receive, obtains working clock frequency and frequency control word that module 610 is sent, root The corresponding search model of frequency dividing ratio is determined according to the maximum length value of memory, the working clock frequency and the frequency control word It encloses and the search cycle number of each frequency dividing ratio.

Further, the first determining module 621 includes:

Computing unit 6211 is used for according to the working clock frequency, the frequency control word and the memory most It greatly enhances angle value and calculates the corresponding minimum frequency dividing ratio of the frequency control word；According to the working clock frequency and the frequency control Word processed calculates the corresponding maximum frequency dividing ratio of the frequency control word；

First determination unit 6212 is used to determine the frequency dividing according to the minimum frequency dividing ratio and the maximum frequency dividing ratio Than corresponding search range；

Second determination unit 6213 is used for the maximum length value, described according to the working clock frequency, the memory Search value in frequency control word and the corresponding search range of each frequency dividing ratio calculates each frequency dividing ratio Search cycle number.

First determining module 621 is by the determining corresponding search range of frequency dividing ratio and the search cycle number of each frequency dividing ratio Mesh obtains module 622 to frequency error and sends.

Frequency error obtains the corresponding search range of frequency dividing ratio that module 622 is used to receive the transmission of the first determining module 621 And the search cycle number of each frequency dividing ratio, according to the search cycle number of described search range and each frequency dividing ratio Mesh obtains corresponding frequency error of all search cycles of each frequency dividing ratio.Frequency error, which will obtain module 622, each to be divided Corresponding frequency error of all search cycles of frequency ratio is sent to the second determining module 623.

Second determining module 623 obtains all search for each frequency dividing ratio that module 622 is sent for receiver frequency error Period corresponding frequency error determines that the corresponding target frequency dividing ratio of the frequency error, the target that meet preset requirement are searched The mark in rope period.Second determining module 623 sends target frequency dividing ratio, the mark in target search period to computing module 624.

Computing module 624 is used to receive the target frequency dividing ratio of the second determining module 623 transmission, the mark in target search period Know, the corresponding look-up table length of the target frequency dividing ratio and phase stepping is calculated according to the mark in the target search period Value.Computing module 624 by the corresponding look-up table length of target frequency dividing ratio and it is phase stepping be worth to generation module 630 send.

Generation module 630 is used to receive the corresponding look-up table length of target frequency dividing ratio and phase of the transmission of computing module 624 Position step value generates look-up table according to the look-up table length and the phase stepping value.Generation module 630 divides target The information of ratio is sent to trigger module 640.

Trigger module 640 is used to receive the information of the target frequency dividing ratio of the transmission of generation module 630, according to the work clock Frequency, the target frequency dividing ratio generate trigger signal.Trigger module 640 sends trigger signal to frequency synthesis module 650.

Frequency synthesis module 650, which is used to receive, obtains working clock frequency and trigger module 640 that module 610 is sent The trigger signal of transmission obtains the corresponding width of the count value from the look-up table according to the corresponding count value of the trigger signal Degree, and digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

Above scheme, Direct Digital Frequency Synthesizers are according to the maximum length value, working clock frequency and frequency of memory Rate control word determines the search cycle number of the corresponding search range of frequency dividing ratio and each frequency dividing ratio；According to search range and The search cycle number of each frequency dividing ratio obtains corresponding frequency error of all search cycles of each frequency dividing ratio；It determines Meet the corresponding target frequency dividing ratio of frequency error, the mark in target search period of preset requirement；According to the target search period Mark calculates the corresponding look-up table length of target frequency dividing ratio and phase stepping value；According to look-up table length and phase stepping value Generate look-up table；Trigger signal is generated according to working clock frequency, target frequency dividing ratio；According to the corresponding count value of trigger signal from Look-up table obtains the corresponding amplitude of count value, and carries out digital-to-analogue conversion to amplitude and export sine wave signal.Due to Direct Digital frequency Rate synthesizer is according to the corresponding target frequency dividing ratio of frequency error, the conjunction of look-up tables'implementation Direct Digital frequency for meeting preset requirement At frequency error can be effectively reduced, can effectively reduce according to meeting the look-up table that the frequency error of preset requirement obtains Length reduces the occupied memory space of look-up table, improves memory usage.

It is the structural schematic diagram of the another embodiment of Direct Digital Frequency Synthesizers of the present invention referring to Fig. 7, Fig. 7.As shown in the figure The present embodiment in Direct Digital Frequency Synthesizers 700 may include: one or more processors 710, it is one or more defeated Enter equipment 720, one or more output equipments 730 and memory 740.Above-mentioned processor 710, input equipment 720, output equipment 730 and memory 740 connected by bus 750.

Memory 740 is for storing program instruction.

The program instruction that processor 710 is used to be stored according to memory 740 executes following operation:

Processor 710 is for obtaining working clock frequency and frequency control word；

Processor 710 is also used to the maximum length value according to memory, the working clock frequency and the frequency control Word processed determines the corresponding target frequency dividing ratio of frequency error, look-up table length and the phase stepping value for meeting preset requirement；

Processor 710 is also used to generate look-up table according to the look-up table length and the phase stepping value；

Processor 710 is also used to generate trigger signal according to the working clock frequency, the target frequency dividing ratio；

Processor 710 is also used to obtain the count value from the look-up table according to the corresponding count value of the trigger signal Corresponding amplitude, and digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

Further, processor 710 is also used to the maximum length value according to memory, the working clock frequency and institute State the search cycle number that frequency control word determines the corresponding search range of frequency dividing ratio and each frequency dividing ratio；And it is used for basis The search cycle number of described search range and each frequency dividing ratio obtains all search cycles of each frequency dividing ratio Corresponding frequency error；And for determining the corresponding target frequency dividing ratio of the frequency error, the mesh that meet preset requirement Mark the mark of search cycle；And the target frequency dividing ratio is corresponding to be looked into for being calculated according to the mark in the target search period Look for table length and phase stepping value.

Further, processor 710 is specifically used for according to the working clock frequency, the frequency control word and described The maximum length value of memory calculates the corresponding minimum frequency dividing ratio of the frequency control word；According to the working clock frequency and The frequency control word calculates the corresponding maximum frequency dividing ratio of the frequency control word；According to the minimum frequency dividing ratio and it is described most Big frequency dividing ratio determines the corresponding search range of the frequency dividing ratio；It is most greatly enhanced according to the working clock frequency, the memory The search value of angle value, the frequency control word and each frequency dividing ratio calculates the search cycle number of each frequency dividing ratio Mesh.

Further, processor 710 is specifically used for being calculated according to the search value of the working clock frequency, each frequency dividing ratio The corresponding sample rate of search value of each frequency dividing ratio；According to the maximum length value of the memory, the sample rate, The frequency control word calculates the search cycle number of each frequency dividing ratio.

Further, if processor 710 is small specifically for the current search period corresponding frequency error of current frequency dividing ratio In within the scope of described search, the historical search period of all frequency dividing ratios corresponding historical frequency error, then by the current frequency dividing Than being identified as target frequency dividing ratio, by the mark for being identified as the target search period in the current search period.

Further, if processor 710 is small specifically for the current search period corresponding frequency error of current frequency dividing ratio In predeterminated frequency error threshold, then the current frequency dividing ratio is identified as target frequency dividing ratio, by the mark in the current search period It is identified as the mark in target search period.

It should be appreciated that in embodiments of the present invention, alleged processor 710 can be central processing unit (Central Processing Unit, CPU), which can also be other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit (Application SpecificIntegrated Circuit, ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic Device, discrete gate or transistor logic, discrete hardware components etc..General processor can be microprocessor or this at Reason device is also possible to any conventional processor etc..

Input equipment 720 may include that Trackpad, fingerprint adopt sensor (for acquiring the finger print information and fingerprint of user Directional information), microphone etc., output equipment 730 may include display (LCD etc.), loudspeaker etc..

The memory 740 may include read-only memory and random access memory, and to processor 510 provide instruction and Data.The a part of of memory 740 can also include nonvolatile RAM.For example, memory 740 can also be deposited Store up the information of device type.

In the specific implementation, processor 710 described in the embodiment of the present invention, input equipment 720, output equipment 730 can It executes described in the first embodiment and second embodiment of power Direct Digital Frequency Synthesis provided in an embodiment of the present invention The implementation of Direct Digital Frequency Synthesizers described in the embodiment of the present invention also can be performed in implementation, no longer superfluous herein It states.

The present invention also provides a kind of modulated transmitting device, modulated transmitting device includes direct described in any of the above-described embodiment Digital frequency synthesizer.Modulated transmitting device includes but is not limited to the frequency modulation (Frequency for being used for stereo coding Modulation, FM) emitter, the pilot signal of stereo coding is 19KHz.

The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.

Claims

1. a kind of power Direct Digital Frequency Synthesis, which is characterized in that the power Direct Digital Frequency Synthesis includes:

Obtain working clock frequency and frequency control word；

Frequency dividing ratio and phase are carried out according to the maximum length value of memory, the working clock frequency and the frequency control word The search of step value, and corresponding frequency error of all search cycles of each frequency dividing ratio is calculated, it determines and meets in advance If it is required that the corresponding target frequency dividing ratio of frequency error, look-up table length and phase stepping value；

The corresponding amplitude of the count value is obtained from the look-up table according to the corresponding count value of the trigger signal, and to described Amplitude carries out digital-to-analogue conversion and exports sine wave signal.

2. power Direct Digital Frequency Synthesis according to claim 1, which is characterized in that the maximum according to memory Length value, the working clock frequency and the frequency control word carry out the search of frequency dividing ratio and phase stepping value, and calculate Corresponding frequency error of all search cycles of each frequency dividing ratio determines that the frequency error for meeting preset requirement is corresponding Target frequency dividing ratio, look-up table length and phase stepping value include:

Determine that frequency dividing ratio is corresponding according to the maximum length value of memory, the working clock frequency and the frequency control word The search cycle number of search range and each frequency dividing ratio；

According to described search range and the search cycle number of each frequency dividing ratio, all of each frequency dividing ratio are obtained Search cycle corresponding frequency error；

Determine the corresponding target frequency dividing ratio of the frequency error, the mark in target search period for meeting preset requirement；

The corresponding look-up table length of the target frequency dividing ratio and phase stepping is calculated according to the mark in the target search period Value.

3. power Direct Digital Frequency Synthesis according to claim 2, which is characterized in that the maximum according to memory Length value, the working clock frequency and the frequency control word determine the corresponding search range of frequency dividing ratio and each frequency dividing The search cycle number of ratio includes:

The frequency is calculated according to the maximum length value of the working clock frequency, the frequency control word and the memory The corresponding minimum frequency dividing ratio of control word；

The corresponding maximum frequency dividing ratio of the frequency control word is calculated according to the working clock frequency and the frequency control word；

The corresponding search range of the frequency dividing ratio is determined according to the minimum frequency dividing ratio and the maximum frequency dividing ratio；

According to the working clock frequency, the maximum length value of the memory, the frequency control word and each point described Search value in the corresponding search range of frequency ratio calculates the search cycle number of each frequency dividing ratio.

4. power Direct Digital Frequency Synthesis according to claim 3, which is characterized in that described according to the work clock Frequency, the maximum length value of the memory, the frequency control word and the corresponding search model of each frequency dividing ratio The search cycle number that search value in enclosing calculates each frequency dividing ratio includes:

It is respectively corresponded to according to the search value that the search value of the working clock frequency, each frequency dividing ratio calculates each frequency dividing ratio Sample rate；

Each frequency dividing ratio is calculated according to the maximum length value of the memory, the sample rate, the frequency control word Search cycle number.

5. according to the described in any item power Direct Digital Frequency Synthesis of claim 2 to 4, which is characterized in that the determination is full The corresponding target frequency dividing ratio of the frequency error of sufficient preset requirement, the mark in target search period include:

If the current search period corresponding frequency error of current frequency dividing ratio is less than within the scope of described search, all frequency dividing ratios are gone through History search cycle corresponding historical frequency error, then be identified as target frequency dividing ratio for the current frequency dividing ratio, currently searches described The mark for being identified as the target search period in rope period.

6. according to the described in any item power Direct Digital Frequency Synthesis of claim 2 to 4, which is characterized in that the determination is full The corresponding target frequency dividing ratio of the frequency error of sufficient preset requirement, the mark in target search period include:

If the current search period corresponding frequency error of current frequency dividing ratio is less than predeterminated frequency error threshold, described currently to divide Frequency ratio is identified as target frequency dividing ratio, by the mark for being identified as the target search period in the current search period.

7. a kind of Direct Digital Frequency Synthesizers, which is characterized in that the Direct Digital Frequency Synthesizers include:

Determining module, for according to the maximum length value, the working clock frequency and the frequency control word of memory into The search of row frequency dividing ratio and phase stepping value, and the corresponding frequency of all search cycles for calculating each frequency dividing ratio is missed Difference determines the corresponding target frequency dividing ratio of frequency error, look-up table length and the phase stepping value for meeting preset requirement；

Frequency synthesis module, for obtaining the count value pair from the look-up table according to the corresponding count value of the trigger signal The amplitude answered, and digital-to-analogue conversion is carried out to the amplitude and exports sine wave signal.

8. Direct Digital Frequency Synthesizers according to claim 7, which is characterized in that the determining module includes:

First determining module, for being controlled according to the maximum length value, the working clock frequency and the frequency of memory Word determines the search cycle number of the corresponding search range of frequency dividing ratio and each frequency dividing ratio；

Frequency error obtains module and obtains for the search cycle number according to described search range and each frequency dividing ratio Take corresponding frequency error of all search cycles of each frequency dividing ratio；

Second determining module, for determining the corresponding target frequency dividing ratio of the frequency error, the target search that meet preset requirement The mark in period；

Computing module, for calculating the corresponding look-up table length of the target frequency dividing ratio according to the mark in the target search period And phase stepping value.

9. Direct Digital Frequency Synthesizers according to claim 8, which is characterized in that first determining module includes:

Computing unit, for the maximum length according to the working clock frequency, the frequency control word and the memory Value calculates the corresponding minimum frequency dividing ratio of the frequency control word；According to the working clock frequency and the frequency control word meter Calculate the corresponding maximum frequency dividing ratio of the frequency control word；

First determination unit, for determining that the frequency dividing ratio is corresponding according to the minimum frequency dividing ratio and the maximum frequency dividing ratio Search range；

Second determination unit, for being controlled according to the maximum length value of the working clock frequency, the memory, the frequency Search value in word and the corresponding search range of each frequency dividing ratio calculates the search cycle of each frequency dividing ratio Number.

10. Direct Digital Frequency Synthesizers according to claim 9, which is characterized in that second determination unit is specific Search value for calculating each frequency dividing ratio according to the search value of the working clock frequency, each frequency dividing ratio respectively corresponds to Sample rate；Each frequency dividing is calculated according to the maximum length value of the memory, the sample rate, the frequency control word The search cycle number of ratio.

11. according to the described in any item Direct Digital Frequency Synthesizers of claim 8 to 10, which is characterized in that described second really If the current search period corresponding frequency error that cover half block is specifically used for current frequency dividing ratio is less than within the scope of described search, own The historical search period of frequency dividing ratio corresponding historical frequency error, then be identified as target frequency dividing ratio for the current frequency dividing ratio, will The mark for being identified as the target search period in the current search period.

12. according to the described in any item Direct Digital Frequency Synthesizers of claim 8 to 10, which is characterized in that described second really If the current search period corresponding frequency error that cover half block is specifically used for current frequency dividing ratio is less than predeterminated frequency error threshold, The current frequency dividing ratio is identified as target frequency dividing ratio, by the mark for being identified as the target search period in the current search period Know.

13. a kind of modulated transmitting device, which is characterized in that the modulated transmitting device includes such as any one of claim 7-12 institute The Direct Digital Frequency Synthesizers stated.