CN101534186A - Digital smoothing circuit and method for utilizing digital smoothing circuit to extract clock from Ethernet signals - Google Patents
Digital smoothing circuit and method for utilizing digital smoothing circuit to extract clock from Ethernet signals Download PDFInfo
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Abstract
The invention relates to a digital smoothing circuit and a method for utilizing the digital smoothing circuit to extract clock from random Ethernet signals. The digital smoothing circuit comprises a bit adjusting circuit and a digital phase-locked loop which comprises a frequency discriminator, a phase discriminator, an adder and a frictional frequency divider. The invention adopts a method with juxtaposition of frequency discrimination and phase discrimination, simultaneously combines a digital filter with the method, adopts the frictional frequency divider to form a digital control vibrator, and restores E1 clock signals therefrom. The invention solves the technical problem that the existing digital smoothing circuit has complex structure, and has the advantages of simple structure and easy realization; an ASIC circuit designed by the method has reliable operation and jitter index thereof meets relevant ITU-T standard by experimental verification.
Description
Technical field
The present invention relates to a kind of digital smoothness circuit and utilize this digital smoothness circuit from ethernet signal at random, to extract the method for clock.
Background technology
In IP-based New Generation of Communication, in order to realize multi-service transmission,,, make it become the too packet of net bag real time business (TDM business) processings of packing at transmitting terminal, transmit then; At receiving terminal, in order to reply original T DM business, data are added up and jitter elimination, thus the timing information of acquisition code stream.The basic principle of jitter elimination is exactly the principle of digital phase-locked loop; Utilize PHASE-LOCKED LOOP PLL TECHNIQUE to realize that quantification, digital filtering and timing to the incoming timing signal are comprehensive.Traditional digitlization theory here shows as simply and rounds, and what circuit was often corresponding is the pulse of handling up, and is the form of counter.
In the TDMoIP system, at transmitting terminal, the signal that needs to send is the E1 signal of standard, in order in Ethernet system, to transmit, the E1 signal is split, encapsulates, make its Ethernet bag that becomes fixed size, the timing information in the E1 signal is originally all lost; Do not contain any timing information in the signal that receiving terminal is received, the shake of data also becomes at random, and this just need will carry out special processing at receiving terminal, could reply the clock of E1 signal.Because ethernet signal is random signal, at first at random ethernet signal is carried out statistical disposition, obtain the fundamental frequency of signal, be benchmark with this frequency then, carry out digital smoothness; Traditional digital smoothness circuit can be divided into two classes; One class is to be made of the digital phase-locked loop that bit is adjusted circuit and Medium-bandwidth, and another kind of is to be made of a phase-locked loop, but the smaller bandwidth of phase-locked loop.But such digital smoothness circuit structure is more complicated all.
Summary of the invention
The object of the invention provides a kind of digital smoothness circuit and method that realizes extracting clock from ethernet signal, and it has solved existing digital smoothness circuit structure complicated technology problem.
Technical solution of the present invention is:
A kind of digital smoothness circuit of realizing from ethernet signal extracting clock comprises that bit adjusts the digital phase-locked loop of circuit and Medium-bandwidth, and described bit is adjusted circuit and is made up of multimode counter and data storage; Described multimode counter comprises first counter 1 and second counter 2; Its special character is that described digital phase-locked loop comprises frequency discriminator FD, phase discriminator PD, adder 3 and decimal frequency divider; The output of described first counter 1 and second counter 2 and phase demodulation control signal vd link to each other with the input of frequency discriminator PD respectively; The output of described phase demodulation control signal vd and decimal frequency divider links to each other with the input of phase discriminator FD respectively; The output of described frequency discriminator FD and phase discriminator PD links to each other with the input of adder 3 respectively; The output of described adder 3 links to each other with the input of decimal frequency divider respectively.
Above-mentioned decimal frequency divider comprises controller 4, first frequency divider 5, second frequency divider 6 and selector MUX; The output of described adder 3 links to each other with the input of controller 4, and the output of described controller 4 links to each other with the control end of selector MUX; The input of described first frequency divider 5 and second frequency divider 6 connects reference clock signal respectively, and its output links to each other with the input of selector MUX respectively.
Above-mentioned controller 4 is made of serial adder.
A kind of method that realizes from ethernet signal, extracting clock, it may further comprise the steps:
1] first counter 1 and second counter 2 are respectively to the input signal f of ethernet signal
InWith output signal f
OutCount;
2] count results and phase demodulation control signal vd send into frequency discriminator FD respectively, frequency discriminator FD output frequency difference f
dPhase discriminator PD utilizes high-frequency clock that output signal and the differing of phase demodulation control signal vd of selector MUX are counted, and output differs p
d
3] adder 3 produces the control signal of frequency divider to the result of frequency discriminator FD and phase discriminator PD and constant addition;
4] control signal of generation obtained frequency dividing ratio after frequency divider was handled according to adder 3, sent into decimal frequency divider;
5] the output signal f of decimal frequency divider output Ethernet
Out
The concrete steps that above-mentioned frequency divider is sent frequency dividing ratio into decimal frequency divider are: controller 4 is according to the output signal filter of adder 3, obtain frequency dividing ratio, and frequency dividing ratio sent into selector MUX, selector MUX is according to frequency dividing ratio, the frequency of first frequency divider 5 and second frequency divider 6 is selected and adjusted, the output signal f of output Ethernet
Out
The present invention has following advantage:
1, the present invention proposes a kind of digital smoothness device that can be level and smooth, wherein comprise the second order digital phase-locked loop the E1 tributary signal, simple in structure, be easy to realize, especially be fit to ASIC and realize, with this method ASIC design circuit, reliable, and the experiment proved that the shake index meets relevant ITU-T standard.
2, the present invention adopts frequency discrimination, phase demodulation and puts method, simultaneously digital filter is incorporated wherein, adopts decimal frequency divider to constitute digital controlled oscillator, therefrom recovers the E1 clock signal.
3, the present invention elongates the variation of the frequency of output stream in time, is convenient to the design of digital phase-locked loop.
Description of drawings
Fig. 1 is a circuit theory schematic diagram of the present invention;
Wherein: 1-the first counter, 2-the second counter, 3-adder, 4-controller, 5-the first frequency divider, 6-the second frequency divider, FD-frequency discriminator, PD-phase discriminator, MUX-selector, f
Out-output signal, f
In-input signal, vd-phase demodulation control signal, f
0-reference clock, filter-adder output signal, f
dThe frequency difference of-input signal and output signal, p
dDiffering of-input signal and output signal.
Embodiment
Digital smoothness circuit of the present invention comprises that bit adjusts the digital phase-locked loop of circuit and Medium-bandwidth, and bit is adjusted circuit and is made up of multimode counter and data storage; The multimode counter comprises first counter and second counter; Digital phase-locked loop comprises frequency discriminator, phase discriminator, adder and decimal frequency divider; The output of first counter and second counter and phase demodulation control signal link to each other with the input of frequency discriminator respectively; The output of phase demodulation control signal and decimal frequency divider links to each other with the input of phase discriminator respectively; The output of frequency discriminator and phase discriminator links to each other with the input of adder respectively; The output of adder links to each other with the input of decimal frequency divider respectively.Decimal frequency divider comprises controller, first frequency divider, second frequency divider and selector; The output of adder links to each other with the input of controller, and the output of controller links to each other with the control end of selector; The input of first frequency divider and second frequency divider connects reference clock signal respectively, and its output links to each other with the input of selector MUX respectively; Controller is according to the control signal of input signal generation to first frequency divider and the output of second frequency divider, and controller is made of serial adder.
A kind of method that realizes from ethernet signal, extracting clock, may further comprise the steps: first counter and second counter are counted the input signal and the output signal of ethernet signal respectively; Count results and phase demodulation control signal are sent into frequency discriminator respectively, frequency discriminator output frequency difference; Phase discriminator utilizes high-frequency clock that the output signal and the differing of phase demodulation control signal of selector are counted, and output differs; Adder produces the control signal of controller to the result of frequency discriminator and phase discriminator and constant addition; The control signal that controller is handled the back generation according to adder obtains frequency dividing ratio, sends into selector; Selector is according to frequency dividing ratio, and the frequency of first frequency divider and second frequency divider is selected and adjusted the output signal of output Ethernet.
The principle of the invention:
The present invention is directed to data structure by Ethernet transmission E1 signal, designed a kind of all-digital phase-locked loop, adopted frequency discrimination, phase demodulation and put method, simultaneously digital filter has been incorporated wherein, adopt decimal frequency divider to constitute digital controlled oscillator, therefrom recover the E1 clock signal.Confirm to have reached designing requirement through hardware experiments, this circuit structure is simple, is easy to be integrated among the ASIC go, and stronger practicality is arranged, and is easy to utilize.
The present invention adopts the digital phase-locked loop by bit adjustment circuit and Medium-bandwidth to constitute the digital smoothness circuit, and bit is adjusted circuit and is made up of multimode counter and data storage; The multimode counter determines to add or detain the frequency of pulse according to the state of data buffer FIFO on data flow, then this information is deposited in data storage, is implemented in to add the button pulse on the data flow, and the variation of the frequency of output stream is elongated in time.
The present invention is a direct processing formula phase-locked loop, first counter and second counter are counted the read-write clock pulse respectively, subtracter, the output frequency difference, digital phase discriminator is a counter, count differing with high-frequency clock, the effect of adder is the result of frequency discrimination and phase demodulation and constant addition, produces the control signal of controller, and controller is to be made of serial adder; First frequency divider and second frequency divider are M and M+1 frequency divider, and they and controller, selector constitute a frequency divider that contains decimal together, and the frequency dividing ratio of frequency divider is the result by frequency discrimination and phase demodulation, handle the control signal of back generation through adder and determine.
Because adjusting circuit, digital phase-locked loop and bit constitute digital Jitter Attenuation device together, be used for decaying and transmit the shake that the E1 signal causes by Ethernet, the bit is here adjusted circuit and just is equivalent to a controlled low pass filter, according to designing requirement, bit is adjusted the output of circuit, be being input as of phase-locked loop: at first Ethernet data is added up, determine the basic rate of E1 signal, then the data that are higher or lower than basic rate are carried out the bit adjustment, the speed that bit is adjusted is determined by adaptive algorithm.
First counter is identical cycle counter with second counter, just initial value is inequality, its function is equivalent to that the past input signal is carried out infinite time and adds up, they and frequency discriminator, phase discriminator, adder are finished the effect of frequency discrimination, phase demodulation jointly, the function that also contains filter simultaneously that is to say that a frequency discrimination, identified result carried out digital filtering.The phase demodulation control signal is finished the value moment to frequency discrimination, identified result, in fact plays a quantized interval, and it should be counted with touching of phase discriminator definite integer ratio relation.Adder the effect here is the result of frequency discrimination, phase demodulation and puts and a constant addition that it is successive to play a circuit.In fact, signal has just really been finished frequency discrimination, phase demodulation effect through after the adder.
Claims (5)
1, a kind of digital smoothness circuit of realizing from ethernet signal extracting clock comprises that bit adjusts the digital phase-locked loop of circuit and Medium-bandwidth, and described bit is adjusted circuit and is made up of multimode counter and data storage; Described multimode counter comprises first counter (1) and second counter (2); It is characterized in that: described digital phase-locked loop comprises frequency discriminator (FD), phase discriminator (PD), adder (3) and decimal frequency divider; The output of described first counter (1) and second counter (2) and phase demodulation control signal (vd) link to each other with the input of frequency discriminator (PD) respectively; The output of described phase demodulation control signal (vd) and decimal frequency divider links to each other with the input of phase discriminator (FD) respectively; The output of described frequency discriminator (FD) and phase discriminator (PD) links to each other with the input of adder (3) respectively; The output of described adder (3) links to each other with the input of decimal frequency divider respectively.
2, the digital smoothness circuit of clock is extracted in realization according to claim 1 from ethernet signal, it is characterized in that: described decimal frequency divider comprises controller (4), first frequency divider (5), second frequency divider (6) and selector (MUX); The output of described adder (3) links to each other with the input of controller (4), and the output of described controller (4) links to each other with the control end of selector (MUX); The input of described first frequency divider (5) and second frequency divider (6) connects reference clock signal (f0) respectively, and its output links to each other with the input of selector (MUX) respectively.
3, digital smoothness circuit according to claim 2 is characterized in that: described controller (4) is made of serial adder.
4, a kind of method that realizes from ethernet signal, extracting clock, it is characterized in that: it may further comprise the steps:
1] first counter (1) and second counter (2) are respectively to the input signal (f of ethernet signal
In) and output signal (f
Out) count;
2] count results and phase demodulation control signal (vd) are sent into frequency discriminator (FD) respectively, frequency discriminator (FD) output frequency difference (f
d); Phase discriminator (PD) utilizes high-frequency clock that the output signal and the differing of phase demodulation control signal (vd) of selector (MUX) are counted, and output differs (p
d);
3] adder (3) produces the control signal of frequency divider to the result and the constant addition of frequency discriminator (FD) and phase discriminator (PD);
4] control signal of generation obtained frequency dividing ratio after frequency divider was handled according to adder (3), sent into decimal frequency divider;
5] output signal (f of decimal frequency divider output Ethernet
Out).
5, the method for clock is extracted in realization according to claim 4 from ethernet signal, it is characterized in that: the concrete steps that described frequency divider is sent frequency dividing ratio into decimal frequency divider are:
Described decimal frequency divider comprises controller (4), first frequency divider (5), second frequency divider (6) and selector (MUX); Described controller (4) is according to the output signal (filter) of adder (3), obtain frequency dividing ratio, and frequency dividing ratio sent into selector (MUX), selector (MUX) is according to frequency dividing ratio, the frequency of first frequency divider (5) and second frequency divider (6) is selected and adjusted, the output signal (f of output Ethernet
Out).
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|---|---|---|---|
| CN200810017670.9A CN101534186B (en) | 2008-03-10 | 2008-03-10 | Digital smoothing circuit and method for utilizing digital smoothing circuit to extract clock from Ethernet signals |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860415A (en) * | 2010-05-18 | 2010-10-13 | 中国电子科技集团公司第五十四研究所 | Blind identification method for coding parameters of extended Golay code of error-tolerant code |
| CN102088285A (en) * | 2009-12-04 | 2011-06-08 | Nxp股份有限公司 | Clock signal generator |
| CN102104378B (en) * | 2009-12-18 | 2013-01-02 | 中国科学院微电子研究所 | Locking detection method and device for ADPLL (All Digital Phase-Locked Loop) |
| CN108923782A (en) * | 2018-07-19 | 2018-11-30 | 深圳大学 | A kind of all-digital phase-locked loop and its quick phase-lock technique |
| CN110138488A (en) * | 2013-02-22 | 2019-08-16 | 瑞典爱立信有限公司 | The pluggable transceiver and its synchronous method of time synchronization |
| CN117254805A (en) * | 2023-11-20 | 2023-12-19 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079630B (en) * | 2006-05-23 | 2010-05-12 | 中兴通讯股份有限公司 | A digital phase lock loop device for smooth switching of clock phase and its method |
-
2008
- 2008-03-10 CN CN200810017670.9A patent/CN101534186B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088285A (en) * | 2009-12-04 | 2011-06-08 | Nxp股份有限公司 | Clock signal generator |
| CN102104378B (en) * | 2009-12-18 | 2013-01-02 | 中国科学院微电子研究所 | Locking detection method and device for ADPLL (All Digital Phase-Locked Loop) |
| CN101860415A (en) * | 2010-05-18 | 2010-10-13 | 中国电子科技集团公司第五十四研究所 | Blind identification method for coding parameters of extended Golay code of error-tolerant code |
| CN110138488A (en) * | 2013-02-22 | 2019-08-16 | 瑞典爱立信有限公司 | The pluggable transceiver and its synchronous method of time synchronization |
| CN108923782A (en) * | 2018-07-19 | 2018-11-30 | 深圳大学 | A kind of all-digital phase-locked loop and its quick phase-lock technique |
| CN108923782B (en) * | 2018-07-19 | 2021-09-07 | 深圳大学 | All-digital phase-locked loop and rapid phase locking method thereof |
| CN117254805A (en) * | 2023-11-20 | 2023-12-19 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
| CN117254805B (en) * | 2023-11-20 | 2024-05-28 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
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Granted publication date: 20140521 |