CN102104378B - Locking detection method and device for ADPLL (All Digital Phase-Locked Loop) - Google Patents
Locking detection method and device for ADPLL (All Digital Phase-Locked Loop) Download PDFInfo
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Abstract
The invention provides a locking detection method for an ADPLL (All Digital Phase-Locked Loop). The locking detection method for the ADPLL comprises the following steps of: recording the phase error signal of the ADPLL or the control words of a digital control oscillator in a register array when the ADPLL enters a dynamic locking state; counting the value of each register in the register array; counting the unequal numbers of the register array, wherein the unequal numbers equal to zero when the values in the register array are fully equal, or else, the equal numbers equal to col(1,m)*col(1,n); and generating a locking signal according to the unequal numbers to confirm whether the ADPLL is locked, wherein the value in each register of the register array is a first value or a second value when the values in the register array are not fully equal, m and n are positive integers, m presents a register number when the values of the registers are a first value, and n presents a register number when the values of the registers are a second value. The invention also provides a locking detection device for the ADPLL. By means of the locking detection method and device provided by the invention, the locking of a PLL (Phase-Locked Loop) can be detected.
Description
Technical field
The present invention relates to phaselocked loop and use, more specifically, relate to lock detecting method and device for all-digital phase-locked loop.
Background technology
Phaselocked loop (phase-locked loop) is and frame synchronization synchronous for the row that improves television receiver at first, to improve antijamming capability.Later stage the 1950's, phaselocked loop was used to the tracking of space flight target, telemetry and telecommand along with the development of space technology.The beginning of the sixties, phaselocked loop was used more and more wider along with the development of digital communication system, such as extracting reference carrier, set up bit synchronization etc. for coherent demodulation.FM signal phase-locked frequency discriminator with thresholding extended capability also grows up at the beginning of the sixties.Aspect electronic device, phaselocked loop has played vital role in the instruments such as frequency synthesizer and phasometer.
Phaselocked loop makes frequency stabilization and is often utilized in radio transmission.Phaselocked loop mainly comprises voltage controlled oscillator VCO and PLL IC, signal of voltage controlled oscillator output, and the part of this signal is output as output signal, and another part then carries out the phase bit comparison by carrying out frequency division with the local oscillation signal that PLL IC produces.Constant for holding frequency, require phase differential not change, if phase differential changes, then the output voltage of the voltage output end of PLL IC will change, thus the Control of Voltage VCO to change until phase differential recovers, thereby reaches the purpose of frequency locking.Phase-locked loop circuit is to make the frequency of controlled oscillator and phase place all keeps determining relation with input signal closed loop electronic circuit.
Phaselocked loop also comprises phase detector, loop filter.Phase detector is used for differentiating the phase differential between input signal Ui and the output signal U o, and output error voltage Ud.Noise and Interference composition among the Ud is by the loop filter filtering of low pass character, thus the control voltage U c of formation voltage controlled oscillator.Uc is applied in voltage controlled oscillator, thereby the output oscillation frequency f of voltage controlled oscillator is pulled to loop input signal frequency f i, and when the two was equal, loop was locked, was called into lock.The direct-current control voltage of keeping locking is provided by phase detector, so remains with certain phase differential between two input signals of phase detector.
In recent years because the advantage of the aspects such as fast-developing and integrated and cost of digital technology so that integrated circuit be digitized into a large focus for current integrated circuit development.Digital phase-locked loop is a kind of novel phase-locked loop structures that development in recent years is got up, and is good by each large-scale commerce company because it has a lot of advantages.TI company with the radio frequency R﹠D team headed by the staszewski at the C035 of TI processing line (interconnection material:copper, minimum metal pitch:0.35um, transistor nominal voltage:1.5V, L drawn:0.11um, L effective:0.08um, gate oxide:29A, substrate resistivity:50) realized all-digital phase-locked loop (ADPLL) on, again expand to the transceiver architecture of FMAM, and be successfully applied in the realization of the agreements such as BLUETOOTH and EDGE thereafter.All-digital phase-locked loop was integrated into again among the C54X series Hydra DSP of TI afterwards.Ching-Chen Chung, the people such as Chen-Yi Lee have proposed a kind of all-digital phase-locked loop structure for generation of high-speed clock signal in 2003 at JSSC, this phaselocked loop adopts 0.3 μ m CMOS technique to realize, operating frequency range is 45MHz ~ 510MHz, the Pk-Pk shake of output signal is shaken less than 22ps less than 70ps, RMS, circuit power consumption is 100mW, and chip area is 0.71mm
2Robert Bogdon, the people such as John L.Wallberg proposed a kind of all-digital phase-locked loop structure that is applied on the mobile phone in 2005 at JSSC, this structure adopts the 90nm digital CMOS process to realize, centre frequency is 824.2MHz, in-band phase noise for-the 93dBc/Hz(loop bandwidth is 40KHz), be with outer phase place noise to be-122dBc/Hz 400KHz; Volodymyr Kratyuk, the people such as Pavan Kumar Hanumolu proposed a kind of digital phase-locked loop structure with wide following range in 2007 at IEEE CICC, this structure adopts 0.13 μ m CMOS technique to realize, operating frequency range is 0.6GHz～2GHz, RMS is dithered as 13.1ps@1.6GHz, circuit power consumption is 15.7mW, and chip area is 0.27mm
2
Number lock pick-up unit (LD, lock detector) is the Important Circuit module of digital phase-locked loop (DPLL, digital phase locked loop), also is the design difficulty of whole phaselocked loop and transceiver.At present, all-digital phase-locked loop can not well be detected when locking.
Summary of the invention
According to an aspect of the present invention, a kind of lock detecting method for all-digital phase-locked loop is provided, may further comprise the steps: when all-digital phase-locked loop enters dynamic lock-out state, phase error signal or the numerically-controlled oscillator control word of all-digital phase-locked loop are recorded in the register array, and register array consists of first-in first-out register; Value in the statistic registers array in each register; The unequal number of counter register array, wherein, when the value in the register array equated entirely, unequal number equaled 0, if the value in the described register array is respectively the first value or the second value, unequal number equals col(1, m) * col(1, n); And generate locking signals according to unequal number, determining whether all-digital phase-locked loop locks, and wherein, m, n are positive integers, m represents that its value is that the register of the first value is quantity, and n represents that its value is that the register of the second value is quantity.
Preferably, the first value is close with the second value.
Preferably, register array comprises 7 registers.
According to another aspect of the present invention, a kind of lock detection device for all-digital phase-locked loop is provided, this device comprises: record cell, be used for when all-digital phase-locked loop enters dynamic lock-out state, phase error signal or the numerically-controlled oscillator control word of all-digital phase-locked loop are recorded in the register array, and register array consists of first-in first-out register; Statistic unit, the value in the statistic registers array in each register; Computing unit, the unequal number of counter register array, wherein, when the value in the register array equated entirely, unequal number equaled 0, if the value in the described register array is respectively the first value or the second value, unequal number equals col(1, m) * col(1, n); And determining unit, generate locking signals according to unequal number, determining whether all-digital phase-locked loop locks, and wherein, m, n are positive integers, m represents that its value is that the register of the first value is quantity, and n represents that its value is that the register of the second value is quantity.
Preferably, the first value is close with the second value.
Preferably, register array comprises 7 registers.
Lock detection device available standards digital units of the present invention is realized.Thereby utilizing this lock detection device of the present invention and method can identify the behavior pattern of all-digital phase-locked loop when loop-locking can realize the locking of phaselocked loop is detected.
Other features and advantages of the present invention will be set forth in the following description, and, partly from instructions, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the instructions of writing, claims and accompanying drawing.
Description of drawings
Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is further described in detail.
Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of the application's a part, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not consist of improper restriction of the present invention.In the accompanying drawings:
Fig. 1 is the lock detecting method process flow diagram according to the embodiment of the invention;
Fig. 2 is the lock detection device schematic diagram according to the embodiment of the invention; And
Fig. 3 is a kind of schematic diagram of multi-mode staged locking scheme.
Embodiment
Describe embodiments of the invention in detail below in conjunction with accompanying drawing.
With reference to Fig. 1, the lock detecting method that is used for all-digital phase-locked loop may further comprise the steps:
Step S102 when all-digital phase-locked loop enters dynamic lock-out state, is recorded in phase error signal or the numerically-controlled oscillator control word of all-digital phase-locked loop in the register array, and register array consists of first-in first-out register;
Step S104, the value in the statistic registers array in each register;
Step S106, the unequal number of counter register array, wherein, when the value in the register array equated entirely, unequal number equaled 0, otherwise unequal number equals col(1, m) * col(1, n); And
Step S108 generates locking signal according to unequal number, whether locks with definite all-digital phase-locked loop,
Wherein, when the value in the register array did not equate entirely, the value in each register of register array was the first value or the second value, and wherein, m, n are positive integers, m represents that its value is the quantity of the register of the first value, and n represents that its value is the quantity of the register of the second value.
Preferably, the first value is close with the second value.
Preferably, register array comprises 7 registers.
With reference to Fig. 2, the lock detection device that is used for all-digital phase-locked loop comprises:
Record cell 202 is used for when all-digital phase-locked loop enters dynamic lock-out state, and phase error signal or the numerically-controlled oscillator control word of all-digital phase-locked loop is recorded in the register array, and register array consists of first-in first-out register;
Statistic unit 204 is used for the value in each register of statistic registers array;
Computing unit 206, for the unequal number of counter register array, wherein, when the value in the register array equated entirely, unequal number equaled 0, otherwise equal numbers equals col(1, m) * col(1, n); And
Determining unit 208, be used for generating locking signal according to unequal number, to determine whether all-digital phase-locked loop locks, wherein, when the value in the register array does not equate entirely, value in each register of register array is the first value or the second value, and wherein, m, n are positive integers, m represents that its value is that the register of the first value is quantity, and n represents that its value is that the register of the second value is quantity.
Preferably, the first value is close with the second value.
Preferably, register array comprises 7 registers.
Below with reference to Fig. 3 an alternative embodiment of the invention is described.
Fig. 3 is a kind of schematic diagram of multi-mode staged locking scheme.Minutes 3 steps of locking process finish, and power on that what initially carry out is the phase-locked process of PVT, next are the phase-locked processes of acquisition, next are the phase-locked process of tracking again.
In the present embodiment, one group of register consists of the FIFO of a first in first out, and FIFO has recorded the phase error of all-digital phase-locked loop or the content of control word register.The length of supposing register among the FIFO is that 7 register intermediate values are respectively F1, F2, F3, F4, F5, F6 and F7 among 7, the FIFO.The value in each register is changing always among the FIFO in the dynamic locking process of phaselocked loop.When digital phase-locked loop during in certain locking, the value in each register can equal certain standard value or do the arest neighbors fluctuation around certain standard value in stage.At this moment the value among the FIFO or complete equating, or be certain two neighbour's number.Can draw unequal number (NumofNotEqual) by the value in each register relatively, wherein:
When the value in each register among the FIFO equated entirely, unequal number was 0;
When the value in each register among the FIFO is respectively two neighbours' number (a, b), utilize col(m, n) function is determined unequal number, wherein col(m, n) the function representation number of combinations of from n thing, getting m thing, m, n is positive integer, and m is not more than n.In this embodiment, can followingly determine unequal number for the value in each register:
1a6b(namely, the value among the FIFO in 7 registers comprises 1 a, 6 b), its unequal number is col(1,1) * col(1,6)=6;
2a5b(namely, the value among the FIFO in 7 registers comprises 2 a, 5 b), its unequal number is col(1,2) * col(1,5)=10;
3a4b(namely, the value among the FIFO in the register comprises 3 a, 4 b), its unequal number is col(1,3) * col(1,4)=12;
Because a, b is reciprocity symmetry (because combinatorial operation is centrosymmetric) for unequal number, so 4a3b, 5a2b etc. can be easy to draw.
Just can the lock-out state of loop be detected by unequal number.This part function is realized by the CL module among Fig. 4.The CL module judges by utilizing unequal number decoding to generate locking signal whether phaselocked loop locks.
Lock detection device available standards digital units of the present invention is realized.Thereby utilizing this lock detection device of the present invention and method can identify the behavior pattern of all-digital phase-locked loop when loop-locking can realize the locking of phaselocked loop is detected.
Be the preferred embodiments of the present invention only below, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a lock detecting method that is used for all-digital phase-locked loop is characterized in that, comprising:
When described all-digital phase-locked loop enters dynamic lock-out state, phase error signal or the numerically-controlled oscillator control word of described all-digital phase-locked loop is recorded in the register array, described register array consists of first-in first-out register;
Add up the value in each register in the described register array;
Calculate the unequal number of described register array, wherein, when the value in the described register array equates entirely, described unequal number equals 0, if the value in the described register array is respectively the first value or the second value, utilizes col(m, n) function is determined unequal number, wherein col(m, n) the function representation number of combinations of from n thing, getting m thing, m, n is positive integer, and m is not more than n, and described unequal number equals col(1, m) * col(1, n); And
Generate locking signal according to described unequal number, whether lock with definite described all-digital phase-locked loop,
Wherein, m represents that its value is the quantity of the register of described the first value, and n represents that its value is the quantity of the register of described the second value.
2. the lock detecting method for all-digital phase-locked loop according to claim 1 is characterized in that, described the first value is close with described the second value.
3. the lock detecting method for all-digital phase-locked loop according to claim 2 is characterized in that, described register array comprises 7 registers.
4. a lock detection device that is used for all-digital phase-locked loop is characterized in that, comprising:
Record cell is used for when described all-digital phase-locked loop enters dynamic lock-out state, and phase error signal or the numerically-controlled oscillator control word of described all-digital phase-locked loop is recorded in the register array, and described register array consists of first-in first-out register;
Statistic unit is added up the value in each register in the described register array;
Computing unit calculates the unequal number of described register array, wherein, when the value in the described register array equated entirely, described unequal number equaled 0, if the value in the described register array is respectively the first value or the second value, utilizing col(m, n) function determines unequal number, wherein col(m, n) the function representation number of combinations of from n thing, getting m thing, m, n are positive integer, and m is not more than n, described unequal number equals col(1, m) * col(1, n); And
Determining unit generates locking signal according to described unequal number, whether locks with definite described all-digital phase-locked loop,
Wherein, m represents that its value is the quantity of the register of described the first value, and n represents that its value is the quantity of the register of described the second value.
5. the lock detection device for all-digital phase-locked loop according to claim 4 is characterized in that, described the first value is close with described the second value.
6. the lock detection device for all-digital phase-locked loop according to claim 5 is characterized in that, described register array comprises 7 registers.
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| CN101083523A (en) * | 2007-07-27 | 2007-12-05 | 华南理工大学 | Method for realizing integrated time stamp clock synchronous phase-locked loop |
| CN101534186A (en) * | 2008-03-10 | 2009-09-16 | 西安邮电学院 | Digital smoothing circuit and method for utilizing digital smoothing circuit to extract clock from Ethernet signals |
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| CN101083523A (en) * | 2007-07-27 | 2007-12-05 | 华南理工大学 | Method for realizing integrated time stamp clock synchronous phase-locked loop |
| CN101534186A (en) * | 2008-03-10 | 2009-09-16 | 西安邮电学院 | Digital smoothing circuit and method for utilizing digital smoothing circuit to extract clock from Ethernet signals |
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| 李建伟，徐红兵，王毅.一种锁定相位编程可调全数字锁相环设计.《现代电子技术》.2007,(第3期),第84-86页. * |
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