CN107395199A - A kind of phase-locked loop circuit - Google Patents
A kind of phase-locked loop circuit Download PDFInfo
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- CN107395199A CN107395199A CN201710842729.7A CN201710842729A CN107395199A CN 107395199 A CN107395199 A CN 107395199A CN 201710842729 A CN201710842729 A CN 201710842729A CN 107395199 A CN107395199 A CN 107395199A
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- 238000002955 isolation Methods 0.000 claims 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The present invention relates to a kind of phase-locked loop circuit, including PLL loop modules, prime amplification module, signal feedback module, central processing unit, final stage amplification module, calibration module and voltage-controlled local oscillator module；The present invention reduces the method for PLL frequency displacements by using signal feedback control loop, and provides improved ultimate voltage-controlled local oscillator output frequency signal device, will with it is more stable, more accurately output signal to user terminal.
Description
Technical field
The present invention relates to frequency signal device field, and in particular to a kind of phase-locked loop circuit.
Background technology
Phaselocked loop (phase locked loop), is exactly the loop of locking phase as its name suggests.Learned and automatically control original
The people of reason both knows about, and this is a kind of typical feedback control circuit, using being shaken inside the reference signal control loop of outside input
The frequency and phase of signal are swung, realizes that output signal frequency, from motion tracking, is generally used for Closed loop track to frequency input signal
Circuit.It is to make a kind of relatively stable method of frequency in radio transmitting, mainly there is voltage-controlled local oscillator（Voltage controlled oscillator）And PLL
IC （Phase-locked loop intergrated circuit）, voltage controlled oscillator provides a signal, a part as output, another part by frequency dividing with
Local oscillation signal caused by PLL IC makees phase bit comparison, in order to which keep frequency is constant, it is desirable to and phase difference does not change, if
Dephased change, then the voltage of PLL IC voltage output end change, go to control voltage-controlled local oscillator, until phase difference is extensive
It is multiple, reach the purpose of lock phase.The frequency of controlled oscillator and phase can be made to keep the closed loop electricity of determination relation with input signal
Sub-circuit.
In the PLL circuit environment of reality, we can also ignore the parameter of other key, that is, in whole PLL circuit
The amplitude of signal influences and the accuracy of the voltage-controlled local oscillator output frequency of final extreme pressure controlled oscillator.Domestic related document at present
This technology is not deployed to detailed research in report, cause the phenomenon of most of PLL phase-locked loop operations stability differences.
The content of the invention
The technical problem to be solved in the present invention is：It is proposed a kind of improved phase-locked loop circuit.
The present invention is to solve the technical scheme that above-mentioned technical problem proposes to be：A kind of phase-locked loop circuit, including PLL loop moulds
Block, prime amplification module, signal feedback module, central processing unit, final stage amplification module, calibration module and voltage-controlled local oscillator module；
The obtained frequency signal of the PLL loop modules delivers to the prime amplification module, the letter of the prime amplification module
Number output end is connected respectively to the signal input part of the signal feedback module and the signal input part of final stage amplification module, described
The parameter output of signal feedback module is connected to the parameter input end of the central processing unit, the control of the central processing unit
End is connected to the controlled end of the final stage amplification module；
The voltage-controlled voltage signal of the final stage amplification module exports defeated to the voltage-controlled local oscillator module, the signal of the voltage-controlled local oscillator
Go out end and be connected respectively to the signal input part of the PLL loop modules and the signal input part of calibration module, the central processing
The control terminal of device is also connected to the controlled end of the calibration module.
Further, the calibration module includes isolated amplifier, the first DDS module, the second DDS module, counted when walking
Device, wave filter and latch；
The signal output part of the isolated amplifier is connected respectively to first DDS module and the second DDS module, and described second
The signal output part of DDS module be connected to it is described walk hour counter, it is described walk hour counter be coupled to the latch；
The signal output part of first DDS module is connected to filtration module.
Further, second DDS module is suitable to carry out 1/100 to the voltage-controlled local oscillation signal inputted through isolated amplifier
Scaling down processing.
Further, the 1/100 crossover rate signal obtained through 1/100 scaling down processing is delivered to away hour counter and carried out slightly
Frequency measurement, after central processing unit reads numerical value of the latch to walking hour counter sampling, frequency values now are recorded, are multiplied
So that the coarse frequency value F of voltage-controlled local oscillator can be obtained after 100.
Further, the external communication port of first DDS module is connected to central processing unit, central processing unit according toThe frequency dividing numerical value with DDS1 communications is calculated, wherein f is the radio frequency letter of user terminal to be delivered to
Number frequency values, f0For voltage-controlled local oscillator output signal frequency, and write as specific frequency dividing numerical value of the serial communication sequential by obtained by
First DDS module buffer area, frequency signal is obtained after the first DDS module, after the frequency signal of gained is delivered into wave filter again
Obtain final frequency signal output.
The beneficial effects of the invention are as follows：
The present invention reduces the method for PLL frequency displacements by using signal feedback control loop, and provides improved ultimate voltage-controlled local oscillator
Output frequency signal device, will with it is more stable, more accurately output signal to user terminal.
Brief description of the drawings
The phase-locked loop circuit of the present invention is described further below in conjunction with the accompanying drawings.
Fig. 1 is the structured flowchart of phase-locked loop circuit in the present invention；
Fig. 2 is the circuit theory diagrams of signal feedback module；
Fig. 3 is time-domain radio-frequency signal frequency and magnitude relation figure；
Fig. 4 is the structured flowchart of calibration module.
Embodiment
Embodiment
According to Fig. 1, phase-locked loop circuit of the invention, including PLL loop modules, prime amplification module, signal feedback
Module, central processing unit, final stage amplification module, calibration module and voltage-controlled local oscillator module（VCXO）.
The obtained frequency signal of PLL loop modules delivers to prime amplification module, the signal output part of prime amplification module
It is connected respectively to the signal input part of signal feedback module and the signal input part of final stage amplification module, the ginseng of signal feedback module
Number output ends are connected to the parameter input end of central processing unit, the control terminal of central processing unit be connected to final stage amplification module by
Control end.
The voltage-controlled voltage signal of final stage amplification module, which is exported to voltage-controlled local oscillator module, the signal output part of voltage-controlled local oscillator, to be distinguished
The signal input part of PLL loop modules and the signal input part of calibration module are connected to, the control terminal of central processing unit also connects
To the controlled end of calibration module.
Prime amplification, signal feedback, final stage amplifying element are introduced in such scheme.The frequency that traditional PLL loops obtain
Rate signal do not synchronize phase demodulation before processing by prime amplification obtain radiofrequency signal be fed through signal feedback module processing；In
Central processor obtains the relevant parameter information of radiofrequency signal by the access to signal feedback module, mainly includes signal most significantly
Value, minimum amplitude, peak-to-peak value.The prime amplified signal that final stage amplification module is will be fed under the control of central processing unit is joined
Number is repaired, and completes the synchronous phase discrimination function of traditional PLL phaselocked loops.Voltage-controlled voltage signal is obtained after synchronized phase demodulation effect to remake
For voltage-controlled local oscillator, traditional PLL phase-locked loops are completed.The frequency signal of voltage-controlled local oscillator output is sent into calibration module, in centre
Manage and exported again to user terminal after being modified under the control of device to signal frequency.
On signal feedback module
As shown in Fig. 2 prime amplified signal transports to amplifier A1 and A3 respectively, and prime amplified signal delivers to A2 after A3.A4
It is voltage follower with A5, its output end V11 and V12 voltage magnitudes are identical with the voltage on electric capacity C1 and C2（One-level is added to follow
Effect be with this follower provide electric current support）.V11 and V12 delivers to A6 end of oppisite phase and in-phase end respectively, completes N
（V12-V11）Computing.
Wherein A1 and A4 completes the detection of prime amplified signal peak-peak：When prime amplified signal voltage is more than electric capacity C1
During voltage, pressure drop is produced on resistance Rf, electric current is from left to right.Do not turned on according to the disconnected rule D11 of the void of amplifier.At this moment charging electricity
Stream is carried out by D12 to C1.When the voltage of prime amplified signal is less than electric capacity C1 voltages, pressure drop, electric current are produced on resistance R2
From right to left.Do not turned on according to the disconnected rule D12 of the void of amplifier, at this moment electric current only enters A1 by D11.Due to voltage follow
Device A4 output voltages are identical with the voltage on electric capacity C1, and diode D11 cut-offs, electric capacity can not lead D11 electric discharges, and voltage is protected
Shield, i.e. electric capacity C1 and A4 outputs V11 have recorded the peak-peak of prime amplified signal.Electric capacity C1 has discharge resistance a R1, RC
Discharge time constant τ set according to the cycle of the prime amplified signal of reality, such as the frequency of prime amplified signal is
79Hz, then τ take 1S.Simultaneously V11 be delivered to A/D sampling 1 obtain corresponding to magnitude of voltage be transferred to central processing unit.
It is anti-phase that A3 completes prime amplified signal：Prime amplified signal progress of the amplifier A3 first to its input is anti-phase, then is superimposed
One negative amplitude DC level Vref, is finally completed the conversion of the high and low level of prime amplified signal, obtains signal output to amplifier
A2。
A2 and A5 completes the detection of prime amplified signal minimum peak：Prime amplified signal is delivered to after A3 is handled
Amplifier A2 in-phase end.The wherein for example above-mentioned A1 and A3 of A2 and A5 principles, only this moment passed through due to prime amplified signal
Amplifier A3 processing is crossed, what A2 and A5 were completed is the detection of prime amplified signal minimum value.V12 is delivered to A/D samplings 2 and obtained simultaneously
Corresponding magnitude of voltage is transferred to central processing unit.
A6 completes the detection of peak-to-peak value：Prime amplified signal high level V11 and low level V12 after aforementioned processing distinguishes
Difference amplifier A6 is sent into, by adjusting Ry and Rx ratio, output（V12-V11）*(Ry/Rx).A/D samplings are delivered to simultaneously
Magnitude of voltage corresponding to 3 acquisitions is transferred to central processing unit.
1,2,3 magnitudes of voltage obtained are sampled by above-mentioned A/D and may determine that the frequency of prime amplified signal module output is believed
Number amplitude Characteristics, these signals are fed back in final stage amplified signal module by central processing unit, complete synchronous phase demodulation.
Here there is a critically important technology：Substantially in accordance with main schematic diagram, we are only by above-mentioned acquisition（V12-V11）*(Ry/Rx)
Information carries out processing and is changed into amendment being delivered to voltage-controlled local oscillator with voltage-controlled voltage VX and conventional synchronization phase demodulation voltage-controlled voltage VY summations, I
Remember（V12-V11）=VPP、(Ry/Rx)=K.Here K be a gain amplifier it typically rely on and transported in signal feedback module
Put A6 feedback oscillator Ry and Rx ratio, KVPPDirectly determine and add to the voltage-controlled voltage swing of the amendment of voltage-controlled local oscillator, so
VX must be configured according to the voltage-controlled slope and conventional synchronization phase demodulation of specific voltage-controlled local oscillator with voltage-controlled voltage VY magnitudes, Wo Menyi
As take VX=VY/20 to VX=VY/10 magnitudes
The patent working benefit that above scheme obtains：
The voltage-controlled voltage that we are applied to voltage-controlled local oscillator according to above-mentioned principle is：
VY+VX=VY+（V12-V11）* (Ry/Rx)=VY+KVPP（1）
Here VY is that the synchronous phase demodulation that traditional PLL phaselocked loops obtain is voltage-controlled；K is signal feedback circuit feedback oscillator（During design
Through being fixed）；VPPIt is the peak-to-peak value of prime amplified signal.
According to time-domain radio-frequency signal frequency and magnitude relation, Fig. 3：In same time domain frequency signal output system, with defeated
The frequency for going out signal becomes big, and the peak-to-peak value of signal will diminish, as shown above.So when caused by traditional PLL phase-locked loop circuits
Signal frequency becomes hour, and the prime signal peak-to-peak value of acquisition will become big, to be obtained by the embodiment of this patent voltage-controlled voltage
VY+KVPPIt will become big（It is V in practicePPBecome big）, act on after voltage-controlled local oscillator and the signal frequency for making voltage-controlled local oscillator output become big
（Because what is selected in practice is the voltage-controlled local oscillator of just voltage-controlled slope）, thus serve the effect of compensation.
On calibration module
As shown in figure 4, voltage-controlled local oscillation signal delivers to DDS1 and DDS2 respectively through isolated amplifier：
When voltage-controlled local frequency is up to a hundred million or even hundreds of megahertzs, it is contemplated that walk limit of the hour counter to voltage-controlled local oscillator scope
System, design in the present invention wherein all the way DDS2 modules to voltage-controlled local oscillation signal carry out 1/100 scaling down processing.Voltage-controlled local oscillator pass through every
From the external clock input that DDS2 is sent directly into after amplifier, reference clock when being worked as DDS2.
The DDS chip internals actually selected have 2 48 bit frequency control registers（F0、F1）, for the present apparatus without using
Inside DDS during PLL double frequency functions, during the frequency control register F0 full packings 1 of 48, DDS has the full frequency letter of voltage-controlled local oscillator
Number output, therefore be obtain standard frequency signal export to user terminal, it is necessary to in DDS frequency control register F0 set phase
The frequency dividing numerical value answered, the method specifically calculated are：
（2）
Wherein, the specific frequency dividing numerical value calculated required for D is, f0For voltage-controlled local oscillator output signal frequency.DDS external communication end
Mouth is connected to central processing unit, and central processing unit is according to formula（2）2 obtained48×10-2Frequency dividing numerical value passes through serial communication sequential
DDS2 buffer areas are write, after the 1/100 crossover rate signal that DDS2 is obtained, hour counter 1 is delivered to away and carries out coarse frequency measurement, in
After central processor reads numerical value of the latch 1 to walking the sampling of hour counter 1, frequency values now are recorded, after being multiplied by 100 just
It can obtain the coarse frequency value F of voltage-controlled local oscillator.
Another way is sent to DDS1 external clock input by the voltage-controlled local oscillator of isolated amplifier, is worked as DDS1
When reference clock.DDS1 external communication port is connected to central processing unit simultaneously, and central processing unit is according to formula（2）Calculate
To the frequency dividing numerical value with DDS1 communications：, wherein F is counts by walking hour counter 1, central processing unit computing obtains
Voltage-controlled local oscillator coarse frequency value, f is the radio frequency signal frequency value of user terminal to be delivered to.And by serial communication sequential by institute
The specific frequency dividing numerical value write-in DDS1 buffer areas obtained, frequency signal is obtained after DDS1, the frequency signal of gained is delivered to again low
Final frequency signal output is obtained after pass filtering module.
The present invention's is not limited to above-described embodiment, and the technical scheme of above-mentioned each embodiment of the invention can be handed over each other
Fork combination forms new technical scheme, in addition all technical schemes formed using equivalent substitution, all falls within the guarantor of application claims
In the range of shield.
Claims (5)
- A kind of 1. phase-locked loop circuit, it is characterised in that：Including PLL loop modules, prime amplification module, signal feedback module, in Central processor, final stage amplification module, calibration module and voltage-controlled local oscillator module；The obtained frequency signal of the PLL loop modules delivers to the prime amplification module, the letter of the prime amplification module Number output end is connected respectively to the signal input part of the signal feedback module and the signal input part of final stage amplification module, described The parameter output of signal feedback module is connected to the parameter input end of the central processing unit, the control of the central processing unit End is connected to the controlled end of the final stage amplification module；The voltage-controlled voltage signal of the final stage amplification module exports defeated to the voltage-controlled local oscillator module, the signal of the voltage-controlled local oscillator Go out end and be connected respectively to the signal input part of the PLL loop modules and the signal input part of calibration module, the central processing The control terminal of device is also connected to the controlled end of the calibration module.
- 2. phase-locked loop circuit according to claim 1, it is characterised in that：The calibration module includes isolated amplifier, first DDS module, the second DDS module, walk hour counter, wave filter and latch；The signal output part of the isolated amplifier is connected respectively to first DDS module and the second DDS module, and described second The signal output part of DDS module be connected to it is described walk hour counter, it is described walk hour counter be coupled to the latch；The signal output part of first DDS module is connected to filtration module.
- 3. phase-locked loop circuit according to claim 2, it is characterised in that：Second DDS module is suitable to amplifying through isolation The voltage-controlled local oscillation signal of device input carries out 1/100 scaling down processing.
- 4. phase-locked loop circuit according to claim 3, it is characterised in that：1/100 point obtained through 1/100 scaling down processing Frequency signal delivers to away hour counter and carries out coarse frequency measurement, and central processing unit reads the number that latch samples to walking hour counter After value, frequency values now are recorded, are multiplied by the coarse frequency value F that voltage-controlled local oscillator can be obtained after 100.
- 5. phase-locked loop circuit according to claim 4, it is characterised in that：The external communication port of first DDS module connects Be connected to central processing unit, central processing unit according toThe frequency dividing numerical value with DDS1 communications is calculated, Wherein f is the radio frequency signal frequency value of user terminal to be delivered to, f0For voltage-controlled local oscillator output signal frequency, and pass through serial communication The specific frequency dividing numerical value of gained is write the first DDS module buffer area by sequential, and frequency signal is obtained after the first DDS module, will The frequency signal of gained obtains final frequency signal output after delivering to wave filter again.
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| CN201710842729.7A CN107395199B (en) | 2017-09-18 | 2017-09-18 | Phase-locked loop circuit |
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|---|---|---|---|---|
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-
2017
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