CN106708768A - Aurora interface binding method and device based on shared phase-locked loops - Google Patents
Aurora interface binding method and device based on shared phase-locked loops Download PDFInfo
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- CN106708768A CN106708768A CN201710138574.9A CN201710138574A CN106708768A CN 106708768 A CN106708768 A CN 106708768A CN 201710138574 A CN201710138574 A CN 201710138574A CN 106708768 A CN106708768 A CN 106708768A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention discloses an Aurora interface binding method and device based on shared phase-locked loops. The Aurora interface binding device comprises a transmitting party and a receiving party, wherein the transmitting party comprises a transmitting party user interface module, a transmitting party cache module, a transmitting party high-speed serial transceiver GTH module, a transmitting party shared phase-locked loop PLL module and a transmitting party data alignment module; the receiving party comprises a receiving party user interface module, a receiving party cache module, a receiving party high-speed serial transceiver GTH module, a receiving party shared phase-locked loop PLL module and a receiving party interface damage detecting module. The Aurora interface binding device has the advantages that clock sharing of Aurora interfaces is achieved through the phase-locked loop PLL clock resource sharing technology, Aurora interface is binding is completed by the damage detecting of the Aurora interfaces and data alignment, and high-speed, parallel and reliable transmission of data among boards is achieved.
Description
Technical field
The invention belongs to communication technical field, the one kind further related in technical field of data transmission is based on shared lock
The Ao Ruola Aurora interfaces binding methods and device of phase ring PLL (Phase Locked Loop).The present invention provides one kind and can be total to
The Aurora interface arrangements of phase-locked loop pll are enjoyed, and multiple Aurora interfaces are realized by phase-locked loop clock Resource Sharing Technology
Shared clock, is processed by the necrosis detection of Aurora interfaces and alignment of data, completes the binding of Aurora interfaces, is realized
The high-speed parallel transmitting of data between plate.
Background technology
With the development of the communication technology, docking port message transmission rate and reliability requirement more and more higher.It is existing at present
Aurora interfacings are generally used for point-to-point single channel transmission between plate, and due to the limitation of technology, single channel is point-to-point
Aurora interface data rates are up to 10Gbps.Although this mode has obtained wide in the high-speed interface that backboard is interconnected is realized
General application, but in some applications, when realizing transmission data rate higher, then requirement cannot be met.Therefore, by multiple
Parallel transmission is very important the binding of Aurora interfaces together.
Patent document " the height based on Aurora agreements that SOUL Storage Technology (Wuxi) Co., Ltd. applies at it
(publication date is the expansion structure of fast EBI " for application number 201310033124.5, the A of application publication number CN 103106169
2013.05.15 a kind of Aurora interface arrangements of backboard interconnection are proposed in), the interface arrangement enters to the data of upper-layer user
After row Aurora protocol encapsulations, it is transferred to link layer and up to physical layer and completes parallel-serial conversion, is converted into differential signal transmission
To recipient, treatment of the recipient to data is opposite with sender.But, the interface arrangement structure of the patent is still present not
Foot part is the Aurora interface arrangements for being provided, and is a kind of single pass Aurora interface arrangements, in Aurora interface arrangements
The merging transmission of multiple high speed serialization transceivers is not realized in portion, it is impossible to meet the requirement of more high data rate.The patent is same
When also proposed a kind of extended method for realizing memory interface, a kind of proprietary protocol is the method define, by proprietary protocol
Data encapsulation to Aurora interfaces, and selected the data is activation after encapsulation to system according to the bag form of proprietary protocol definition
Internal storage access LIS interfaces or register access DCR interfaces, realize the extension of memory interface.But, the extended method of the interface
The weak point being still present is, first, poor expandability, due to development board phase-locked loop pll resource-constrained, multiple Interface Expandings
The not enough problem of phase-locked loop pll clock sources occurs.Second, there is no expansion interface detection process, it is impossible to obtain each in real time
The working condition of Aurora interfaces, it is impossible to ensure the reliability of data transfer.Third, without the treatment of expansion interface alignment of data,
It cannot be guaranteed that the correctness of data transfer.
The content of the invention
It is an object of the invention to overcome above-mentioned the deficiencies in the prior art, original Aurora interface arrangements transmission is solved
Speed is relatively low, take that phase-locked loop pll resource is more when multiple Aurora interfaces are bundled, interface it is downright bad cannot detect, interface data
Do not line up, Interface Expanding difference the problems such as, it is proposed that a kind of message transmission rate is faster, resource utilization is higher, structure is simpler
Single, autgmentability is preferably based on the Aurora interface binding methods of shared phaselocked loop, to improve its Practical Performance.
Aurora interface arrangement of the present invention based on shared phaselocked loop, including sender and recipient's two parts, sender
Shared including sender's Subscriber Interface Module SIM, sender's cache module, sender high speed serialization transceiver GTH modules, sender
Phase-locked loop pll module and sender's alignment of data module；Recipient includes recipient's Subscriber Interface Module SIM, recipient's caching mould
Block, recipient high speed serialization transceiver GTH modules, the shared phase-locked loop pll module of recipient and the necrosis detection of recipient's interface
Module；Described sender's Subscriber Interface Module SIM, sender's cache module, sender's high speed serialization transceiver GTH modules pass through
Data/address bus and controlling bus are sequentially connected；The shared phase-locked loop pll module of described sender is received and dispatched with sender's high speed serialization
Device GTH modules are connected by data/address bus with controlling bus；Described sender's Subscriber Interface Module SIM and sender's alignment of data
Module is connected by data/address bus with controlling bus；Described recipient's Subscriber Interface Module SIM, recipient's cache module, recipient
High speed serialization transceiver GTH modules are sequentially connected by data/address bus and controlling bus；The shared phase-locked loop pll mould of described reception
Block is connected with recipient's high speed serialization transceiver GTH modules by data/address bus and controlling bus；Described recipient user connects
Mouth mold block is connected with recipient's interface necrosis detection module by data/address bus and controlling bus；Described sender's high speed serialization
It is connected by differential parallel holding wire backboard between transceiver GTH modules and recipient's high speed serialization transceiver GTH modules；Its
In：
Described sender Subscriber Interface Module SIM, the data for receiving upper-layer user's transmission, there is provided sender's alignment of data
The user clock signal of module；
Described sender cache module, for the data on temporary cache input data bus；
Described sender high speed serialization transceiver GTH modules, for receiving the data on input data bus, there is provided one
Shared phase-locked loop pll；
The shared phase-locked loop pll module of described sender, is fanned out to treatment, and provide transmission for carrying out increase to input clock
Clock input signal needed for the input end of clock mouthful of square high speed serialization transceiver GTP；
Described sender alignment of data module, for the output tx_dst_rdy_n_i letters to sender's Subscriber Interface Module SIM
Number registration process is carried out, and alignment of data result is uploaded into upper-layer user；
Recipient's Subscriber Interface Module SIM, the data for receiving the transmission of recipient's cache module, and it is bad to provide interface
Input signal and clock signal needed for dead detection；
Recipient's cache module, for the data on temporary cache input data bus；
The shared phase-locked loop pll module of the recipient, is fanned out to treatment, and provide reception for carrying out increase to input clock
Clock input signal needed for the input end of clock mouthful of square high speed serialization transceiver GTP；
Recipient's interface necrosis detection module, the output channel_up for detecting recipient's Subscriber Interface Module SIM
Signal, and judge the working condition of each interface；
Recipient's high speed serialization transceiver GTH modules, there is provided a shared phase-locked loop pll.
The binding method of Aurora interface of the present invention based on shared phaselocked loop, comprises the following steps：
(1) four Aurora interfaces of sender are generated：
(1a) carries out example respectively to the intellectual property IP kernel of four high speed serialization transceiver GTH of sender；
(1b) by the intellectual property IP kernel of each the high speed serialization transceiver GTH after example successively with sender's data buffer storage
Module and sender's Subscriber Interface Module SIM are connected, and generate four Aurora interfaces of sender；
(2) four Aurora interfaces of recipient are generated：
(1a) carries out example respectively to the intellectual property IP kernel of four high speed serialization transceiver GTH of recipient；
(1b) caches the intellectual property IP kernel of each the high speed serialization transceiver GTH after example with receiving side data successively
Module and recipient's Subscriber Interface Module SIM are connected, and generate four Aurora interfaces of recipient；
(3) initialize：
The speed of the user data that (3a) is sent with upper-layer user obtains Aurora interface works divided by the bit wide of user data
The clock frequency value of work；
(3b) replaced respectively with clock frequency value four intellectual property IP kernels of recipient's high speed serialization transceiver GTH when
Clock frequency parameter；
(3c) replaced respectively with clock frequency value four intellectual property IP kernels of sender's high speed serialization transceiver GTH when
Clock frequency parameter；
The unified reset signal of one, four Aurora interfaces of (3d) to sender so that four Aurora of sender connect
Mouth is in reset state；
The unified reset signal of one, four Aurora interfaces of (3e) to recipient so that four Aurora of recipient connect
Mouth is in reset state；
(4) phase-locked loop pll of sender is shared：
(4a) arbitrarily three high speed serialization transceiver GTH of selection from four high speed serialization transceiver GTH of sender, shield
Cover the phase-locked loop pll inside each high speed serialization transceiver GTH；
(4b) a pair of differential system clocks are input to the phase-locked loop pll inside unscreened high speed serialization transceiver GTH
It is interior, obtain a single-ended clock output signal；
Single-ended clock output signal is carried out increase and is fanned out to treatment by (4c) by the shared phase-locked loop pll module of sender
Afterwards, a clock output signal is obtained；
Clock output signal is sent to four input end of clock of high speed serialization transceiver GTH mouthful by (4d) simultaneously, is realized
Sender's phase-locked loop pll resource it is shared；
(5) recipient's phase-locked loop pll is shared：
(5a) arbitrarily three high speed serialization transceiver GTH of selection from four high speed serialization transceiver GTH of recipient, shield
Cover the phase-locked loop pll inside each high speed serialization transceiver GTH；
(5b) is by the phaselocked loop inside a pair of differential system clock signal inputs to unscreened high speed serialization transceiver GTH
In PLL, a single-ended clock output signal is obtained；
Single-ended clock output signal is carried out increase and is fanned out to treatment by (5c) by the shared phase-locked loop pll module of recipient
Afterwards, a clock output signal is obtained；
Clock output signal is sent to four input end of clock of high speed serialization transceiver GTH mouthful by (5d) simultaneously, is realized
Recipient's phase-locked loop pll resource it is shared；
(6) recipient's Aurora interfaces are detected：
(6a), when the output channel_up signals of recipient's Subscriber Interface Module SIM are 0, the necrosis of recipient's interface is detected
Inside modules corresponding clock counter timing since 0；
(6b) judges whether the clocking value of clock counter is equal to the frame length for frame that upper-layer user sends, if so, then
Step (6c) is performed, otherwise, it is determined that the Aurora interfaces are normal, step (7) is performed；
(6c) judges the necrosis of Aurora interfaces, the corresponding Aurora interfaces of shielding recipient's Subscriber Interface Module SIM；
(7) align sender's Aurora interface data：
(7a) from four the four of sender's Subscriber Interface Module SIM output clock signals, any selection one exports clock
Signal is used as user clock signal；
(7b) user clock signal is sent to the input end of clock mouthful of sender's alignment of data module；
(7c), when the current period of user clock signal rising edge is reached, alignment of data module is to each sender user
The tx_dst_rdy_n_i signals of interface module output carry out registration process, obtain the result of registration process；
(7d) judges whether the result of registration process is 0, if so, then judging that four Aurora interface data of sender do not have
Alignment, waits the arrival of selected user clock signal next cycle, then performs step (7c), otherwise, performs step (7e)；
(7e) judges that four Aurora interface data of sender realize that the result of registration process will be uploaded to upper strata by alignment
User.
The present invention compared with prior art, with advantages below：
First, because sender's high speed serialization transceiver GTH modules are high with recipient in Aurora interface arrangements of the present invention
Between fast serial transceiver GTH modules, it is connected by differential parallel holding wire backboard, is effectively overcome in the prior art
When Aurora interface arrangements single channel is transmitted, the problem of linear speed is limited because of interface structure so that Aurora interfaces dress of the present invention
Put with message transmission rate higher.
Second, because extended method of the invention proposes a kind of method of shared sender's phase-locked loop pll and shares
The method of recipient's phase-locked loop pll, phase-locked loop pll inadequate resource when effectively overcoming Aurora Interface Expandings in the prior art
Problem, improve phase-locked loop pll resource utilization of the present invention.
3rd, the method that detection recipient's Aurora interfaces are proposed due to extended method of the invention, real-time detection is every
The working condition of individual Aurora interfaces, efficiently against prior art in multiple Aurora interface concurrents data transmission procedures nothing
Method obtains the problem of each Aurora interfaces state in real time, improves the reliability of data transfer of the present invention.
4th, because extended method of the invention proposes a kind of method of the sender's Aurora interface data that aligns, make
Multiple Aurora interface data can align parallel transmission, effectively overcome multiple Aurora interface concurrents in the prior art
The problem that each Aurora interface data is not lined up in transmitting procedure so that the present invention has more practicality.
Brief description of the drawings
Fig. 1 is the structural representation of Aurora interface arrangements of the present invention；
Fig. 2 is the flow chart of Aurora interfaces binding method of the present invention.
Specific embodiment：
The present invention will be further described below in conjunction with the accompanying drawings.
1 pair of Aurora interface arrangements overall structure of the present invention is further described referring to the drawings.
Aurora interface arrangements based on shared phaselocked loop, including sender and recipient's two parts, sender include hair
The side's of sending Subscriber Interface Module SIM, sender's cache module, sender high speed serialization transceiver GTH modules, the shared phaselocked loop of sender
PLL modules and sender's alignment of data module；Recipient includes recipient's Subscriber Interface Module SIM, recipient's cache module, connects
Debit high speed serialization transceiver GTH modules, the shared phase-locked loop pll module of recipient and recipient's interface necrosis detection module；
Described sender's Subscriber Interface Module SIM, sender's cache module, sender high speed serialization transceiver GTH modules are total by data
Line and controlling bus are sequentially connected；The shared phase-locked loop pll module of described sender and sender's high speed serialization transceiver GTH moulds
Block is connected by data/address bus with controlling bus；Described sender's Subscriber Interface Module SIM passes through with sender's alignment of data module
Data/address bus is connected with controlling bus；Described recipient's Subscriber Interface Module SIM, recipient's cache module, recipient's high speed serialization
Transceiver GTH modules are sequentially connected by data/address bus and controlling bus；The shared phase-locked loop pll module of described reception and reception
Square high speed serialization transceiver GTH modules are connected by data/address bus with controlling bus；Described recipient's Subscriber Interface Module SIM with
Recipient's interface necrosis detection module is connected by data/address bus with controlling bus；Described sender's high speed serialization transceiver
It is connected by differential parallel holding wire backboard between GTH modules and recipient's high speed serialization transceiver GTH modules.
Sender's Subscriber Interface Module SIM, the data for receiving upper-layer user's transmission, there is provided sender's alignment of data module
User clock signal.
Sender's cache module, for the data on temporary cache input data bus, including three random access memory
RAM, first random access memory ram, 1, second random access memory ram 2 and the 3rd random access memory ram 3, first with
Machine memory RAM 1 is used for caching the data on sender's cache module input data bus, and second random access memory ram 2 is used
To cache the data on the output data bus that will export sender's cache module, the 3rd random access memory ram 3 is used for
The data on the output data bus of sender's cache module will be exported in second random access memory ram 2 of temporary cache,
The bit wide of four random access memory is 64, and work clock is 156.25MHz.
Sender's high speed serialization transceiver GTH modules, for receiving the data on input data bus, there is provided one is shared
Phase-locked loop pll.
The shared phase-locked loop pll module of sender, treatment is fanned out to for carrying out increase to input clock, and it is high to provide sender
Clock input signal needed for the input end of clock mouthful of fast serial transceiver GTP.
Sender's alignment of data module, enters for the output tx_dst_rdy_n_i signals to sender's Subscriber Interface Module SIM
Row registration process, and alignment of data result is uploaded into upper-layer user.
Recipient's Subscriber Interface Module SIM, for receiving the data of recipient's cache module transmission, and provides interface necrosis inspection
Input signal and clock signal needed for surveying.
Recipient's cache module, for the data on temporary cache input data bus, including three random access memory
RAM, first random access memory ram, 4, second random access memory ram 5 and the 3rd random access memory ram 6, first with
Machine memory RAM 4 is used for caching the data on sender's cache module input data bus, and second random access memory ram 5 is used
To cache the data that will be exported on sender's cache module output data bus, the 3rd random access memory ram 6 is used for temporarily
When second random access memory ram 5 of caching in will export data on sender's cache module output data bus, four
The bit wide of random access memory is 64, and work clock is 156.25MHz.
The shared phase-locked loop pll module of recipient, treatment is fanned out to for carrying out increase to input clock, and it is high to provide recipient
Clock input signal needed for the input end of clock mouthful of fast serial transceiver GTP.
Recipient's interface necrosis detection module, for by internal clock counter to the defeated of recipient's Subscriber Interface Module SIM
Go out channel_up signals to be detected, and judge the working condition of each interface.
Recipient's high speed serialization transceiver GTH modules, there is provided a shared phase-locked loop pll.
Referring to the drawings 2, Aurora interfaces binding method of the present invention is further described.
Step 1, generates four Aurora interfaces of sender.
Intellectual property IP kernel to four high speed serialization transceiver GTH of sender carries out example respectively.
By the intellectual property IP kernel of each the high speed serialization transceiver GTH after example successively with sender's data cache module
With the connection of sender's Subscriber Interface Module SIM, four Aurora interfaces of sender are generated.
Step 2, generates four Aurora interfaces of recipient.
Intellectual property IP kernel to four high speed serialization transceiver GTH of recipient carries out example respectively.
By the intellectual property IP kernel of each the high speed serialization transceiver GTH after example successively with receiving side data cache module
With the connection of recipient's Subscriber Interface Module SIM, four Aurora interfaces of sender are generated.
Step 3, initialization.
The speed of the user data sent with upper-layer user obtains Aurora interfaces divided by the bit wide of user data
Clock frequency value.
Replace four clocks of the intellectual property IP kernel of recipient's high speed serialization transceiver GTH respectively with clock frequency value frequently
Rate parameter value.
Replace four clocks of the intellectual property IP kernel of sender's high speed serialization transceiver GTH respectively with clock frequency value frequently
Rate parameter value.
To the unified reset signal of one, four Aurora interfaces of sender so that four Aurora interfaces of sender are equal
In reset state.
To the unified reset signal of one, four Aurora interfaces of recipient so that four Aurora interfaces of recipient are equal
In reset state.
Step 4, shares the phase-locked loop pll of sender.
Arbitrarily three high speed serialization transceiver GTH of selection from four high speed serialization transceiver GTH of sender, shielding is every
Phase-locked loop pll inside individual high speed serialization transceiver GTH.
A pair of differential system clocks are input in the phase-locked loop pll inside unscreened high speed serialization transceiver GTH, are obtained
To a single-ended clock output signal.
Single-ended clock output signal is carried out by the shared phase-locked loop pll module of sender after increase is fanned out to treatment, to obtain
To a clock output signal.
Described increase is fanned out to treatment, by matching work(of the global buffering BUFG of SEL Xilinx primitive to clock signal
Rate is amplified.
Clock output signal is sent to four input end of clock of high speed serialization transceiver GTH mouthful simultaneously, realizes sending
Square phase-locked loop pll resource it is shared.
Step 5, shares the phase-locked loop pll of recipient.
Arbitrarily three high speed serialization transceiver GTH of selection from four high speed serialization transceiver GTH of recipient, shielding is every
Phase-locked loop pll inside individual high speed serialization transceiver GTH.
By the phase-locked loop pll inside a pair of differential system clock signal inputs to unscreened high speed serialization transceiver GTH
It is interior, obtain a single-ended clock output signal.
Single-ended clock output signal is carried out by the shared phase-locked loop pll module of recipient after increase is fanned out to treatment, to obtain
To a clock output signal.
Described increase is fanned out to treatment, by matching work(of the global buffering BUFG of SEL Xilinx primitive to clock signal
Rate is amplified.
Clock output signal is sent to four input end of clock of high speed serialization transceiver GTH mouthful simultaneously, realizes receiving
Square phase-locked loop pll resource it is shared.
Step 6, detects recipient's Aurora interfaces.
The first step, when the output channel_up signals of recipient's Subscriber Interface Module SIM are 0, the necrosis inspection of recipient's interface
Survey the corresponding clock counter timing since 0 of inside modules.
Second step, judges whether the clocking value of clock counter is equal to the frame length for frame that upper-layer user sends, if so,
The step of step the three is then performed, otherwise, it is determined that the Aurora interfaces are normal, step 7 is performed.
3rd step, judges the necrosis of Aurora interfaces, the corresponding Aurora interfaces of shielding recipient's Subscriber Interface Module SIM.
Step 7, align sender's Aurora interface data.
The first step, from four the four of sender's Subscriber Interface Module SIM output clock signals, one output of any selection
Clock signal is used as user clock signal.
Second step, user clock signal is sent to the input end of clock mouthful of sender's alignment of data module.
3rd step, when the current period of user clock signal rising edge is reached, alignment of data module is to each sender
The tx_dst_rdy_n_i signals of Subscriber Interface Module SIM output carry out registration process, obtain the result of registration process.
Alignment of data module is alignd to the tx_dst_rdy_n_i signals that each sender's Subscriber Interface Module SIM is exported
The step for the treatment of, is as follows：
The first step, arbitrarily sets four register signals, respectively tx_ready1 signals, tx_ready2 signals, tx_
Ready3 signals and tx_ready4 signals, and this four register signals are initialized as 0；
Four tx_dst_rdy_n_i signals are played two bats by second step under user clock, obtain tx_dst_rdy_n_
I1 signals, tx_dst_rdy_n_i2 signals, tx_dst_rdy_n_i3 signals and tx_dst_rdy_n_i4 signals；
3rd step, tx_ready1 signals, tx_dst_rdy_n_i2 letters are assigned to by tx_dst_rdy_n_i1 signal jams
Number obstruction is assigned to tx_ready2 signals, and tx_dst_rdy_n_i3 signal jams are assigned to tx_ready3 signals, tx_dst_
Rdy_n_i4 signal jams are assigned to tx_ready4 signals；
4th step, to tx_ready1 signals, tx_ready2 signals, tx_ready3 signals and tx_ready4 signals successively
Enter line position and computing, using the result of position and computing as registration process result.
4th step, whether the result for judging registration process is 0, if so, then judging four Aurora interface data of sender
Without alignment, the arrival of selected user clock signal next cycle is waited, then perform the 3rd step, otherwise, perform the 5th step.
5th step, judges that four Aurora interface data of sender realize that alignment will upload to the result of registration process
Upper-layer user.
Claims (5)
1. a kind of Aurora interface arrangements based on shared phaselocked loop, including sender and recipient's two parts, sender include
Sender's Subscriber Interface Module SIM, sender's cache module, sender high speed serialization transceiver GTH modules, sender's shared lock phase
Ring PLL modules and sender's alignment of data module；Recipient include recipient's Subscriber Interface Module SIM, recipient's cache module,
Recipient high speed serialization transceiver GTH modules, the shared phase-locked loop pll module of recipient and recipient's interface necrosis detection mould
Block；Described sender's Subscriber Interface Module SIM, sender's cache module, sender high speed serialization transceiver GTH modules is by number
It is sequentially connected according to bus and controlling bus；The shared phase-locked loop pll module of described sender and sender's high speed serialization transceiver
GTH modules are connected by data/address bus with controlling bus；Described sender's Subscriber Interface Module SIM and sender's alignment of data mould
Block is connected by data/address bus with controlling bus；Described recipient's Subscriber Interface Module SIM, recipient's cache module, recipient are high
Fast serial transceiver GTH modules are sequentially connected by data/address bus and controlling bus；The shared phase-locked loop pll module of described reception
It is connected by data/address bus and controlling bus with recipient's high speed serialization transceiver GTH modules；Described recipient's user interface
Module is connected with recipient's interface necrosis detection module by data/address bus and controlling bus；Described sender's high speed serialization is received
It is connected by differential parallel holding wire backboard between hair device GTH modules and recipient's high speed serialization transceiver GTH modules；Wherein：
Described sender Subscriber Interface Module SIM, the data for receiving upper-layer user's transmission, there is provided sender's alignment of data module
User clock signal；
Described sender cache module, for the data on temporary cache input data bus；
Described sender high speed serialization transceiver GTH modules, for receiving the data on input data bus, there is provided one is shared
Phase-locked loop pll；
The shared phase-locked loop pll module of described sender, treatment is fanned out to for carrying out increase to input clock, and it is high to provide sender
Clock input signal needed for the input end of clock mouthful of fast serial transceiver GTP；
Described sender alignment of data module, enters for the output tx_dst_rdy_n_i signals to sender's Subscriber Interface Module SIM
Row registration process, and alignment of data result is uploaded into upper-layer user；
Recipient's Subscriber Interface Module SIM, for receiving the data of recipient's cache module transmission, and provides interface necrosis inspection
Input signal and clock signal needed for surveying；
Recipient's cache module, for the data on temporary cache input data bus；
The shared phase-locked loop pll module of the recipient, treatment is fanned out to for carrying out increase to input clock, and it is high to provide recipient
Clock input signal needed for the input end of clock mouthful of fast serial transceiver GTP；
Recipient's interface necrosis detection module, the output channel_up for detecting recipient's Subscriber Interface Module SIM believes
Number, and judge the working condition of each interface；
Recipient's high speed serialization transceiver GTH modules, there is provided a shared phase-locked loop pll.
2. Aurora interface arrangements based on shared phaselocked loop according to claim 1, it is characterised in that described reception
Square interface necrosis detection module includes a clock counter, for detecting the output letter that recipient's Subscriber Interface Module SIM sends
Number.
3. a kind of Aurora interface binding methods based on shared phaselocked loop, comprise the following steps：
(1) four Aurora interfaces of sender are generated：
(1a) carries out example respectively to the intellectual property IP kernel of four high speed serialization transceiver GTH of sender；
(1b) by the intellectual property IP kernel of each the high speed serialization transceiver GTH after example successively with sender's data cache module
With the connection of sender's Subscriber Interface Module SIM, four Aurora interfaces of sender are generated；
(2) four Aurora interfaces of recipient are generated：
(1a) carries out example respectively to the intellectual property IP kernel of four high speed serialization transceiver GTH of recipient；
(1b) by the intellectual property IP kernel of each the high speed serialization transceiver GTH after example successively with receiving side data cache module
With the connection of recipient's Subscriber Interface Module SIM, four Aurora interfaces of recipient are generated；
(3) initialize：
The speed of the user data that (3a) is sent with upper-layer user obtains Aurora interfaces divided by the bit wide of user data
Clock frequency value；
(3b) replaces four clocks of the intellectual property IP kernel of recipient's high speed serialization transceiver GTH with clock frequency value frequently respectively
Rate parameter value；
(3c) replaces four clocks of the intellectual property IP kernel of sender's high speed serialization transceiver GTH with clock frequency value frequently respectively
Rate parameter value；
The unified reset signal of one, four Aurora interfaces of (3d) to sender so that four Aurora interfaces of sender are equal
In reset state；
The unified reset signal of one, four Aurora interfaces of (3e) to recipient so that four Aurora interfaces of recipient are equal
In reset state；
(4) phase-locked loop pll of sender is shared：
(4a) arbitrarily three high speed serialization transceiver GTH of selection from four high speed serialization transceiver GTH of sender, shielding is every
Phase-locked loop pll inside individual high speed serialization transceiver GTH；
Be input to a pair of differential system clocks in the phase-locked loop pll inside unscreened high speed serialization transceiver GTH by (4b), obtains
To a single-ended clock output signal；
(4c) carries out single-ended clock output signal by the shared phase-locked loop pll module of sender after increase is fanned out to treatment, to obtain
To a clock output signal；
Clock output signal is sent to four input end of clock of high speed serialization transceiver GTH mouthful by (4d) simultaneously, realizes sending
Square phase-locked loop pll resource it is shared；
(5) recipient's phase-locked loop pll is shared：
(5a) arbitrarily three high speed serialization transceiver GTH of selection from four high speed serialization transceiver GTH of recipient, shielding is every
Phase-locked loop pll inside individual high speed serialization transceiver GTH；
(5b) is by the phase-locked loop pll inside a pair of differential system clock signal inputs to unscreened high speed serialization transceiver GTH
It is interior, obtain a single-ended clock output signal；
(5c) carries out single-ended clock output signal by the shared phase-locked loop pll module of sender after increase is fanned out to treatment, to obtain
To a clock output signal；
Clock output signal is sent to four input end of clock of high speed serialization transceiver GTH mouthful by (5d) simultaneously, realizes receiving
Square phase-locked loop pll resource it is shared；
(6) recipient's Aurora interfaces are detected：
(6a) when recipient's Subscriber Interface Module SIM output channel_up signals be 0 when, recipient's interface necrosis detection module
Internal corresponding clock counter timing since 0；
(6b) judges whether the clocking value of clock counter is equal to the frame length for frame that upper-layer user sends, if so, then performing
Step (6c), otherwise, it is determined that the Aurora interfaces are normal, performs step (7)；
(6c) judges the necrosis of Aurora interfaces, the corresponding Aurora interfaces of shielding recipient's Subscriber Interface Module SIM；
(7) align sender's Aurora interface data：
(7a) from four the four of sender's Subscriber Interface Module SIM output clock signals, any selection one exports clock signal
As user clock signal；
(7b) user clock signal is sent to the input end of clock mouthful of sender's alignment of data module；
(7c), when the current period of user clock signal rising edge is reached, alignment of data module is to each sender's user interface
The tx_dst_rdy_n_i signals of module output carry out registration process, obtain the result of registration process；
(7d) judges whether the result of registration process is 0, if so, then judging that four Aurora interface data of sender are not right
Together, the arrival of selected user clock signal next cycle is waited, then performs step (7c), otherwise, perform step (7e)；
(7e) judges that four Aurora interface data of sender realize that the result of registration process will be uploaded to upper strata and used by alignment
Family.
4. Aurora interface binding methods based on shared phaselocked loop according to claim 3, it is characterised in that step
Increase described in (4c), step (5c) is fanned out to treatment and refers to, by matching the global buffering BUFG of SEL Xilinx primitive to clock
The power of signal is amplified.
5. Aurora interface binding methods based on shared phaselocked loop according to claim 3, it is characterised in that step
It is right that alignment of data module described in (7c) is carried out to the tx_dst_rdy_n_i signals that each sender's Subscriber Interface Module SIM is exported
The step of neat treatment, is as follows：
The first step, arbitrarily sets four register signals, respectively tx_ready1 signals, tx_ready2 signals, tx_ready3
Signal and tx_ready4 signals, and this four register signals are initialized as 0；
Four tx_dst_rdy_n_i signals are played two bats by second step under user clock, obtain tx_dst_rdy_n_i1 letters
Number, tx_dst_rdy_n_i2 signals, tx_dst_rdy_n_i3 signals and tx_dst_rdy_n_i4 signals；
3rd step, tx_ready1 signals, the resistance of tx_dst_rdy_n_i2 signals are assigned to by tx_dst_rdy_n_i1 signal jams
Plug is assigned to tx_ready2 signals, and tx_dst_rdy_n_i3 signal jams are assigned to tx_ready3 signals, tx_dst_rdy_
N_i4 signal jams are assigned to tx_ready4 signals；
4th step, is carried out successively to tx_ready1 signals, tx_ready2 signals, tx_ready3 signals and tx_ready4 signals
Position and computing, using the result of position and computing as registration process result.
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| CN107395199A (en) * | 2017-09-18 | 2017-11-24 | 江汉大学 | A kind of phase-locked loop circuit |
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