CN107395199B - A phase locked loop circuit - Google Patents

Abstract

The invention relates to a phase-locked loop circuit, which includes a PLL loop module, a preamplifier module, a signal feedback module, a central processor, a final amplification module, a calibration module and a voltage-controlled local oscillator module; the invention uses a signal feedback loop This method provides a method to reduce the PLL frequency shift and provides an improved ultimate voltage-controlled local oscillator output frequency signal device, which will output a more stable and accurate signal to the user end.

Description

A phase locked loop circuit

Technical field

The invention relates to the field of frequency signal devices, and in particular to a phase-locked loop circuit.

Background technique

Phase locked loop, as the name suggests, is a phase-locked loop. Anyone who has studied the principle of automatic control knows that this is a typical feedback control circuit that uses an externally input reference signal to control the frequency and phase of the oscillation signal inside the loop to achieve automatic tracking of the output signal frequency to the input signal frequency. Generally, Used in closed loop tracking circuits. It is a method to make the frequency more stable in radio transmission. It mainly includes voltage-controlled local oscillator (voltage-controlled oscillator) and PLLIC (phase-locked loop integrated circuit). The voltage-controlled oscillator gives a signal, part of which is used as the output, and the other part By comparing the phase with the local oscillator signal generated by the PLL IC through frequency division, in order to keep the frequency unchanged, the phase difference is required not to change. If there is a change in the phase difference, the voltage at the voltage output terminal of the PLL IC changes to control The voltage controls the local oscillator until the phase difference is restored to achieve phase locking. A closed-loop electronic circuit that maintains a definite relationship between the frequency and phase of a controlled oscillator and the input signal.

In the actual PLL circuit environment, we will also ignore another key parameter, which is the amplitude influence of the signal in the entire PLL circuit and the accuracy of the final voltage-controlled local oscillator output frequency of the extreme voltage-controlled oscillator. At present, there is no detailed research on this technology in relevant domestic literature reports, resulting in the poor working stability of most PLL phase-locked loops.

Contents of the invention

The technical problem to be solved by the present invention is to propose an improved phase-locked loop circuit.

The technical solution proposed by the present invention to solve the above technical problems is: a phase-locked loop circuit, including a PLL loop module, a preamplifier module, a signal feedback module, a central processor, a final amplification module, a calibration module and a voltage control module. vibration module;

The frequency signal obtained by the PLL loop module is sent to the pre-amplification module, and the signal output end of the pre-amplification module is respectively connected to the signal input end of the signal feedback module and the signal input of the final amplification module. terminal, the parameter output terminal of the signal feedback module is connected to the parameter input terminal of the central processor, and the control terminal of the central processor is connected to the controlled terminal of the final amplification module;

The voltage-controlled voltage signal of the final amplification module is output to the voltage-controlled local oscillator module, and the signal output end of the voltage-controlled local oscillator is respectively connected to the signal input end of the PLL loop module and the signal input of the calibration module. terminal, and the control terminal of the central processor is also connected to the controlled terminal of the calibration module.

Further, the calibration module includes an isolation amplifier, a first DDS module, a second DDS module, a travel time counter, a filter and a latch;

The signal output end of the isolation amplifier is connected to the first DDS module and the second DDS module respectively, the signal output end of the second DDS module is connected to the travel time counter, and the travel time counter is coupled to the latch device;

The signal output end of the first DDS module is connected to the filter module.

Further, the second DDS module is suitable for performing 1/100 frequency division processing on the voltage-controlled local oscillator signal input through the isolation amplifier.

Further, the 1/100 frequency signal obtained through the 1/100 frequency division processing is sent to the travel time counter for coarse frequency measurement. After the central processor reads the value sampled by the latch on the travel time counter, it records the current value. After multiplying the frequency value by 100, the coarse frequency value F of the voltage-controlled local oscillator can be obtained.

Further, the external communication port of the first DDS module is connected to the central processor, and the central processor Calculate the frequency division value used for communication with DDS1/> , where f is the frequency value of the radio frequency signal to be transmitted to the user end, f ₀ is the frequency of the voltage-controlled local oscillator output signal, and the specific frequency division value obtained is written into the first DDS module buffer area through the serial communication sequence. The DDS module obtains the frequency signal, and then sends the obtained frequency signal to the filter to obtain the final frequency signal output.

The beneficial effects of the present invention are:

The present invention uses a signal feedback loop to reduce the PLL frequency shift and provides an improved ultimate voltage-controlled local oscillator output frequency signal device, which will output signals to the user end in a more stable and accurate manner.

Description of drawings

The phase-locked loop circuit of the present invention will be further described below with reference to the accompanying drawings.

Figure 1 is a structural block diagram of a phase-locked loop circuit in the present invention;

Figure 2 is the circuit schematic diagram of the signal feedback module;

Figure 3 is a diagram of the relationship between frequency and amplitude of the time domain radio frequency signal;

Figure 4 is a block diagram of the calibration module.

Detailed ways

Example

As shown in Figure 1, the phase-locked loop circuit of the present invention includes a PLL loop module, a preamplifier module, a signal feedback module, a central processor, a final amplification module, a calibration module and a voltage-controlled local oscillator module (VCXO).

The frequency signal obtained by the PLL loop module is sent to the pre-amplification module. The signal output end of the pre-amplification module is connected to the signal input end of the signal feedback module and the signal input end of the final amplification module respectively. The parameter output of the signal feedback module The terminal is connected to the parameter input terminal of the central processor, and the control terminal of the central processor is connected to the controlled terminal of the final amplifier module.

The voltage-controlled voltage signal of the final amplification module is output to the voltage-controlled local oscillator module. The signal output end of the voltage-controlled local oscillator is respectively connected to the signal input end of the PLL loop module, the signal input end of the calibration module, and the control end of the central processor. Also connected to the controlled end of the calibration module.

In the above scheme, preamplification, signal feedback, and final amplification links are introduced. The frequency signal obtained by the traditional PLL loop is amplified by the pre-stage to obtain the radio frequency signal before being processed by the synchronous phase detection and sent to the signal feedback module for processing; the central processor obtains the relevant parameter information of the radio frequency signal by accessing the signal feedback module, mainly Including the maximum amplitude, minimum amplitude, and peak-to-peak value of the signal. Under the control of the central processor, the parameters of the preamplified signal sent to the final amplification module are repaired, and the synchronous phase detection function of the traditional PLL phase-locked loop is completed. After the synchronous phase detection, the voltage-controlled voltage signal is obtained and then acts on the voltage-controlled local oscillator to complete the traditional PLL phase-locked loop. The frequency signal output by the voltage-controlled local oscillator is sent to the calibration module. Under the control of the central processor, the signal frequency is corrected and then output to the user end.

About signal feedback module

As shown in Figure 2, the pre-amplified signals are sent to operational amplifiers A1 and A3 respectively, and the pre-amplified signals are sent to A2 through A3. A4 and A5 are voltage followers, and the voltage amplitudes of their output terminals V11 and V12 are the same as the voltages on capacitors C1 and C2 (the function of adding a first-level follower is to use this follower to provide current support). V11 and V12 are sent to the inverting end and non-inverting end of A6 respectively to complete the N (V12-V11) operation.

Among them, A1 and A4 complete the detection of the maximum peak value of the preamplified signal: when the voltage of the preamplified signal is greater than the voltage of capacitor C1, a voltage drop occurs on the resistor Rf, and the current flows from left to right. According to the virtual break rule of the op amp, D11 will not conduct. At this time, the charging current flows through D12 to C1. When the voltage of the preamplified signal is lower than the voltage of capacitor C1, a voltage drop occurs on resistor R2, and the current flows from right to left. According to the virtual break rule of the op amp, D12 will not conduct, and the current will only enter A1 through D11. Since the output voltage of voltage follower A4 is the same as the voltage on capacitor C1, diode D11 is cut off, the capacitor cannot discharge through D11, and the voltage is protected, that is, the output V11 of capacitor C1 and A4 records the maximum peak value of the preamplification signal. Capacitor C1 has a discharge resistor R1. The discharge time constant τ of RC is set according to the actual period of the preamplified signal. For example, if the frequency of the preamplified signal is 79Hz, then τ should be 1S. At the same time, V11 is sent to A/D sampling 1 to obtain the corresponding voltage value and passed to the central processor.

A3 completes the inversion of the pre-amplification signal: the operational amplifier A3 first inverts the input pre-amplification signal, then superimposes a negative amplitude DC level Vref, and finally completes the conversion of the high and low levels of the pre-amplification signal to obtain the signal Output to op amp A2.

A2 and A5 complete the detection of the minimum peak value of the pre-amplification signal: the pre-amplification signal is processed by A3 and sent to the non-inverting end of the operational amplifier A2. The principles of A2 and A5 are the same as those of A1 and A3 above, except that at this time, because the pre-amplified signal has been processed by the operational amplifier A3, A2 and A5 complete the detection of the minimum value of the pre-amplified signal. At the same time, V12 is sent to A/D sampling 2 to obtain the corresponding voltage value and passed to the central processor.

A6 completes the peak-to-peak detection: the high-level V11 and low-level V12 of the preamplified signal after the aforementioned processing are sent to the differential amplifier A6 respectively. By adjusting the ratio of Ry and Rx, (V12-V11)*(Ry/ Rx). At the same time, it is sent to A/D sampling 3 to obtain the corresponding voltage value and passed to the central processor.

The voltage values obtained through the above A/D sampling 1, 2, and 3 can determine the amplitude characteristics of the frequency signal output by the preamplified signal module. These signals are fed back to the final amplified signal module through the central processor to complete the synchronous identification. Mutually. There is a very important technology here: in fact, according to the main schematic diagram, we only process the (V12-V11)*(Ry/Rx) information obtained above into the corrected voltage-controlled voltage VX and the traditional synchronous phase detection voltage The sum of the controlled voltages VY is transmitted to the voltage-controlled local oscillator. We remember (V12-V11) = V _PP , (Ry/Rx) = K. K here is an amplification gain, which specifically depends on the ratio of the feedback gain Ry and Rx of the operational amplifier A6 in the signal feedback module. KV _PP directly determines the voltage control voltage applied to the voltage-controlled local oscillator for correction, so VX must be based on The specific voltage-controlled slope of the voltage-controlled local oscillator and the traditional synchronous phase detection are set with the voltage-controlled voltage VY. We generally take the level of VX=VY/20 to VX=VY/10.

Patent implementation benefits obtained by the above scheme:

According to the above principle, the voltage-controlled voltage we apply to the voltage-controlled local oscillator is:

VY+VX=VY+（V12-V11）*(Ry/Rx)＝VY+KV _PP (1)

Here VY is the synchronous phase detection voltage control obtained by the traditional PLL phase-locked loop; K is the feedback gain of the signal feedback circuit (already fixed during design); V _PP is the peak-to-peak value of the preamplified signal.

According to the relationship between the frequency and amplitude of the time domain RF signal, Figure 3: In the same time domain frequency signal output system, as the frequency of the output signal becomes larger, the peak-to-peak value of the signal will become smaller, as shown in the figure above. Therefore, when the signal frequency generated by the traditional PLL phase-locked loop circuit becomes smaller, the peak-to-peak value of the pre-stage signal obtained will become larger, and the voltage-controlled voltage VY+KV _PP obtained through the implementation of this patent will become larger (actually V _PP becomes larger), after acting on the voltage-controlled local oscillator, the signal frequency output by the voltage-controlled local oscillator will become larger (because in practice, a voltage-controlled local oscillator with a positive voltage-controlled slope is selected), which plays a compensation role.

About the calibration module

As shown in Figure 4, the voltage-controlled local oscillator signal is sent to DDS1 and DDS2 respectively through the isolation amplifier:

When the frequency of the voltage-controlled local oscillator is hundreds of megahertz or even hundreds of megahertz, considering the limit of the travel time counter on the range of the voltage-controlled local oscillator, one of the DDS2 modules is designed in the present invention to divide the voltage-controlled local oscillator signal into 1/100 frequency processing. The voltage-controlled local oscillator is directly sent to the external clock input terminal of DDS2 after passing through the isolation amplifier, and serves as the reference clock when DDS2 is working.

The actual selected DDS chip has two 48-bit frequency control registers (F0, F1) inside. When this device does not use the DDS internal PLL frequency multiplication function, when the 48-bit frequency control register F0 is filled with all 1s, the DDS will have a voltage control The local oscillator outputs a full frequency signal. Therefore, in order to obtain a standard frequency signal and output it to the user end, it is necessary to set the corresponding frequency division value in the frequency control register F0 in DDS. The specific calculation method is:

(2)

Among them, D is the specific frequency division value that needs to be calculated, and f ₀ is the voltage-controlled local oscillator output signal frequency. The external communication port of DDS is connected to the central processor. The central processor writes the 2 ⁴⁸ × 10 ^-2 frequency division value obtained according to equation (2) into the DDS2 cache area through the serial communication timing. The 1/100 division frequency obtained through DDS2 After receiving the signal, it is sent to travel time counter 1 for coarse frequency measurement. After the central processor reads the value sampled by latch 1 on travel time counter 1, it records the frequency value at this time. After multiplying by 100, the voltage controlled local oscillator can be obtained. The coarse frequency value F.

Another voltage-controlled local oscillator that passes through the isolation amplifier is sent to the external clock input of DDS1 as the reference clock when DDS1 is working. At the same time, the external communication port of DDS1 is connected to the central processor, and the central processor calculates the frequency division value for communication with DDS1 according to equation (2): , where F is the coarse frequency value of the voltage-controlled local oscillator obtained by counting with the travel time counter 1 and calculated by the central processor, and f is the frequency value of the radio frequency signal to be transmitted to the user end. And write the specific frequency division value obtained into the DDS1 buffer area through the serial communication sequence. After passing through DDS1, the frequency signal is obtained. The obtained frequency signal is then sent to the low-pass filter module to obtain the final frequency signal output.

The present invention is not limited to the above-mentioned embodiments. The technical solutions of the above-mentioned embodiments of the present invention can be cross-combined with each other to form new technical solutions. In addition, any technical solution formed by using equivalent substitutions falls within the protection scope required by the present invention. .

Claims (4)

1. A phase locked loop circuit, characterized by: the system comprises a PLL loop module, a pre-stage amplifying module, a signal feedback module, a central processing unit, a final stage amplifying module, a calibration module and a voltage-controlled local oscillation module;

the obtained frequency signal of the PLL loop module is sent to the pre-stage amplifying module, the signal output end of the pre-stage amplifying module is respectively connected to the signal input end of the signal feedback module and the signal input end of the final-stage amplifying module, the parameter output end of the signal feedback module is connected to the parameter input end of the central processing unit, and the control end of the central processing unit is connected to the controlled end of the final-stage amplifying module;

the voltage-controlled voltage signal of the final-stage amplifying module is output to the voltage-controlled local oscillation module, the signal output end of the voltage-controlled local oscillation module is respectively connected to the signal input end of the PLL loop module and the signal input end of the calibration module, and the control end of the central processing unit is also connected to the controlled end of the calibration module;

the frequency signal obtained by the PLL loop is sent to a signal feedback module for processing after being obtained by a pre-amplifying module before synchronous phase discrimination processing; the central processing unit obtains relevant parameter information of the radio frequency signal through accessing the signal feedback module, wherein the relevant parameter information comprises a maximum amplitude value, a minimum amplitude value and a peak value of the signal;

the calibration module comprises an isolation amplifier, a first DDS module, a second DDS module, a time counter, a filter and a latch;

the signal output end of the isolation amplifier is respectively connected to the first DDS module and the second DDS module, the signal output end of the second DDS module is connected to the time-running counter, and the time-running counter is coupled to the latch;

and the signal output end of the first DDS module is connected to the filtering module.

2. The phase-locked loop circuit of claim 1, wherein: the second DDS module is suitable for carrying out 1/100 frequency division processing on the voltage-controlled local oscillation signal input by the isolation amplifier.

3. The phase-locked loop circuit of claim 2, wherein: and sending the 1/100 frequency division signal obtained through the 1/100 frequency division processing to a time counter for coarse frequency measurement, and recording the frequency value at the moment after the central processing unit reads the value sampled by the latch on the time counter, and multiplying the value by 100 to obtain the coarse frequency value F of the voltage-controlled local oscillator.

4. A phase locked loop circuit according to claim 3, wherein: the external communication port of the first DDS module is connected to a central processing unit, and the central processing unit is used for controlling the external communication port of the first DDS module according to the dataCalculating to obtain frequency division value for communication with the first DDS moduleWherein f is the frequency value of the RF signal to be transmitted to the user, f ₀ And the frequency signal is output for the voltage-controlled local oscillator, the obtained specific frequency division value is written into a buffer area of the first DDS module through serial communication time sequence, a frequency signal is obtained after passing through the first DDS module, and the obtained frequency signal is sent to a filter to obtain a final frequency signal output.