CN107395199B - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- 238000001914 filtration Methods 0.000 claims description 3
- 238000005259 measurement Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 5
- 230000003321 amplification Effects 0.000 description 17
- 238000003199 nucleic acid amplification method Methods 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention relates to a phase-locked loop circuit, which comprises a PLL loop module, a pre-stage amplifying module, a signal feedback module, a central processing unit, a final-stage amplifying module, a calibration module and a voltage-controlled local oscillation module; the present invention provides a method for reducing PLL frequency shift by using a signal feedback loop, and an improved final voltage controlled local oscillator output frequency signal device, which will output a signal to the user terminal with a more stable and more accurate.
Description
Technical Field
The invention relates to the field of frequency signal devices, in particular to a phase-locked loop circuit.
Background
A phase locked loop (phase locked loop), as the name implies, is a phase locked loop. It is known by those who learn the principle of automatic control that this is a typical feedback control circuit, and the frequency and phase of the oscillating signal inside the loop are controlled by using an externally input reference signal, so as to realize automatic tracking of the frequency of the output signal to the frequency of the input signal, which is generally used in a closed loop tracking circuit. The method is a method for stabilizing the frequency in radio transmission, mainly comprising a voltage-controlled local oscillator (voltage-controlled oscillator) and a PLL (phase-locked loop integrated circuit), wherein the voltage-controlled oscillator gives out a signal, one part is used as output, the other part is used for phase comparison with a local oscillator signal generated by the PLL through frequency division, in order to keep the frequency unchanged, the phase difference is required not to change, and if the phase difference changes, the voltage at the voltage output end of the PLL changes to control the voltage-controlled local oscillator until the phase difference is recovered, thereby achieving the purpose of phase locking. A closed loop electronic circuit that maintains a defined relationship between the frequency and phase of the controlled oscillator and the input signal.
In the actual PLL circuit environment, we ignore the other critical parameter, namely the amplitude influence of the signal in the whole PLL circuit and the accuracy of the final voltage-controlled local oscillator output frequency of the extreme pressure controlled oscillator. At present, no detailed research on the technology is developed in domestic related literature reports, and the phenomenon that most PLL phase-locked loops are poor in working stability is caused.
Disclosure of Invention
The invention aims to solve the technical problems that: an improved phase locked loop circuit is presented.
The technical scheme provided by the invention for solving the technical problems is as follows: a phase-locked loop circuit comprises a PLL loop module, a pre-stage amplifying module, a signal feedback module, a central processing unit, a final stage amplifying module, a calibration module and a voltage-controlled local oscillation module;
the obtained frequency signal of the PLL loop module is sent to the pre-stage amplifying module, the signal output end of the pre-stage amplifying module is respectively connected to the signal input end of the signal feedback module and the signal input end of the final-stage amplifying module, the parameter output end of the signal feedback module is connected to the parameter input end of the central processing unit, and the control end of the central processing unit is connected to the controlled end of the final-stage amplifying module;
the voltage-controlled voltage signal of the final-stage amplifying module is output to the voltage-controlled local oscillation module, the signal output end of the voltage-controlled local oscillation module is respectively connected to the signal input end of the PLL loop module and the signal input end of the calibration module, and the control end of the central processing unit is also connected to the controlled end of the calibration module.
Further, the calibration module comprises an isolation amplifier, a first DDS module, a second DDS module, a time counter, a filter and a latch;
the signal output end of the isolation amplifier is respectively connected to the first DDS module and the second DDS module, the signal output end of the second DDS module is connected to the time-running counter, and the time-running counter is coupled to the latch;
and the signal output end of the first DDS module is connected to the filtering module.
Furthermore, the second DDS module is suitable for carrying out 1/100 frequency division processing on the voltage-controlled local oscillation signal input by the isolation amplifier.
Further, the 1/100 frequency division signal obtained by the 1/100 frequency division processing is sent to a time counter for coarse frequency measurement, and after the central processing unit reads the value sampled by the latch on the time counter, the frequency value at the moment is recorded, and after the frequency value is multiplied by 100, the coarse frequency value F of the voltage-controlled local oscillator is obtained.
Further, the external communication port of the first DDS module is connected to the central processing unitThe CPU is based onCalculating to obtain the frequency division value +.>Wherein f is the frequency value of the RF signal to be transmitted to the user terminal, f 0 And the frequency signal is output for the voltage-controlled local oscillator, the obtained specific frequency division value is written into a buffer area of the first DDS module through serial communication time sequence, a frequency signal is obtained after passing through the first DDS module, and the obtained frequency signal is sent to a filter to obtain a final frequency signal output.
The beneficial effects of the invention are as follows:
the present invention provides a method for reducing PLL frequency shift by using a signal feedback loop, and an improved final voltage controlled local oscillator output frequency signal device, which will output a signal to the user terminal with a more stable and more accurate.
Drawings
The phase locked loop circuit of the present invention is further described with reference to the accompanying drawings.
FIG. 1 is a block diagram of a phase locked loop circuit in accordance with the present invention;
FIG. 2 is a schematic circuit diagram of a signal feedback module;
FIG. 3 is a plot of frequency versus amplitude for a time domain RF signal;
fig. 4 is a block diagram of the calibration module.
Detailed Description
Examples
The phase-locked loop circuit according to the present invention, as shown in fig. 1, includes a PLL loop module, a pre-amplification module, a signal feedback module, a central processing unit, a final amplification module, a calibration module, and a voltage-controlled local oscillator module (VCXO).
The obtained frequency signal of the PLL loop module is sent to a pre-stage amplifying module, the signal output end of the pre-stage amplifying module is respectively connected to the signal input end of the signal feedback module and the signal input end of the final-stage amplifying module, the parameter output end of the signal feedback module is connected to the parameter input end of a central processing unit, and the control end of the central processing unit is connected to the controlled end of the final-stage amplifying module.
The voltage-controlled voltage signal of the final-stage amplifying module is output to the voltage-controlled local oscillation module, the signal output end of the voltage-controlled local oscillation module is respectively connected to the signal input end of the PLL loop module and the signal input end of the calibration module, and the control end of the central processing unit is also connected to the controlled end of the calibration module.
In the scheme, a front stage amplification, signal feedback and final stage amplification link is introduced. The frequency signal obtained by the traditional PLL loop is amplified by a pre-stage before synchronous phase discrimination processing, so that a radio frequency signal is obtained and is sent to a signal feedback module for processing; the central processing unit obtains relevant parameter information of the radio frequency signal through accessing the signal feedback module, and the relevant parameter information mainly comprises a maximum amplitude value, a minimum amplitude value and a peak-to-peak value of the signal. And under the control of the CPU, the pre-amplification signal sent to the final-stage amplification module is subjected to parameter restoration, and the synchronous phase discrimination function of the traditional PLL phase-locked loop is completed. The voltage-controlled voltage signal obtained after synchronous phase discrimination is acted on the voltage-controlled local oscillator to complete the traditional PLL phase-locked loop. The frequency signal output by the voltage-controlled local oscillator is sent to the calibration module, and the signal frequency is corrected under the control of the central processing unit and then is output to the user side.
Feedback module for signal
As shown in fig. 2, the pre-amplified signals are respectively supplied to the operational amplifiers A1 and A3, and the pre-amplified signal is supplied to A2 through A3. A4 and A5 are voltage followers whose output terminals V11 and V12 are the same voltage magnitude as the voltages on the capacitors C1 and C2 (the effect of the plus-stage follower is to provide current support with this follower). V11 and V12 are respectively sent to the inverting terminal and the non-inverting terminal of A6 to finish N (V12-V11) operation.
Wherein A1 and A4 complete the detection of the maximum peak value of the pre-amplification signal: when the amplified signal voltage of the front stage is greater than the voltage of the capacitor C1, voltage drop is generated on the resistor Rf, and the current flows from left to right. The virtual circuit D11 is not conducted according to the operational amplifier. At this time, the charging current is conducted to C1 through D12. When the voltage of the amplified signal of the front stage is lower than the voltage of the capacitor C1, voltage drop is generated on the resistor R2, and the current is from right to left. According to the virtual break rule D12 of the operational amplifier, the current is not conducted, and only passes through D11 to enter A1. Since the voltage follower A4 outputs the same voltage as the voltage on the capacitor C1, the diode D11 is turned off, the capacitor cannot discharge through D11, and the voltage is protected, i.e. the capacitors C1 and A4 output V11 record the maximum peak value of the pre-amplification signal. The capacitor C1 has a discharge resistor R1, RC with a discharge time constant τ set according to the period of the actual pre-amplification signal, for example, if the frequency of the pre-amplification signal is 79Hz, τ may be 1S. And V11 is transmitted to the A/D sampling 1 to obtain a corresponding voltage value and then transmitted to the central processing unit.
A3, finishing the inversion of the pre-amplification signal: the operational amplifier A3 inverts the input pre-stage amplified signal, and then superimposes a negative amplitude direct current level Vref, and finally completes the high and low level conversion of the pre-stage amplified signal, and the obtained signal is output to the operational amplifier A2.
A2 and A5 finish the detection of the minimum peak value of the pre-amplification signal: the pre-amplified signal is processed by A3 and is sent to the non-inverting terminal of the operational amplifier A2. The principle of A2 and A5 is as the above A1 and A3, except that at this moment, the detection of the minimum value of the pre-amplification signal is completed by A2 and A5 because the pre-amplification signal has already been processed by the operational amplifier A3. And V12 is transmitted to the A/D sampling 2 to obtain corresponding voltage value and then transmitted to the central processing unit.
A6, detecting peak-to-peak value: the high level V11 and the low level V12 of the pre-amplified signal after the processing are respectively sent to the differential amplifier A6, and the ratio of Ry to Rx is adjusted to output (V12-V11) × (Ry/Rx). And simultaneously, the voltage value is transmitted to the A/D sampling 3 to obtain a corresponding voltage value, and the corresponding voltage value is transmitted to the central processing unit.
The amplitude characteristics of the frequency signals output by the front-stage amplification signal module can be judged through the voltage values obtained by the A/D sampling 1, 2 and 3, and the signals are fed back to the final-stage amplification signal module through the central processing unit to finish synchronous phase discrimination. There is a very important technology: in fact, according to the main schematic diagram, we only process the obtained (V12-V11)/(Ry/Rx) information to become the correction voltage-controlled voltage VX and the traditional synchronous phase-discrimination voltage-controlled voltage VY to sum and send to the voltage-controlled local oscillator, we note that (V12-V11) =v PP (Ry/Rx) =k. Where K is an amplification gain and is specificallyDependent on the ratio of Ry to Rx of the feedback gain of the operational amplifier A6 in the signal feedback module, KV PP Directly determining the magnitude of the correction voltage applied to the voltage-controlled local oscillator, so that VX must be set according to the voltage-controlled slope of the specific voltage-controlled local oscillator and the magnitude of the voltage-controlled voltage VY for traditional synchronous phase discrimination, and we generally take the magnitudes of VX=VY/20 to VX=VY/10
The patent implementation benefit obtained by the scheme is as follows:
according to the principle, the voltage-controlled voltage applied to the voltage-controlled local oscillator is as follows:
VY+VX=VY+（V12-V11）*(Ry/Rx)＝VY+KV PP （1）
here VY is the synchronous phase discrimination voltage control obtained by the conventional PLL phase locked loop; k is the feedback gain of the signal feedback circuit (which is fixed in design); v (V) PP Is the peak-to-peak value of the pre-amplified signal.
According to the relation between the frequency and the amplitude of the time domain radio frequency signal, fig. 3: in the same time domain frequency signal output system, as the frequency of the output signal becomes larger, the peak-to-peak value of the signal becomes smaller as shown in the above figure. Therefore, when the frequency of the signal generated by the traditional PLL phase-locked loop circuit is reduced, the peak-to-peak value of the obtained previous signal will be increased, and the voltage-controlled voltage VY+KV obtained by the embodiment of the patent PP Will become larger (in practice V) PP Become larger), the signal frequency output by the voltage-controlled local oscillator becomes larger after acting on the voltage-controlled local oscillator (because the voltage-controlled local oscillator with positive voltage control slope is selected in practice), thus the compensation function is realized.
With respect to calibration modules
As shown in fig. 4, the voltage-controlled local oscillation signals are sent to DDS1 and DDS2 respectively through isolation amplifiers:
when the voltage-controlled local oscillation frequency is hundreds of megahertz or even hundreds of megahertz, considering the limitation of the running counter to the voltage-controlled local oscillation range, one DDS2 module is designed to carry out 1/100 frequency division processing on the voltage-controlled local oscillation signal. The voltage-controlled local oscillator is directly transmitted to the external clock input end of the DDS2 after passing through the isolation amplifier and is used as a reference clock when the DDS2 works.
2 48-bit frequency control registers (F0 and F1) are arranged in a DDS chip actually selected, when the DDS internal PLL frequency doubling function is not used in the device, the DDS can output voltage-controlled local oscillator full-frequency signals when the 48-bit frequency control register F0 is fully filled with 1, so that corresponding frequency division values are required to be set for the frequency control register F0 in the DDS in order to obtain standard frequency signals to be output to a user side, and the specific calculation method is as follows:
（2）
wherein D is a specific frequency division value to be calculated, f 0 And outputting signal frequency for the voltage-controlled local oscillation. The external communication port of the DDS is connected to a central processing unit, and the central processing unit obtains 2 according to the formula (2) 48 ×10 -2 The frequency division value is written into a DDS2 buffer area through serial communication time sequence, after a 1/100 frequency division signal obtained through the DDS2 is sent to a time counter 1 for coarse frequency measurement, after the central processing unit reads the value sampled by the time counter 1 by the latch 1, the frequency value at the moment is recorded, and after the frequency value is multiplied by 100, the coarse frequency value F of the voltage-controlled local oscillator can be obtained.
The other path of voltage-controlled local oscillation passing through the isolation amplifier is sent to the external clock input end of the DDS1 and used as a reference clock when the DDS1 works. Meanwhile, an external communication port of the DDS1 is connected to a central processing unit, and the central processing unit calculates a frequency division value for communication with the DDS1 according to the formula (2):wherein F is the coarse frequency value of the voltage-controlled local oscillator obtained by counting by the time counter 1 and operation by the central processing unit, and F is the frequency value of the radio frequency signal to be transmitted to the user terminal. And writing the obtained specific frequency division value into a DDS1 buffer area through a serial communication time sequence, obtaining a frequency signal after the DDS1, and sending the obtained frequency signal to a low-pass filtering module to obtain a final frequency signal to be output.
The technical solutions of the above embodiments of the present invention can be cross-combined with each other to form a new technical solution, and in addition, all technical solutions formed by equivalent substitution fall within the scope of protection claimed by the present invention.
Claims (4)
1. A phase locked loop circuit, characterized by: the system comprises a PLL loop module, a pre-stage amplifying module, a signal feedback module, a central processing unit, a final stage amplifying module, a calibration module and a voltage-controlled local oscillation module;
the obtained frequency signal of the PLL loop module is sent to the pre-stage amplifying module, the signal output end of the pre-stage amplifying module is respectively connected to the signal input end of the signal feedback module and the signal input end of the final-stage amplifying module, the parameter output end of the signal feedback module is connected to the parameter input end of the central processing unit, and the control end of the central processing unit is connected to the controlled end of the final-stage amplifying module;
the voltage-controlled voltage signal of the final-stage amplifying module is output to the voltage-controlled local oscillation module, the signal output end of the voltage-controlled local oscillation module is respectively connected to the signal input end of the PLL loop module and the signal input end of the calibration module, and the control end of the central processing unit is also connected to the controlled end of the calibration module;
the frequency signal obtained by the PLL loop is sent to a signal feedback module for processing after being obtained by a pre-amplifying module before synchronous phase discrimination processing; the central processing unit obtains relevant parameter information of the radio frequency signal through accessing the signal feedback module, wherein the relevant parameter information comprises a maximum amplitude value, a minimum amplitude value and a peak value of the signal;
the calibration module comprises an isolation amplifier, a first DDS module, a second DDS module, a time counter, a filter and a latch;
the signal output end of the isolation amplifier is respectively connected to the first DDS module and the second DDS module, the signal output end of the second DDS module is connected to the time-running counter, and the time-running counter is coupled to the latch;
and the signal output end of the first DDS module is connected to the filtering module.
2. The phase-locked loop circuit of claim 1, wherein: the second DDS module is suitable for carrying out 1/100 frequency division processing on the voltage-controlled local oscillation signal input by the isolation amplifier.
3. The phase-locked loop circuit of claim 2, wherein: and sending the 1/100 frequency division signal obtained through the 1/100 frequency division processing to a time counter for coarse frequency measurement, and recording the frequency value at the moment after the central processing unit reads the value sampled by the latch on the time counter, and multiplying the value by 100 to obtain the coarse frequency value F of the voltage-controlled local oscillator.
4. A phase locked loop circuit according to claim 3, wherein: the external communication port of the first DDS module is connected to a central processing unit, and the central processing unit is used for controlling the external communication port of the first DDS module according to the dataCalculating to obtain frequency division value for communication with the first DDS moduleWherein f is the frequency value of the RF signal to be transmitted to the user, f 0 And the frequency signal is output for the voltage-controlled local oscillator, the obtained specific frequency division value is written into a buffer area of the first DDS module through serial communication time sequence, a frequency signal is obtained after passing through the first DDS module, and the obtained frequency signal is sent to a filter to obtain a final frequency signal output.
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