CN107741523B - Time domain signal measuring device based on PLL - Google Patents
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Abstract
The invention relates to a time domain signal measuring device based on a PLL (phase locked loop), which comprises a normalization module, a VCXO (vertical resonant oscillator-to-oscillator) module, a frequency measuring instrument, a single chip microcomputer, a compensation module and a PLL loop unit, wherein the VCXO module is connected with the normalization module; the invention provides a time domain signal measuring device based on a PLL (phase locked Loop), a method for reducing PLL frequency shift by using a signal feedback loop, and an improved final VCXO output frequency signal device, which can interface with a measuring system of a user terminal by a more stable and more accurate output signal.
Description
Technical Field
The invention relates to the field of signal measurement, in particular to a time domain signal measuring device based on a PLL (phase locked loop).
Background
A phase locked loop (pll), as the name implies, is a phase locked loop. As known to those who have learned the principle of automatic control, this is a typical feedback control circuit, which uses an externally input reference signal to control the frequency and phase of an internal oscillation signal of a loop, so as to realize automatic tracking of the frequency of an output signal to the frequency of an input signal, and is generally used in a closed-loop tracking circuit. The method for stabilizing frequency in radio transmission mainly includes VCXO (voltage controlled oscillator) and PLL IC (phase locked loop integrated circuit), in which the voltage controlled oscillator can give out a signal, one portion can be used as output, another portion can be compared with local oscillator signal produced by PLL IC by means of frequency division, in order to keep frequency constant, it is required that the phase difference does not change, if the phase difference is changed, the voltage of voltage output end of PLL IC can be changed, and can be used for controlling VCXO until the phase difference is recovered so as to attain the goal of locking phase. A closed loop electronic circuit that maintains both the frequency and phase of a controlled oscillator in a defined relationship with an input signal.
In the actual PLL circuit environment, we also ignore another key parameter, that is, the amplitude effect of the signal in the whole PLL circuit and finally the accuracy of the output frequency of the voltage controlled oscillator VCXO. At present, detailed research is not carried out on the technology in relevant domestic literature reports, and the phenomenon that most PLL (phase locked loop) is poor in working stability is caused.
The evaluation of the frequency stability of time domain frequency signals is an important aspect of time frequency research work. For a signal source, its output signal is usually expressed by the following equation:
wherein a (t) represents random amplitude fluctuations of the signal source output signal over time,
showing the random fluctuation of the phase (i.e. frequency) of the output signal of the signal source with time, delta.t showing the slight unidirectional variation of the frequency of the output signal of the signal source with time, called frequency drift, the currently preferred VCXO is generally several x 10-12－×10-14Magnitude.
The delta t is caused by aging of the inside of the signal source along with time, and the introduced output frequency changes in a single direction.
Early people characterized the frequency stability of a signal source by the standard deviation of relative frequency offset fluctuations. If f0 is the average frequency of the signal source, the relative frequency offset of the output frequency during the sampling time τ is:
research shows that for various signal source output signals, the relative frequency offset fluctuation y of the output frequencyτThe size and speed of (t) are influenced by 5 kinds of noises listed in a power law spectrum noise model, wherein the power law spectrum noise model comprises the following steps:
wherein α ═ 2, -1, 0, 1, 2; f is more than 0 and less than fh，hαIs constant and the size is determined by the specific signal source; f. ofhIs the high cut-off frequency of the system.
Practical use shows that the frequency of the measured frequency source has range limitation when entering the measuring instrument, which is one of the defects; secondly, the frequency instability of the external reference clock itself can bring errors to the system measurement.
The above problems remain to be solved.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a time domain signal measuring device based on a PLL having a more stable and accurate output signal is provided.
The technical scheme provided by the invention for solving the technical problems is as follows: a time domain signal measuring device based on a PLL (phase locked Loop) comprises a normalization module, a VCXO (virtual Circuit Crystal oxygen) module, a frequency measuring instrument, a single chip microcomputer, a compensation module and a PLL loop unit;
the VCXO module is suitable for outputting a high-stability external reference source clock signal, and the external reference source clock signal is respectively sent to the normalization module and the frequency measuring instrument;
the normalization module is suitable for performing normalization processing on the frequency signal to be measured under the action of the external reference source clock to obtain a standard frequency signal for 1MHz verification and outputting the frequency signal to the frequency measuring instrument;
the frequency measuring instrument is suitable for measuring the time domain frequency of the signal frequency output by the normalization module according to the sampling time T being 10 seconds under the action of an external reference source clock, and sending the measuring result to an external computer;
the compensation module is suitable for performing compensation control on the output error frequency of the VCXO module;
the single chip microcomputer is suitable for performing parameter control on the normalization module, the frequency measuring instrument and the compensation module;
the PLL unit is adapted to close-loop control the accuracy of the VCXO module output frequency by a precise signal frequency.
Furthermore, the PLL loop unit includes a PLL loop module, a pre-amplification module, a signal feedback module, and a final-amplification module, and before the synchronous phase discrimination processing, the frequency signal obtained by the PLL loop module is amplified by the pre-amplification to obtain a radio frequency signal, which is sent to the signal feedback module for processing;
the single chip microcomputer obtains relevant parameter information of the radio frequency signal through accessing the signal feedback module, the relevant parameter information comprises a maximum amplitude value, a minimum amplitude value and a peak-to-peak value of the signal, the parameter of the pre-stage amplification signal sent to the final-stage amplification module is repaired under the control of the single chip microcomputer, and the synchronous phase discrimination function of the traditional PLL is completed;
after the synchronous phase discrimination, the voltage-controlled voltage signal is obtained and then used for the VCXO module to complete the PLL phase-locked loop.
Furthermore, the normalization module comprises a first isolation amplifier, a first DDS module and a second DDS frequency division rate unit, a reference frequency signal f0 of the external reference source clock passes through the first isolation amplifier and then is sent to an external clock input end of the first DDS module to serve as a working external reference clock of the first DDS module, and an external communication port of the first DDS module is connected to the single chip microcomputer and used for receiving control word commands from the single chip microcomputer and carrying out bidirectional data transmission;
the second DDS frequency division unit comprises a second isolation amplifier, a second DDS module, a travel time counter, a latch, a third DDS module and a filtering module; the second isolation amplifier is respectively connected to the second DDS module and a third DDS module, the second DDS module, the first travel time counter and the first latch sequentially form signal connection, and the third DDS module is connected to the filtering module; and the external communication ports of the second DDS module and the third DDS module are respectively connected to the singlechip and used for receiving control word commands from the singlechip and carrying out bidirectional data transmission.
Further, the frequency measuring instrument comprises a third isolation amplifier, a second travel time counter, a second latch, a fourth isolation amplifier, a third travel time counter and a third latch; the third isolation amplifier, the second travel time counter and the second latch form signal connection in sequence; the fourth isolation amplifier, the third travel time counter and the third latch form signal connection in sequence; the third isolation amplifier and the fourth isolation amplifier are further respectively connected to the single chip microcomputer, controlled ends of the second travel time counter and the third travel time counter are respectively connected to a control end of the single chip microcomputer, and a reading end of the single chip microcomputer is further respectively connected to the second latch and the third latch.
Furthermore, the compensation module comprises a first voltage reference module, a second voltage reference module, a D/A module and a temperature control module;
the first voltage reference module is suitable for providing a stable voltage output to the VCXO module;
the second voltage reference module is suitable for providing a stable voltage reference and sending the stable voltage reference to an external voltage reference end of the D/A module;
the temperature control module is arranged on the outer wall of the VCXO module and comprises a temperature control chip and a second thermistor, and the temperature control module is suitable for detecting the working temperature of the VCXO module and sending the result to the single chip microcomputer;
the D/A module is suitable for outputting a direct current voltage value with variable size under the control of the single chip microcomputer and sending the direct current voltage value to the VCXO module.
The invention has the beneficial effects that:
the invention provides a time domain signal measuring device based on a PLL (phase locked Loop), a method for reducing PLL frequency shift by using a signal feedback loop, and an improved final VCXO output frequency signal device, which can interface with a measuring system of a user terminal by a more stable and more accurate output signal.
Drawings
The time domain signal measuring device based on the PLL phase-locked loop of the present invention will be further described with reference to the accompanying drawings.
FIG. 1 is a block diagram of a time domain signal measuring device based on a PLL according to the present invention;
FIG. 2 is a block diagram of the structure and operation of a PLL loop unit;
FIG. 3 is a block diagram of a normalization module;
fig. 4 is a block diagram of a second DDS frequency dividing unit;
FIG. 5 is a block diagram of the structure and operation of a compensation module;
FIG. 6 is a circuit diagram of a temperature control module;
FIG. 7 is a schematic diagram of a compensation module;
FIG. 8 is a schematic diagram of frequency measurement of a signal;
FIG. 9 is a schematic block diagram of the structure of the frequency measuring instrument;
fig. 10 is a circuit schematic of a signal feedback module.
Detailed Description
Examples
Referring to fig. 1, the time domain signal measuring apparatus based on the PLL phase-locked loop of the present invention includes a normalization module, a VCXO module, a frequency measuring instrument, a single chip, a compensation module, and a PLL loop unit.
The VCXO module is suitable for outputting a high-stability external reference source clock signal, and the external reference source clock signal is respectively sent to the normalization module and the frequency measuring instrument;
the normalization module is suitable for normalizing the measured frequency signal under the action of an external reference source clock to obtain a standard frequency signal for 1MHz verification and outputting the standard frequency signal to the frequency measuring instrument.
As shown in fig. 3, it may be preferable that: the normalization module comprises a first isolation amplifier, a first DDS module and a second DDS frequency division rate unit.
The reference frequency signal f0 is sent to the external clock input end of the first DDS module after passing through the first isolation amplifier, and is used as the external reference clock for the first DDS module to work, and the external communication port of the first DDS module is connected to the single chip microcomputer for receiving the control word command from the single chip microcomputer and performing bidirectional data transmission. Actually, 2 48-bit frequency control registers (F0, F1) are arranged in a DDS chip, a reference frequency signal F0 of the device is 10MHz, when the frequency doubling function of the DDS internal PLL is not used, and when 1 is fully filled in the 48-bit frequency control register F0, the DDS outputs a 10MHz frequency signal, so that in order to obtain a standard sampling time period signal T (e.g., 1 second and 10 seconds), a corresponding frequency division value needs to be set for the frequency control register F0 in the DDS, and the specific calculation method is as follows:
wherein D is the specific frequency division value to be calculated, f0 is the reference signal frequency, f0 in the device is 10MHz, f is the sampling time signal frequency to be divided, and for the case that f is 1Hz (1 second) and 0.1Hz (10 seconds), the frequency division value D should be 248 × 10-7 or 248 × 10-8. The specific sampling time T is set by a user through PC end software according to the requirement in the actual sampling process, and the frequency division value is calculated by using a formula (4) after the single chip microcomputer communicates with the PC end through an RS232 serial interface to obtain the sampling time T set by the user. And the single chip microcomputer writes the frequency division value D into a corresponding buffer of the first DDS module according to the serial communication time sequence corresponding to the first DDS module to obtain a final sampling time signal T output of the first DDS module.
When the frequency of the detected signal is hundreds of mega even hundreds of mega hertz, considering the limit of the travel time counter to the detected frequency range, as shown in fig. 4, the second DDS frequency dividing unit includes a second isolation amplifier, a second DDS module, a travel time counter, a latch, a third DDS module, and a filtering module; the second isolation amplifier is respectively connected to the second DDS module and the third DDS module, the second DDS module, the first travel time counter and the first latch sequentially form signal connection, and the third DDS module is connected to the filtering module; and the external communication ports of the second DDS module and the third DDS module are respectively connected to the singlechip and used for receiving control word commands from the singlechip and carrying out bidirectional data transmission.
In the patent, a second DDS module is designed to carry out 1/100 frequency division processing on a frequency signal to be detected. The measured signal passes through the second isolation amplifier and then is directly sent to the external clock input end of the second DDS module to be used as a reference clock when the second DDS module works. And an external communication port of the second DDS module is connected to the singlechip, the singlechip writes 248 multiplied by 10 < -2 > frequency division values obtained according to the formula (4) into a buffer area of the second DDS module through a serial communication time sequence, sends 1/100 frequency division rate signals obtained by the second DDS module to the first travel time counter for coarse frequency measurement, and records the frequency value at the moment after the singlechip reads the value sampled by the first latch on the first travel time counter, and multiplies the frequency value by 100 to obtain a coarse frequency value F of the measured signal.
And the other path of tested signal passing through the second isolation amplifier is sent to an external clock input end of a third DDS module to be used as a reference clock when the third DDS module works. Meanwhile, an external communication port of the third DDS module is connected to the single chip microcomputer, and the single chip microcomputer calculates a frequency division value for communicating with the third DDS module according to the formula (4):
f is a coarse frequency value of a detected signal obtained through counting of the first travel time counter and calculation of the single chip microcomputer, 1MHz is adopted as F, the obtained specific frequency division value is written into a third DDS module cache region through a serial communication time sequence, a 1MHz frequency signal is obtained through the third DDS module, and the obtained frequency signal is sent to the low-pass filtering module to obtain a final 1MHz frequency signal to be output.
The compensation module is adapted to perform compensation control on the output error frequency of the VCXO module.
As shown in fig. 5, it may be preferable that: the compensation module comprises a first voltage reference module, a second voltage reference module, a D/A module and a temperature control module. The first voltage reference module is suitable for providing a stable voltage output to the VCXO module. The second voltage reference module is suitable for providing a stable voltage reference to be sent to an external voltage reference end of the D/A module. The temperature control module is arranged on the outer wall of the VCXO module and comprises a temperature control chip and a second thermistor, and the temperature control module is suitable for detecting the working temperature of the VCXO module and sending the result to the single chip microcomputer. The D/A module is suitable for outputting a direct current voltage value with variable size under the control of the single chip microcomputer and sending the direct current voltage value to the VCXO module.
As shown in FIG. 6, two of R and R1 are resistors with the same temperature coefficient, and their resistance should be chosen to be equal to Rk. Where the value of R1 reflects the actual VCXO operating ambient temperature T. Rk is a thermistor, which is attached to the surface of the VCXO to sense the actual working environment temperature T of the VCXO. Therefore, when the working environment temperature T of the VCXO is not changed, the bridge in the upper diagram is in balance, and the temperature compensation voltage value transmitted to the voltage-controlled transformation module is 0. Once the working environment temperature T of the VCXO changes, the resistance value of the thermistor Rk becomes smaller (temperature increases) or larger (temperature decreases), and then a voltage difference exists between the two ends of the bridge, which is differentially amplified by the operational amplifier a to become a temperature compensation voltage and transmitted to the voltage source, and the temperature compensation voltage is output to the conventional heating wire coil loop. The amplification gain of the whole circuit is adjusted by a negative feedback resistor Rw of the operational amplifier, wherein the Rw is a digital potentiometer, and the function of changing the compensation factor of the circuit is achieved by adjusting the resistance value of the Rw.
In the compensation module set, we performed component screening:
the voltage references 1 and 2 have the same temperature coefficient, that is, each time the temperature changes by 10C, the corresponding voltage reference value changes uniformly, for example: -1E-3 (V/0C).
According to the temperature characteristic curve of the VCXO, a specific operating temperature point of the VCXO is set by the single chip microcomputer, so that the VCXO has a temperature characteristic opposite to the 1 voltage reference around the operating point (if the above is a negative temperature coefficient, the VCXO is correspondingly selected to be a positive temperature coefficient), for example, specific values are selected as follows: +1E-10/0C, i.e., every 10C change in temperature, will cause the VCXO output signal frequency to change by + 1E-10.
In combination with the above 1, selecting a voltage-controlled slope value of the corresponding VCXO, for example, selecting 1E-7/V, since the voltage reference acts on the VCXO to output different frequencies, then in combination with 1, we can obtain an output signal frequency change rate caused by the voltage reference change caused by the corresponding temperature change acting on the VCXO as follows:
-1E-3(V/0C)×1E-7(V)＝-1E-10/0C
the VCXO with the smaller aging drift rate is selected, for example: 1E-6/year, converted into 365 days per year to obtain-2.7E-9/day.
As shown in fig. 7, where the portion of the curve (VCXO output) represents the frequency sampling curve of a conventional VCXO output. As can be seen from the graph portion, the VCXO outputs a large fluctuation point during the whole sampling process: an upper frequency fluctuation limit and a lower frequency fluctuation limit. This is extremely disadvantageous for some applications requiring strict absolute values of frequency, such as missile accurate guidance, GPS accurate navigation, etc. The specific compensation embodiment of this patent is as follows:
1. based on the conventional VCXO process, first, the VCXO, the voltage reference 1, and the voltage reference 2 are all operated at the operating temperature point required by the scheme, for example, T ═ 200C, then the VCXO will have a positive temperature coefficient +1E-10/0C, the voltage reference 1 and the voltage reference 2 will have a negative temperature coefficient-1E-3/0C, and the corresponding resulting VCXO output signal frequency change rate is: -1E-10/0C. During the normal operation of the VCXO, the internal operating module VCXO, the voltage reference 1, and the voltage reference 2 will be affected by the temperature fluctuation due to the limitation of the temperature control effect, but according to the implementation of the above solution 1, the positive frequency variation value of the VCXO caused by the temperature and the voltage reference caused by the temperature act on the negative frequency variation value of the VCXO to be neutralized to 0. The problem of VCXO output frequency variation caused by temperature variation is solved here.
2. The single chip microcomputer records the voltage-controlled slope data of the VCXO, establishes a relation of voltage and frequency, namely the expected values f1 and f2 in the graph are required to be realized, and the processor records corresponding voltage values V1 and V2. Here, VCXO output frequency control is achieved within a small range, i.e., within the desired value block shown in the implementation diagram.
3. In combination with the selected VCXO aging drift data: 2.7E-9/day, and voltage controlled slope value of VCXO: 1E-7/V, the singlechip carries out corresponding main adjustment on the deviation correcting voltage V according to the day, namely, the deviation correcting voltage V is added with a fixed correction value on the basis of the 2 technologies every day, such as: 27mV, which in turn causes the VCXO output frequency to increase by 1E-7/V27 mV + -2.7E-9, which compensates for the frequency variation effects of the VCXO due to aging drift. The solution here will lead to a better implementation of the above 2.
The frequency measuring instrument is suitable for measuring the time domain frequency of the signal frequency output by the normalization module according to the sampling time T being 10 seconds under the action of an external reference source clock, and sending the measuring result to an external computer.
As shown in fig. 8 and 9, it may be preferable that: the frequency measurement instrument includes a third isolation amplifier, a second travel time counter, a second latch, a fourth isolation amplifier, a third travel time counter, and a third latch. The third isolation amplifier, the second travel time counter and the second latch form signal connection in sequence; the fourth isolation amplifier, the third travel time counter and the third latch form signal connection in sequence; the third isolation amplifier and the fourth isolation amplifier are further connected to the single chip microcomputer respectively, controlled ends of the second travel time counter and the third travel time counter are connected to a control end of the single chip microcomputer respectively, and a reading end of the single chip microcomputer is further connected to the second latch and the third latch respectively.
And respectively transmitting a 1MHz frequency signal obtained by processing the frequency signal to be measured by the DDS frequency division unit and a 10MHz reference clock signal to a frequency measuring instrument. As shown in fig. 4 and 5, the single chip enables two paths of frequency signals to perform measurement according to a rising edge of a sampling time signal T obtained after a reference clock signal is processed by a first DDS module, specifically: and after the rising edge of a sampling signal T, when the rising edges of the detected signal and the external reference clock signal arrive, enabling the second travel time counter and the third travel time counter to count the frequency by the singlechip respectively. After the falling edge of a sampling signal T, when the rising edges of the detected signal and the external reference clock signal arrive, the singlechip enables the second travel time counter and the third travel time counter to finish frequency counting respectively, and meanwhile, the total pulse numbers N1 and N2 of the detected signal and the external reference clock signal in the time of a complete sampling signal T in the figure are obtained. And enabling the second latch and the third latch to latch the count values of the second travel time counter and the third travel time counter, respectively. If the frequency of the measured signal is Fx, the frequency of the reference time base is fo (actually 10MHz), and the counts of the counter on the measured signal and the reference time base are N1 and N2 respectively during the gate time T, then:
as can be seen from equation (5), the frequency fx of the measured signal is related to the reference clock fo and the count values N1, N2 of the two counters. In a complete sampling period T, the reading values N1, N2 of the second travel time counter and the third travel time counter stored by the second latch and the third latch are transmitted to the single chip microcomputer, and in formula (5), the reference clock source frequency fo is considered to be unchanged, namely 10MHz, so that the frequency value fx of the detected signal can be easily obtained.
The PLL unit is adapted to close-loop control the accuracy of the VCXO module output frequency by a precise signal frequency. Among them, it is preferable that: as shown in fig. 2, the PLL loop unit includes a PLL loop module, a pre-amplification module, a signal feedback module, and a final-amplification module, where a frequency signal obtained by the PLL loop module is amplified by the pre-amplification before being processed by the phase-lock demodulation to obtain a radio frequency signal, and the radio frequency signal is sent to the signal feedback module for processing.
The frequency signal output by the VCXO module is sent to the calibration module, and the signal frequency is corrected under the control of the single chip microcomputer and then output to the user side.
As for the signal feedback module, as shown in fig. 10, the pre-amplified signals are respectively input to the operational amplifiers a1 and A3, and the pre-amplified signals are sent to a2 after passing through A3. A4 and a5 are voltage followers whose outputs V11 and V12 have the same voltage amplitude as the voltages on the capacitors C1 and C2 (the effect of the added stage follower is to provide current support with this follower). V11 and V12 are respectively sent to the inverting terminal and the non-inverting terminal of A6, and N (V12-V11) operation is completed.
Wherein A1 and A4 complete the detection of the maximum peak value of the pre-amplified signal:
when the voltage of the front-stage amplified signal is greater than the voltage of the capacitor C1, a voltage drop occurs on the resistor Rf, and the current flows from left to right. According to the virtual break rule of the operational amplifier, D11 is not conducted. The charging current now goes through D12 to C1. When the voltage of the front-stage amplified signal is lower than the voltage of the capacitor C1, a voltage drop is generated on the resistor R2, and the current flows from right to left. According to the virtual break rule of the operational amplifier, D12 is not conducted, and the current only enters A1 through D11. Because the output voltage of the voltage follower A4 is the same as the voltage on the capacitor C1, the diode D11 is cut off, the capacitor can not discharge through the D11, and the voltage is protected, namely the capacitors C1 and A4 output V11 to record the maximum peak value of the pre-amplified signal. The capacitor C1 has a discharge resistor R1, and the discharge time constant τ of the RC is set according to the period of the actual pre-amplified signal, for example, when the frequency of the pre-amplified signal is 79Hz, τ is 1S. And simultaneously, the V11 is transmitted to the A/D sampling 1 to obtain a corresponding voltage value, and the voltage value is transmitted to the single chip microcomputer.
A3 completes the inversion of the pre-amplified signal:
the operational amplifier A3 firstly inverts the input pre-amplified signal, then superposes a negative amplitude direct current level Vref, and finally completes the high-low level conversion of the pre-amplified signal to obtain a signal output to the operational amplifier A2.
A2 and A5 complete detection of the minimum peak of the pre-amplified signal:
the pre-amplified signal is processed by A3 and sent to the non-inverting terminal of the operational amplifier a 2. Wherein the principles of a2 and a5 are as described above for a1 and A3, except that at this time, since the pre-amplified signal has already been processed by the op-amp A3, a2 and a5 perform detection of the minimum value of the pre-amplified signal. And simultaneously, the V12 is transmitted to the A/D sampling 2 to obtain a corresponding voltage value, and the voltage value is transmitted to the single chip microcomputer.
A6 completes the detection of peak-to-peak values:
the processed pre-amplified signals of high level V11 and low level V12 are respectively sent to a differential amplifier a6, and (V12-V11) × (Ry/Rx) is output by adjusting the ratio of Ry to Rx. And simultaneously, the voltage is transmitted to the A/D sampling 3 to obtain a corresponding voltage value and transmitted to the singlechip.
The amplitude characteristics of the frequency signals output by the pre-stage amplification signal module can be judged through the voltage values obtained by the A/ D sampling 1,2 and 3, and the signals are fed back to the final-stage amplification signal module through the single chip microcomputer to complete the synchronous phase discrimination. There is a very important technology here: actually, according to the main schematic diagram, we only process the obtained (V12-V11) × (Ry/Rx) information into the sum of the voltage-controlled voltage VX for correction and the conventional synchronous phase discrimination voltage VY, and then send the sum to the VCXO, where we remember (V12-V11) ═ VPPAnd (Ry/Rx) ═ K. Where K is an amplification gain which depends specifically on the ratio of the feedback gain Ry to Rx of the operational amplifier A6 in the signal feedback module，KVPPThe magnitude of the voltage-controlled voltage for correction applied to the VCXO is directly determined, so VX must be set according to the voltage-controlled slope of the specific VCXO and the magnitude of the voltage-controlled voltage VY for the conventional phase demodulation, and we generally obtain patent implementation benefits obtained by a scheme in which VX is VY/20 to VX is VY/10 magnitude or more:
the voltage-controlled voltage we apply to the VCXO according to the above principle is:
VY+VX＝VY+(V12-V11)*(Ry/Rx)＝VY+KVPP (6)
here, VY is the synchronous phase discrimination voltage control obtained by the traditional PLL phase-locked loop; k is the feedback gain of the signal feedback circuit (which is already fixed during design); vPPIs the peak-to-peak value of the pre-amplified signal.
In the same time domain frequency signal output system, as the frequency of the output signal becomes higher, the peak-to-peak value of the signal becomes smaller, as shown in the above figure. Therefore, when the frequency of the signal generated by the traditional PLL circuit becomes smaller, the peak-to-peak value of the obtained previous-stage signal becomes larger, and the voltage-controlled voltage VY + KV obtained by the embodiment of this patent becomes largerPPWill become larger (in practice V)PPBecomes larger) and the frequency of the signal output by the VCXO will become larger (because a positive slope VCXO is actually selected) after the VCXO is applied, thus performing the compensation function.
The present invention is not limited to the above embodiments, and the technical solutions of the above embodiments of the present invention may be combined with each other in a crossing manner to form a new technical solution, and all technical solutions formed by using equivalent substitutions fall within the scope of the present invention.
Claims (4)
1. A time domain signal measuring device based on a PLL (phase locked Loop) is characterized in that: the device comprises a normalization module, a VCXO module, a frequency measuring instrument, a single chip microcomputer, a compensation module and a PLL loop unit;
the VCXO module is suitable for outputting a high-stability external reference source clock signal, and the external reference source clock signal is respectively sent to the normalization module and the frequency measuring instrument;
the normalization module is suitable for performing normalization processing on the frequency signal to be measured under the action of the external reference source clock to obtain a standard frequency signal for 1MHz verification and outputting the frequency signal to the frequency measuring instrument;
the frequency measuring instrument is suitable for measuring the time domain frequency of the signal frequency output by the normalization module according to the sampling time T =10 seconds under the action of an external reference source clock, and sending the measuring result to an external computer;
the compensation module is suitable for performing compensation control on the output error frequency of the VCXO module;
the single chip microcomputer is suitable for performing parameter control on the normalization module, the frequency measuring instrument and the compensation module;
the PLL loop unit is suitable for controlling the accuracy of the output frequency of the VCXO module through accurate signal frequency closed-loop, the PLL loop unit comprises a PLL loop module, a preceding stage amplification module, a signal feedback module and a final stage amplification module, and before synchronous phase discrimination processing, a frequency signal obtained by the PLL loop module is amplified by the preceding stage amplification module to obtain a radio frequency signal which is sent to the signal feedback module for processing;
the single chip microcomputer obtains relevant parameter information of the radio frequency signal through accessing the signal feedback module, the relevant parameter information comprises a maximum amplitude value, a minimum amplitude value and a peak-to-peak value of the signal, the parameter of the pre-stage amplification signal sent to the final-stage amplification module is repaired under the control of the single chip microcomputer, and the synchronous phase discrimination function of the traditional PLL is completed;
after the synchronous phase discrimination, the voltage-controlled voltage signal is obtained and then used for the VCXO module to complete the PLL phase-locked loop.
2. The PLL phase locked loop based time domain signal measuring apparatus of claim 1, wherein:
the normalization module comprises a first isolation amplifier, a first DDS module and a second DDS frequency division rate unit, a reference frequency signal f0 of the external reference source clock passes through the first isolation amplifier and then is sent to an external clock input end of the first DDS module to serve as a working external reference clock of the first DDS module, and an external communication port of the first DDS module is connected to the single chip microcomputer and used for receiving control word commands from the single chip microcomputer and carrying out bidirectional data transmission;
the second DDS frequency division unit comprises a second isolation amplifier, a second DDS module, a travel time counter, a latch, a third DDS module and a filtering module; the second isolation amplifier is respectively connected to the second DDS module and a third DDS module, the second DDS module, the first travel time counter and the first latch sequentially form signal connection, and the third DDS module is connected to the filtering module; and the external communication ports of the second DDS module and the third DDS module are respectively connected to the singlechip and used for receiving control word commands from the singlechip and carrying out bidirectional data transmission.
3. The PLL phase locked loop based time domain signal measuring apparatus of claim 2, wherein: the frequency measuring instrument comprises a third isolation amplifier, a second travel time counter, a second latch, a fourth isolation amplifier, a third travel time counter and a third latch; the third isolation amplifier, the second travel time counter and the second latch form signal connection in sequence; the fourth isolation amplifier, the third travel time counter and the third latch form signal connection in sequence; the third isolation amplifier and the fourth isolation amplifier are further respectively connected to the single chip microcomputer, controlled ends of the second travel time counter and the third travel time counter are respectively connected to a control end of the single chip microcomputer, and a reading end of the single chip microcomputer is further respectively connected to the second latch and the third latch.
4. The PLL phase locked loop based time domain signal measuring apparatus of claim 3, wherein: the compensation module comprises a first voltage reference module, a second voltage reference module, a D/A module and a temperature control module;
the first voltage reference module is suitable for providing a stable voltage output to the VCXO module;
the second voltage reference module is suitable for providing a stable voltage reference and sending the stable voltage reference to an external voltage reference end of the D/A module;
the temperature control module is arranged on the outer wall of the VCXO module and comprises a temperature control chip and a thermistor, and the temperature control module is suitable for detecting the working temperature of the VCXO module and sending the result to the single chip microcomputer;
the D/A module is suitable for outputting a direct current voltage value with variable size under the control of the single chip microcomputer and sending the direct current voltage value to the VCXO module.
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