CN105915215A - Frequency phase-locked loop PLL generation apparatus - Google Patents
Frequency phase-locked loop PLL generation apparatus Download PDFInfo
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- CN105915215A CN105915215A CN201610046457.5A CN201610046457A CN105915215A CN 105915215 A CN105915215 A CN 105915215A CN 201610046457 A CN201610046457 A CN 201610046457A CN 105915215 A CN105915215 A CN 105915215A
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- frequency
- phase
- locked loop
- frequency synthesizer
- generating means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
The invention relates to a frequency phase-locked loop PLL generation apparatus. The apparatus comprises a voltage controlled temperature compensated crystal oscillator, a direct digital frequency synthesizer (DDS), a filter circuit, a frequency divider, a phase-locked loop frequency synthesizer, a digital power attenuator and an impedance matching circuit which are successively connected, and further comprises a controller. According to the invention, through selecting an integrated chip ADF4350 with small volume and high integration for the phase-locked loop frequency synthesizer, the complete low-noise, low-loss, high-stability and high-reliability phase-locked loop frequency synthesizer can be formed simply through additional arrangement of a loop filter yet without external connection with a voltage controlled oscillator. The DDS is employed as a reference source for driving the phase-locked loop frequency synthesizer, and then through combination with the programmable digital power attenuator and the impedance matching circuit, a high-stability, high-resolution, fast-frequency-hopping-speed, low-phase-noise and small-step-scanning pulse microwave source for Ramsey-CPT atom frequency marking can be realized.
Description
Technical field
The present invention relates to field of atomic frequency standard, be specifically related to a kind of frequency phase lock ring PLL generating means.
Background technology
Coherent Population Trapping imprison (Coherent Population Trapping, CPT) it is a kind of New type atom frequency marking utilizing atom and coherent laser to interact produced a kind of quantum interference phenomenon and realizing, also it is the atomic frequency standard that uniquely can realize miniaturization at present from principle, its volume, power dissipation ratio Hydrogen Atom Frequency Standard, gorgeous atomic frequency standard, little, even the most much smaller compared with the Rb atom frequency marking that current volume, power consumption are minimum.
But, limited owing to being widened by atomic spectral line Doppler, the live width of atomic spectrum is wider, the degree of stability causing CPT atomic frequency standard is on the low side, to this end, the Ramsey sepavated oscillatory field technique of time domain can be combined with CPT phenomenon, thus obtain that live width is narrower, signal to noise ratio more preferably Ramsey-CPT interference spectrum, using this spectral line as microwave frequency discrimination signal, it is possible to achieve degree of stability higher Ramsey-CPT atomic frequency standard.
CPT atomic frequency standard uses continuous laser and the working method of atomic interaction, and Ramsey-CPT atomic frequency standard uses pulse laser and the working method of atomic interaction, but current existing Ramsey-CPT atomic frequency standard acousto-optic modulator (AOM) produces pulse laser as photoswitch, owing to AOM volume is relatively big, power consumption is higher, limit Ramsey-CPT atomic frequency standard to miniaturization and the development in low-power consumption atomic frequency standard direction.
Additionally, Ramsey-CPT atomic frequency standard is with rubidium 85 for work atom, employing overall with is modulated, its frequency lock procedure requires microwave source frequency centered by 3.035 732 439 GHz, in small frequency ranges, small step length is scanned and obtains a Ramsey-CPT peak-to-peak signal, by control circuit microwave frequency is locked at the maximum at the narrowest Ramsey-CPT peak of live width, thus realizes the closed loop locking of atomic frequency standard.Obviously, Ramsey-CPT atomic frequency standard is the highest to the requirement of microwave source precision and volume, so needing to design high-performance, the pulse microwave source of small size.
At present, for Ramsey-CPT atomic frequency standard microwave source, design mainly has 1) phaselocked loop (PLL) scheme;2) injected locking ring scheme;3) local oscillator (LO) scheme.Wherein, PLL scheme is satisfied by designing requirement at phase noise and the aspect such as spuious, it it is the most ripe design, Symmetricom and Kernco is the producer of only CPT atomic frequency standard commercialization of present stage in the world, they all use PLL scheme, but the volume of microwave source and power consumption are bigger than normal, " in order to solve the problem of volume and power consumption, injected locking ring scheme and LO scheme are the most constantly applied in CPT atomic frequency standard.LO scheme uses the dielectric oscillator (DRO) that volume is the least directly to produce high-frequency signal, at volume and realize having in complexity advantage, but phase noise aspect is poorer than first two scheme. and in general, atomic frequency standard needs to produce the standard output frequency of low frequency, this is accomplished by adding complicated fractional frequency division circuit, largely reduces the advantage of LO small size.
Summary of the invention
The technical problem to be solved in the present invention is: propose the pulse microwave source of a kind of high-performance, miniaturization.
The present invention solves that the technical scheme that above-mentioned technical problem proposes is: a kind of frequency phase lock ring PLL generating means, including the voltage controlled temperature compensated crystal oscillator being sequentially connected with, Direct Digital Frequency Synthesizers, filter circuit, frequency divider, phase-locked loop frequency synthesizer, digital power attenuator and impedance matching circuit, also include controller；
The end that controls of described controller is connected to described Direct Digital Frequency Synthesizers, described frequency divider, phase-locked loop frequency synthesizer and the controlled end of described digital power attenuator.
Further, described phase-locked loop frequency synthesizer is to be made up of integrated chip ADF4350 and peripheral circuit, and the peripheral circuit of described integrated chip ADF4350 includes linear voltage regulator LP5900SD and external loop filter.
Further, the output frequency of described voltage controlled temperature compensated crystal oscillator is 10MHz.
Further, described Direct Digital Frequency Synthesizers is to be made up of integrated chip AD9954 and peripheral circuit, the peripheral circuit of described AD9954 includes regulated power supply LP3878MR-ADJ and low pass filter, described AD9954 frequency control word is 32, work clock is 10MHz, the frequency resolution f=10 x 106/232=0.0023 Hz of output clock.AD9954 phase control words is 14, and the phase resolution of output clock is 3600/214=0.0220.
Further, described digital power attenuator is programmable digital power attenuator.
The invention has the beneficial effects as follows:
The present invention is by selecting the integrated chip ADF4350 of phase-locked loop frequency synthesizer that volume is little, integrated level is high so that it is need not external voltage controlled oscillator only needs an additional loop filter to can be formed by a complete low noise, low-power consumption, high stability, the phase-locked loop frequency synthesizer of high reliability.Direct Digital Frequency Synthesizers (DDS) is used to drive phase-locked loop frequency synthesizer as reference source, in conjunction with programmable digital power attenuator and impedance matching circuit, thus realize the pulse microwave source using Ramsey-CPT atomic frequency standard of high stability, high-resolution, fast frequency hopping speed, low phase noise, little step scan.
Accompanying drawing explanation
Below in conjunction with the accompanying drawings the frequency phase lock ring PLL generating means of the present invention is described further.
Fig. 1 is the structured flowchart of medium frequency phase-locked loop pll generating means of the present invention；
Fig. 2 is the circuit structure diagram of low pass filter.
Detailed description of the invention
According to Fig. 1 and Fig. 2, frequency phase lock ring PLL generating means in the present invention, including the voltage controlled temperature compensated crystal oscillator (VCTCXO) being sequentially connected with, Direct Digital Frequency Synthesizers (DDS), filter circuit, frequency divider, phase-locked loop frequency synthesizer (PLL), digital power attenuator and impedance matching circuit, also include controller.
The end that controls of controller is connected to Direct Digital Frequency Synthesizers, frequency divider, phase-locked loop frequency synthesizer and the controlled end of numeral power attenuator.
In the present invention, use phase noise, humorous miscellaneous suppression all well voltage controlled temperature compensated crystal oscillator VCTCXO as the reference clock source of DDS, by microcontroller, frequency control word and phase control words being write in the depositor within DDS, DDS just can produce the analog sine output of a frequency and phase place PLC technology；Then using the output signal of DDS as the reference signal of PLL, set frequency dividing ratio N of frequency divider, just obtained the clock signal that frequency is DDS output frequency N/R times；The microwave signal of impulse form is realized by programmable digital power attenuator, then through impedance matching circuit, finally according to desired output pulsed microwave signals.This structure utilizes the high-resolution of DDS to ensure that sufficiently small frequency step, and the part during the bandpass characteristics of PLL inhibits DDS output spectrum well simultaneously is spuious.
Achieve the mutual supplement with each other's advantages of DDS and PLL, take into account the performance of various aspects.So the pulse microwave source that this scheme realizes has small size, upper frequency, very fast frequency conversion speed and a feature of upper frequency resolution, the system that simultaneously ensure that the most well is spuious and phase noise performance.
Phase-locked loop frequency synthesizer is to be made up of integrated chip ADF4350 and peripheral circuit, and the peripheral circuit of integrated chip ADF4350 includes linear voltage regulator LP5900SD and external loop filter.
The output frequency of voltage controlled temperature compensated crystal oscillator is 10MHz.
Direct Digital Frequency Synthesizers is to be made up of integrated chip AD9954 and peripheral circuit, the peripheral circuit of AD9954 includes regulated power supply LP3878MR-ADJ and low pass filter, AD9954 frequency control word is 32, work clock is 10MHz, the frequency resolution f=10 x 106/232=0.0023 Hz of output clock.AD9954 phase control words is 14, and the phase resolution of output clock is 3600/214=0.0220.
Can be as preferably: digital power attenuator is programmable digital power attenuator.
The present invention is not limited to above-described embodiment, and the technical scheme of each embodiment above-mentioned of the present invention can form new technical scheme with combined crosswise each other, and the technical scheme that the most all employing equivalents are formed all falls within the protection domain of application claims.
Claims (5)
1. a frequency phase lock ring PLL generating means, it is characterized in that: include voltage controlled temperature compensated crystal oscillator, Direct Digital Frequency Synthesizers, filter circuit, frequency divider, phase-locked loop frequency synthesizer, digital power attenuator and the impedance matching circuit being sequentially connected with, also include controller；
The end that controls of described controller is connected to described Direct Digital Frequency Synthesizers, described frequency divider, phase-locked loop frequency synthesizer and the controlled end of described digital power attenuator.
Frequency phase lock ring PLL generating means the most according to claim 1, it is characterized in that: described phase-locked loop frequency synthesizer is to be made up of integrated chip ADF4350 and peripheral circuit, and the peripheral circuit of described integrated chip ADF4350 includes linear voltage regulator LP5900SD and external loop filter.
Frequency phase lock ring PLL generating means the most according to claim 2, it is characterised in that: the output frequency of described voltage controlled temperature compensated crystal oscillator is 10MHz.
Frequency phase lock ring PLL generating means the most according to claim 3, it is characterized in that: described Direct Digital Frequency Synthesizers is to be made up of integrated chip AD9954 and peripheral circuit, the peripheral circuit of described AD9954 includes regulated power supply LP3878MR-ADJ and low pass filter, described AD9954 frequency control word is 32, work clock is 10MHz, the frequency resolution f=10 x 106/232=0.0023 Hz of output clock, AD9954 phase control words is 14, and the phase resolution of output clock is 3600/214=0.0220.
Frequency phase lock ring PLL generating means the most according to claim 4, it is characterised in that: described digital power attenuator is programmable digital power attenuator.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610046457.5A CN105915215A (en) | 2016-01-25 | 2016-01-25 | Frequency phase-locked loop PLL generation apparatus |
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| CN201610046457.5A CN105915215A (en) | 2016-01-25 | 2016-01-25 | Frequency phase-locked loop PLL generation apparatus |
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| CN201610046457.5A Pending CN105915215A (en) | 2016-01-25 | 2016-01-25 | Frequency phase-locked loop PLL generation apparatus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741523A (en) * | 2017-09-07 | 2018-02-27 | 江汉大学 | A kind of time-domain signal measurement apparatus based on PLL phaselocked loops |
| CN108566201A (en) * | 2018-07-24 | 2018-09-21 | 成都意科科技有限责任公司 | A kind of high frequency resolution pulse digit generating system |
| CN111934843A (en) * | 2020-07-31 | 2020-11-13 | 深圳市智绘科技有限公司 | Multi-sensor data synchronous acquisition method for intelligent unmanned system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055473A (en) * | 2010-12-23 | 2011-05-11 | 中国科学院武汉物理与数学研究所 | CPT (coherent population trapping) atomic frequency standard based frequency synthesis system |
| CN102075187A (en) * | 2011-02-22 | 2011-05-25 | 合肥威师智能电子电器厂 | Cpt atomic clock servo circuit |
| CN203119874U (en) * | 2013-02-01 | 2013-08-07 | 江汉大学 | Ramsey-CPT (Coherent Population Trapping) pulse signal source device |
| CN203708219U (en) * | 2014-02-21 | 2014-07-09 | 成都天奥电子股份有限公司 | 3.4G digital phase-locking frequency multiplier for CPT clock |
-
2016
- 2016-01-25 CN CN201610046457.5A patent/CN105915215A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055473A (en) * | 2010-12-23 | 2011-05-11 | 中国科学院武汉物理与数学研究所 | CPT (coherent population trapping) atomic frequency standard based frequency synthesis system |
| CN102075187A (en) * | 2011-02-22 | 2011-05-25 | 合肥威师智能电子电器厂 | Cpt atomic clock servo circuit |
| CN203119874U (en) * | 2013-02-01 | 2013-08-07 | 江汉大学 | Ramsey-CPT (Coherent Population Trapping) pulse signal source device |
| CN203708219U (en) * | 2014-02-21 | 2014-07-09 | 成都天奥电子股份有限公司 | 3.4G digital phase-locking frequency multiplier for CPT clock |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741523A (en) * | 2017-09-07 | 2018-02-27 | 江汉大学 | A kind of time-domain signal measurement apparatus based on PLL phaselocked loops |
| CN107741523B (en) * | 2017-09-07 | 2020-01-07 | 江汉大学 | Time domain signal measuring device based on PLL |
| CN108566201A (en) * | 2018-07-24 | 2018-09-21 | 成都意科科技有限责任公司 | A kind of high frequency resolution pulse digit generating system |
| CN111934843A (en) * | 2020-07-31 | 2020-11-13 | 深圳市智绘科技有限公司 | Multi-sensor data synchronous acquisition method for intelligent unmanned system |
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