CN204465511U - A kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider - Google Patents
A kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider Download PDFInfo
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- CN204465511U CN204465511U CN201520264478.5U CN201520264478U CN204465511U CN 204465511 U CN204465511 U CN 204465511U CN 201520264478 U CN201520264478 U CN 201520264478U CN 204465511 U CN204465511 U CN 204465511U
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Abstract
The utility model discloses a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider, comprises program control frequency division PFD phase discriminator, single-chip microcomputer, display module, Independent keys module, low-pass filtering module, VCXO module, frequency-doubled signal buffered feedback and output module, high-pass filtering module, impedance matching module, reference clock buffer module, clock signal input module, the utility model adopts single-chip microcomputer as microcontroller center, using the frequency synthesis chip ADF4106 with phase demodulation and program control division function as frequency synthesis center, by low-pass filter circuit and high frequency, low noise VCXO VCXO produces frequency-doubled signal, cushion constrained input signal with clock buffer chip ADCLK905 and ADCLK925 and realize frequency-doubled signal and export, then realize data display respectively by TFT LCD MODULE and Independent keys module to arrange with user, structure is simple, circuit stability, wide range of frequencies signal can be realized export, phase noise is low, practical.
Description
Technical field
The utility model relates to a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider, belongs to radio communication electronic technology field.
Background technology
High frequency signal generator has in electron trade to be applied extremely widely, and it mainly can be divided into two classes, and a class is amplitude adjusted, and another kind of is frequency adjustment, and the utility model relates generally to frequency adjustment direction.Frequency adjustment all has extremely important application in analog circuit and digital circuit, and these analog circuits and digital circuit are the bases forming various system.Such as, radio communication, radar, radio, single-chip microcomputer and DSP Digital Signal Processing clock, sweep generator etc.Testing LCR(inductance, electric capacity, resistance) network time just need sweep generator, its principle is exactly the signal frequency by changing the tested network of input, tests out the resistive of LCR network, inductive and capacitive character.Resistive main manifestations is the inhibition to the signal of telecommunication, and inductive and capacitive character main manifestations are the time delayed action to signal.And in radio communication direction, by the change frequency of wide region thus the modulation and demodulation signal launching or receive, have extremely important effect for the interference free performance improving signal transmission.High Performance SCM (MCU) and digital signal processing chip (DSP) have strict requirement to clock, in order to reach high-performance, need high-frequency, low phase noise clock signal.
Low phase noise, wide range of frequencies output device have many different implementations, and traditional high performance frequency output device is in order to improve reference frequency output and reduce signal phase noise, often complex circuit designs, bulky, expensive.In some applications, often need the high performance frequency synthesizer of some low costs, this is current problem in urgent need to solve.
Utility model content
Technical problem to be solved in the utility model is: for the defect of prior art, the utility model is the program control frequency doubling device based on PLL phase-locked loop and frequency divider, adopt single-chip microcomputer as microcontroller center, using the frequency synthesis chip ADF4106 with phase demodulation and program control division function as frequency synthesis center, by low-pass filter circuit and high frequency, low noise VCXO VCXO produces frequency-doubled signal, cushion constrained input signal with clock buffer chip ADCLK905 and ADCLK925 and realize frequency-doubled signal and export, then realize data display respectively by TFT LCD MODULE and Independent keys module to arrange with user, structure is simple, circuit stability, wide range of frequencies signal can be realized export, phase noise is low, practical.
Technical solutions of the utility model are as follows:
Based on a program control frequency doubling device for PLL phase-locked loop and frequency divider, comprise program control frequency division PFD phase discriminator, single-chip microcomputer, display module, Independent keys module, low-pass filtering module, VCXO module, frequency-doubled signal buffered feedback and output module, high-pass filtering module, impedance matching module, reference clock buffer module, clock signal input module;
Described single-chip microcomputer is connected with display module, Independent keys module, program control frequency division PFD phase discriminator respectively;
Described clock signal input module, reference clock buffer module, impedance matching module, high-pass filtering module, program control frequency division PFD phase discriminator, low-pass filtering module, VCXO module, frequency-doubled signal buffered feedback are connected successively with output module;
Described frequency-doubled signal buffered feedback and output module are also connected with program control frequency division PFD phase discriminator.
As further prioritization scheme of the present utility model, described reference input clock buffer module is based on ADCLK905 chip.
As further prioritization scheme of the present utility model, described frequency-doubled signal buffered feedback and output module are based on ADCLK925 chip.
As further prioritization scheme of the present utility model, describedly program controlly ADF4106 chip can be adopted by frequency division PFD phase discriminator.
As further prioritization scheme of the present utility model, described single-chip microcomputer adopts MSP430F5529 single-chip microcomputer.
As further prioritization scheme of the present utility model, described display module adopts TFT LCD.
As further prioritization scheme of the present utility model, the circuit of program control frequency doubling device comprises active crystal oscillator chip, clock buffer modules A DCLK905 chip, VCXO SARONIX chip, program control frequency division PFD phase discriminator ADF4106 chip, frequency-doubled signal buffered feedback and output module ADCLK925 chip, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, 9th resistance, tenth resistance, 11 resistance, 12 resistance, 13 resistance, 14 resistance, 15 resistance, 16 resistance, 17 resistance, first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, 11 electric capacity,
The output of described active crystal oscillator is connected with the 16 pin with one end of the first electric capacity, one end of the second electric capacity, the 15 pin of ADCLK905 chip respectively, and the other end of described first electric capacity connects the first pin of ADCLK905 chip;
11 pin of described ADCLK905 chip connects one end of the 4th electric capacity, one end of the 3rd resistance respectively, and the other end of described 4th electric capacity connects one end of the 4th resistance, the other end of described 3rd resistance, the equal ground connection of the other end of the 4th resistance;
12 pin of described ADCLK905 chip connects one end of the 3rd electric capacity, one end of the first resistance respectively, the other end ground connection of described first resistance, the other end of described 3rd electric capacity connects one end of the second resistance, one end of the 5th electric capacity, the other end ground connection of described second resistance respectively;
The other end of described 5th electric capacity connects the 8th pin of ADF4106 chip, and the first pin of described ADF4106 chip connects one end of the 5th resistance, the other end ground connection of described 5th resistance;
Second pin of described ADF4106 chip connects one end of the 8th resistance, one end of the 7th electric capacity, one end of the 6th electric capacity respectively, the other end of described 7th electric capacity connects one end of the 7th resistance, the other end of described 6th electric capacity, the equal ground connection of the other end of the 7th resistance;
The other end of described 8th resistance connects the first pin of SARONIX chip, one end of the 8th electric capacity, the other end ground connection of described 8th electric capacity respectively;
Tenth pin of described ADF4106 chip connects one end of the 6th resistance, and the other end of described 6th resistance connects voltage;
5th pin of described ADF4106 chip connects one end of the 14 electric capacity, the other end of described 14 electric capacity connects one end of the 17 resistance, 6th pin of described ADF4106 chip connects one end of the 13 electric capacity, and the other end of described 13 electric capacity connects one end of the 16 resistance;
The described other end of the 16 resistance, the other end of the 17 resistance connect the 9th pin, the tenth pin of ADCLK925 chip respectively, 9th pin of described ADCLK925 chip, the tenth pin also connect one end of the 15 resistance, one end of the 14 resistance respectively, the described other end of the 15 resistance, the equal ground connection of the other end of the 14 resistance;
First pin of described ADCLK925 chip connects one end of the 9th electric capacity, and the other end of described 9th electric capacity connects the 4th pin of SARONIX chip; Second pin of described ADCLK925 chip connects one end of the tenth electric capacity, the 15 pin of ADCLK925 chip and the 16 pin respectively, the other end ground connection of described tenth electric capacity;
12 pin of described ADCLK925 chip connects one end of the 9th resistance, one end of the 11 resistance respectively, the other end of described 11 resistance connects one end of the 12 electric capacity, the other end of described 12 electric capacity connects P1, P1 ground connection, the other end ground connection of described 9th resistance;
11 pin of described ADCLK925 chip connects one end of the tenth resistance, one end of the 12 resistance respectively, one end that the other end connects one end of the 11 electric capacity, the other end of the 11 electric capacity connects the 13 resistance of described 12 resistance, the described other end of the tenth resistance, the other end ground connection of the 13 resistance.
The utility model adopts above technical scheme compared with prior art, has following technique effect:
The utility model adopts single-chip microcomputer as microcontroller center, using the frequency synthesis chip ADF4106 with phase demodulation and program control division function as frequency synthesis center, by low-pass filter circuit and high frequency, low noise VCXO VCXO produces frequency-doubled signal, cushion constrained input signal with clock buffer chip ADCLK905 and ADCLK925 and realize frequency-doubled signal and export, then realize data display respectively by TFT LCD MODULE and Independent keys module to arrange with user, structure is simple, circuit stability, wide range of frequencies signal can be realized export, phase noise is low, practical.
the beneficial effects of the utility model
The utility model is the program control frequency doubling device based on PLL phase-locked loop and frequency divider, adopt single-chip microcomputer as microcontroller center, using the frequency synthesis chip ADF4106 with phase demodulation and program control division function as frequency synthesis center, by low-pass filter circuit and high frequency, low noise VCXO VCXO produces frequency-doubled signal, cushion constrained input signal with clock buffer chip ADCLK905 and ADCLK925 and realize frequency-doubled signal and export, then realize data display respectively by TFT LCD MODULE and Independent keys module to arrange with user, structure is simple, circuit stability, wide range of frequencies signal can be realized export, phase noise is low, practical.
Accompanying drawing explanation
Fig. 1 is system principle diagram of the present utility model.
Fig. 2 is reference input clock buffer module circuit diagram of the present utility model.
Fig. 3 is impedance matching of the present utility model and high-pass filtering module circuit diagram.
Fig. 4 be of the present utility model program control can frequency division PFD phase discriminator and low-pass filtering VCO module circuit diagram.
Fig. 5 is frequency-doubled signal buffered feedback of the present utility model and output module circuit diagram.
Fig. 6 is TFT LCD MODULE circuit diagram of the present utility model.
Fig. 7 is Independent keys module circuit diagram of the present utility model.
Fig. 8 is main control singlechip circuit diagram of the present utility model.
Embodiment
Be described below in detail execution mode of the present utility model, the example of described execution mode is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the execution mode be described with reference to the drawings, only for explaining the utility model, and can not being interpreted as restriction of the present utility model.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, and all terms used herein (comprising technical term and scientific terminology) have the meaning identical with the general understanding of the those of ordinary skill in field belonging to the utility model.Should also be understood that those terms defined in such as general dictionary should be understood to have the meaning consistent with the meaning in the context of prior art, unless and define as here, can not explain by idealized or too formal implication.
As Fig. 1, the utility model discloses a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider, comprises program control frequency division PFD phase discriminator, single-chip microcomputer, display module, Independent keys module, low-pass filtering module, VCXO module, frequency-doubled signal buffered feedback and output module, high-pass filtering module, impedance matching module, reference clock buffer module, clock signal input module;
Described single-chip microcomputer is connected with display module, Independent keys module, program control frequency division PFD phase discriminator respectively;
Described clock signal input module, reference clock buffer module, impedance matching module, high-pass filtering module, program control frequency division PFD phase discriminator, low-pass filtering module, VCXO module, frequency-doubled signal buffered feedback are connected successively with output module;
Described frequency-doubled signal buffered feedback and output module are also connected with program control frequency division PFD phase discriminator.
As Fig. 2, show the circuit of reference input clock buffer module, based on clock buffer chip ADCLK905.Figure is left, the active crystal oscillator of 10MHz is as the input clock signal of this device, 1 pin of active crystal oscillator U0 does not connect, 2 pin meet GND, 4 pin meet VCC_3.3V, 3 pin 10Mhz signals export and connect C1 electric capacity one end, and 1 pin of another termination ADCLK905 chip of C1 electric capacity U1, C1 electric capacity serves the effect of isolated DC voltage herein.3 pin of ADCLK905 chip U0,4 pin, 5 pin, 6 pin, 9 pin and 10 pin do not connect, 7 pin, 14 pin meet GND, 8 pin, 14 pin meet VCC_3.3V, and 2 pin, 15 pin and 16 pin are by an electric capacity C2 ground connection, C2 is mainly used in absorbing the small-signal on GND, and chip operation is stablized, and this is extremely important for high frequency chip, 12 pin and 11 pin are respectively 10MHz signal and its complementation (10MHz signal phase postpones 180 degree) and export, access OUT1 and
the network port.ADCLK905 for reducing the randomized jitter of input ADF4106 chip U2 signal, and improves the slew rate of input signal.Concrete, the minimum input signal slew rate of ADF4106 chip is 50V/
μs(volt/delicate), and the slew rate of 10MHz 0dBm sine wave only has 20V/
μs.
As Fig. 3, specifically show the circuit of impedance matching and high-pass filtering module, be made up of discrete component (resistance and electric capacity).The signal of reference input clock buffer module export OUT1 with
the network port, termination coupling and high-pass filtering module, OUT1 input signal first meets GND by R1, connect C3 electric capacity again, C3 connect R2 resistance draw to GND, OUT2 port from electric capacity C3 one end that access is program control can frequency division PFD phase discriminator and low-pass filtering VCO module, same
input signal first meets GND by R3 resistance, then connects C4 electric capacity, and C4 connects R4 resistance to GND.R1, C3, R2 are respectively 150 Ω, 10nF, 51 Ω, R3, C4, R4 are also respectively 150 Ω, 10nF, 51 Ω, R2 is for mating the impedance between output OUT2 and transmission line OUT1 to OUT2, and R1 is for absorbing the ripple of returning from line reflection, C3 and R2 constitutes single order high pass filter again indirectly, cut-off frequency is: f=1/C3/R2=2MHz, for filtering low frequency spur.
As Fig. 4, show program control can the circuit of frequency division PFD phase discriminator and low-pass filtering VCO module, based on program control can frequency division PFD phase discriminator ADF4106 chip and VCXO SARONIX-300.000.1 pin of ADF4106 chip U2 is by R5 grounding through resistance, and 3 pin, 4 pin and 9 pin meet GND simultaneously, 6 pin and 5 pin respectively by C13 and C14 electric capacity connect OUT3 and
port, 8 pin were connected electric capacity C5 and were connect OUT2 port, 7 pin meet VCC_3.3V, 15 pin meet VCC_3.3V, 16 pin meet VCC_5V, 10 pin meet VCC_3.3V by R6 resistance, 11 pin, 12 pin, 13 pin and 14 pin are the programming port CLK of ADF4106 chip U2, DATA, LE and MT, meet the P3.3 of single-chip microcomputer respectively, P3.2, P3.1 and P3.0 mouth, 2 pin are that charge pump exports, connect C6 electric capacity to GND, C7 electric capacity R7 resistance in parallel is to GND, R8 resistance C8 electric capacity in parallel is to GND, the voltage-controlled end of 1 pin of C8 and R8 tip node output voltage access SARONIX-300.000, C6 is 680pF, C7 is 10nF, R7 is 43 Ω, C8 is 1nF, R8 is 910 Ω, constituting cut-off frequency is that 3 of 1MHz connects low pass filter, 2 pin and 3 pin of SARONIX-300.000 meet GND, it is sinusoidal wave that 4 pin VCXOUT export 10 to 300MHz, 5 pin do not connect, 6 pin meet VCC_5V.The 1 pin control voltage of SARONIX-300.000 is 0-5V, 2.5V ± 2.5V, and when 1 pin floating does not connect, voltage is the output of 2.5V, ADF4106 charge pump is ± 5mA, and after current-voltage low pass filter, generation ± 5V voltage superposition is on 1 pin primary voltage 2.5V.
As Fig. 5, show the circuit of frequency-doubled signal buffered feedback and output module, based on clock buffer chip ADCLK925.ADCLK925 is for reducing the randomized jitter of input ADF4106 chip U2 signal, and the slew rate improving input signal is to more than 320V/us, be different from ADCLK905, ADCLK925 is doubleway output, one tunnel by signal feedback to ADF4106, another road directly exports, and reduces the impact of output signal on feedback signal greatly, makes system more stable.Concrete, VCXO output VCXOUT connects C9 electric capacity one end, and 1 pin of another termination ADCLK925 chip of C9 electric capacity U4, C9 electric capacity serves the effect of isolated DC voltage herein.3 pin of ADCLK925 chip U4, 4 pin, 5 pin and 6 pin do not connect, 7 pin, 14 pin meet GND, 8 pin, 14 pin meet VCC_3.3V, and 2 pin, 15 pin and 16 pin are by an electric capacity C10 ground connection, C10 is mainly used in absorbing the small-signal on GND, chip operation is stablized, this is extremely important for high frequency chip, 10 pin and 9 pin are respectively signal and export and the output of its complementary signal, 10 pin connect R14 resistance to GND, then connect R17 resistance to program control can the input port OUT3 of frequency division PFD phase discriminator and the voltage-controlled module of low-pass filtering, same, 9 pin connect R15 resistance to GND, then connect R16 resistance to program control can the input port of frequency division PFD phase discriminator and low-pass filtering VCO module
, R14 and R15 resistance is 150 Ω, for impedance matching, R16 and R17 resistance is the amplitudes of 30 Ω for reducing output signal, meet ADF4106 chip U2 to the requirement of input signal, 12 pin are identical with 9 pin output signals with 10 pin with 11 pin, 11 pin connect R10 resistance to GND, then R12 resistance one end is connect, another termination C11 electric capacity of R12 is to R13 resistance to GND, 12 pin connect R9 resistance to GND, then R11 resistance one end is connect, another termination C12 electric capacity of R11 exports to P1 mouth, P1 mouth is frequency-doubled signal output, R9 and R10 resistance is 150 Ω, R11 and R12 resistance is 30 Ω, R13 resistance is 51 Ω, it is equal that value used is mated in these resistance values and 10 pin and 9 pin output impedance, chip operation is stablized.
As Fig. 6, 1 pin VCC of TFT LCD MODULE meets VCC_3.3V, 2 pin meet GND, TFT LCD MODULE 3 pin RST connects MSP430F5529 single-chip microcomputer P2.0 mouth, 4 pin CS connect single-chip microcomputer P2.1 mouth, 5 pin RD connect single-chip microcomputer P2.2 mouth, 6 pin WR connect single-chip microcomputer P2.3 mouth, 7 pin RS connect single-chip microcomputer P2.4 mouth, 8 pin DB0 connect single-chip microcomputer P1.0 mouth, 9 pin DB1 connect single-chip microcomputer P1.1 mouth, 10 pin DB2 connect single-chip microcomputer P1.2 mouth, 11 pin DB3 connect single-chip microcomputer P1.3 mouth, 12 pin DB4 connect single-chip microcomputer P1.4 mouth, 13 pin DB5 connect single-chip microcomputer P1.5 mouth, 14 pin DB6 connect single-chip microcomputer P1.6 mouth, 15 pin DB7 connect single-chip microcomputer P1.7 mouth.
As Fig. 7, S1, S2, S3 tri-buttons meet VCC_3.3V respectively by R18, R19 and R20 pull-up resistor, and output port KEY1, KEY2, KEY3 connect P2.5, P2.6, P2.7 mouth of MSP430F5529 single-chip microcomputer respectively.MSP430F5529 single-chip microcomputer judges whether three Independent keys have key to be pressed, if there is key to press, then judges it is which key is pressed.S1 presses and represents that output signal frequency adds certainly, and S2 presses and represents that output signal frequency is from subtracting, and S3 presses and represents that signal exports confirmation.Signal every 10MHz from 10MHz to 300MHz increases progressively, or the every 10MHz of 300MHz to 10MHz successively decreases, and is shown in real time by TFT liquid crystal display screen.
As Fig. 8, it is the concrete connection layout of single-chip microcomputer MSP430F5529.MSP430F5529 single-chip microcomputer P1.7, P1.6, P1.5, P1.4, P1.3, P1.2, P1.1, P1.0 meet DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0 of TFT LCD MODULE respectively, and P2.4, P2.3, P2.2, P2.1, P2.0 meet TFT LCD MODULE RS, WR, RD, CS, RST, to complete the control to Liquid Crystal Module.Independent keys part, P2.7, P2.6, P2.5 mouth of single-chip microcomputer MSP430F5529 connects KEY3, KEY2, KEY1 port of Independent keys S3, S2, S1 respectively.Program control can frequency division PFD phase discriminator part, P3.3, P3.2, P3.1, P3.0 mouth of single-chip microcomputer connect respectively program control can CLK, DATA, LE, MT port of frequency division PFD phase discriminator ADF4106 chip.In addition, the power supply of single-chip microcomputer MSP430F5529 does not provide.
The utility model installation's power source obtains the direct voltage of+5V ,+3.3V again through over commutation, filtering and linear power supply chip fixed ampllitude after powering and using civil power transformation, again via the filtering of 10uF and 0.1uF shunt capacitance, power respectively to MSP430F5529, ADCLK905, ADCLK925, ADF4106 chip and peripheral circuit.
Single-chip microcomputer adopts MSP430F5529 single-chip microcomputer, and this single-chip microcomputer belongs to the High Performance SCM in TI company super low power consuming single chip processor MSP430 series, is low-power consumption and high performance combination.Display module adopts TFT LCD.
Program control can frequency division PFD phase discriminator ADF4106 chip, it is the PLL frequency synthesizer (PLL Frequency Synthesizer) of a high-performance of ADI company, low phase noise, integral frequency divisioil, PLL is the abbreviation of Phase-locked Loop, ADF4106 chip is by the phase place of comparator input signal and feedback signal, control the square-wave voltage that internal charge pump exports the variable duty ratio of certain frequency, the internal integers frequency divider of control ADF4106 can realize the change of external signal frequency.Wherein integer frequency divider can only be set to integer value, and ADF4106 chip bandwidth is that 6GHz, 2.7-3.3V power, and phase noise is extremely low, and the phase noise of 10Hz is the phase noise of-140dBc/Hz, 1MHz is-158dBc/Hz.
Clock buffer chip ADCLK905 and ADCLK925 belongs to the ADCLK9 series high-performance clock buffer chip of ADI company, output signal randomized jitter is only 60fs(femtosecond), propagation delay 95ps(skin is wonderful), the highest 8000V/us of slew rate, 2.5V to 3.3V powers, with ADCLK905 chip unlike, ADCLK925 chip is doubleway output.
VCXO SARONIX-300.000 is SARONIX company 300MHz VCXO, 5V powers, during voltage-controlled end floating, i.e. 1 pin floating, frequency center point Wo is 150MHz, voltage-controlled voltage pin voltage range 2.5V ± 2.5V, voltage-controlled parameter Kv=60MHz/V, output impedance 50 Ω, phase noise is extremely low, the phase noise of 10Hz is the phase noise of-86dBc/Hz, 1MHz is-172dBc/Hz.
Utility model works process is as follows:
10MHz input clock signal is after reference clock buffer chip ADCLK905, reduce the randomized jitter of input signal, improve the slew rate of input signal, then after impedance matching and high-pass filtering module, ADF4106 chip is inputted, ADF4106 is by the signal of comparator input signal with the inner frequency divider of process fed back, by internal charge pump output current, after overcurrent-voltage low-pass filter circuit, be converted to voltage, control the signal that VCXO SARONIX-300.000 produces 10 to 300MHz, after based on the frequency-doubled signal buffered feedback of clock buffer chip ADCLK925 and output module, one tunnel by signal feedback to frequency synthesis chip ADF4106, another road directly exports.Period, single-chip microcomputer is connected with frequency synthesis chip ADF4106, single-chip microcomputer scanning Independent keys S1, S2 and S3, judge whether to press, then according to the different key pressed, by the frequency division value of ADF4106 chip controls mouth write frequency divider, thus the signal of response 10 to 300MHz exports, concrete, when inner integer frequency divider settings are 1 to 30 integer, the every 10MHz increment signal of response 10 to 300MHz exports, and TFT LCD MODULE is by the frequency of the real-time display translation signal of control of single-chip microcomputer.
By reference to the accompanying drawings execution mode of the present utility model is explained in detail above, but the utility model is not limited to above-mentioned execution mode, in the ken that those of ordinary skill in the art possess, can also make a variety of changes under the prerequisite not departing from the utility model aim.The above, it is only preferred embodiment of the present utility model, not any pro forma restriction is done to the utility model, although the utility model discloses as above with preferred embodiment, but and be not used to limit the utility model, any those skilled in the art, do not departing within the scope of technical solutions of the utility model, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solutions of the utility model content, according to technical spirit of the present utility model, within spirit of the present utility model and principle, to any simple amendment that above embodiment is done, equivalent replacement and improvement etc., within the protection range all still belonging to technical solutions of the utility model.
Claims (6)
1., based on a program control frequency doubling device for PLL phase-locked loop and frequency divider, it is characterized in that: comprise program control frequency division PFD phase discriminator, single-chip microcomputer, display module, Independent keys module, low-pass filtering module, VCXO module, frequency-doubled signal buffered feedback and output module, high-pass filtering module, impedance matching module, reference clock buffer module, clock signal input module;
Described single-chip microcomputer is connected with display module, Independent keys module, program control frequency division PFD phase discriminator respectively;
Described clock signal input module, reference clock buffer module, impedance matching module, high-pass filtering module, program control frequency division PFD phase discriminator, low-pass filtering module, VCXO module, frequency-doubled signal buffered feedback are connected successively with output module;
Described frequency-doubled signal buffered feedback and output module are also connected with program control frequency division PFD phase discriminator
.
2. a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider according to claim 1, is characterized in that: described reference input clock buffer module is based on ADCLK905 chip.
3. a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider according to claim 1, is characterized in that: described frequency-doubled signal buffered feedback and output module are based on ADCLK925 chip.
4. a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider according to claim 1, is characterized in that: describedly program controlly can adopt ADF4106 chip by frequency division PFD phase discriminator.
5. a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider according to claim 1 or 2 or 3, is characterized in that: described display module adopts TFT LCD.
6. a kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider according to claim 1 or 2 or 3 or 4, it is characterized in that: the circuit of program control frequency doubling device comprises active crystal oscillator chip, clock buffer modules A DCLK905 chip, VCXO SARONIX chip, program control frequency division PFD phase discriminator ADF4106 chip, frequency-doubled signal buffered feedback and output module ADCLK925 chip, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, 9th resistance, tenth resistance, 11 resistance, 12 resistance, 13 resistance, 14 resistance, 15 resistance, 16 resistance, 17 resistance, first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, 11 electric capacity,
The output of described active crystal oscillator is connected with the 16 pin with one end of the first electric capacity, one end of the second electric capacity, the 15 pin of ADCLK905 chip respectively, and the other end of described first electric capacity connects the first pin of ADCLK905 chip;
11 pin of described ADCLK905 chip connects one end of the 4th electric capacity, one end of the 3rd resistance respectively, and the other end of described 4th electric capacity connects one end of the 4th resistance, the other end of described 3rd resistance, the equal ground connection of the other end of the 4th resistance;
12 pin of described ADCLK905 chip connects one end of the 3rd electric capacity, one end of the first resistance respectively, the other end ground connection of described first resistance, the other end of described 3rd electric capacity connects one end of the second resistance, one end of the 5th electric capacity, the other end ground connection of described second resistance respectively;
The other end of described 5th electric capacity connects the 8th pin of ADF4106 chip, and the first pin of described ADF4106 chip connects one end of the 5th resistance, the other end ground connection of described 5th resistance;
Second pin of described ADF4106 chip connects one end of the 8th resistance, one end of the 7th electric capacity, one end of the 6th electric capacity respectively, the other end of described 7th electric capacity connects one end of the 7th resistance, the other end of described 6th electric capacity, the equal ground connection of the other end of the 7th resistance;
The other end of described 8th resistance connects the first pin of SARONIX chip, one end of the 8th electric capacity, the other end ground connection of described 8th electric capacity respectively;
Tenth pin of described ADF4106 chip connects one end of the 6th resistance, and the other end of described 6th resistance connects voltage;
5th pin of described ADF4106 chip connects one end of the 14 electric capacity, the other end of described 14 electric capacity connects one end of the 17 resistance, 6th pin of described ADF4106 chip connects one end of the 13 electric capacity, and the other end of described 13 electric capacity connects one end of the 16 resistance;
The described other end of the 16 resistance, the other end of the 17 resistance connect the 9th pin, the tenth pin of ADCLK925 chip respectively, 9th pin of described ADCLK925 chip, the tenth pin also connect one end of the 15 resistance, one end of the 14 resistance respectively, the described other end of the 15 resistance, the equal ground connection of the other end of the 14 resistance;
First pin of described ADCLK925 chip connects one end of the 9th electric capacity, and the other end of described 9th electric capacity connects the 4th pin of SARONIX chip; Second pin of described ADCLK925 chip connects one end of the tenth electric capacity, the 15 pin of ADCLK925 chip and the 16 pin respectively, the other end ground connection of described tenth electric capacity;
12 pin of described ADCLK925 chip connects one end of the 9th resistance, one end of the 11 resistance respectively, the other end of described 11 resistance connects one end of the 12 electric capacity, the other end of described 12 electric capacity connects P1, P1 ground connection, the other end ground connection of described 9th resistance;
11 pin of described ADCLK925 chip connects one end of the tenth resistance, one end of the 12 resistance respectively, one end that the other end connects one end of the 11 electric capacity, the other end of the 11 electric capacity connects the 13 resistance of described 12 resistance, the described other end of the tenth resistance, the other end ground connection of the 13 resistance.
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| CN201520264478.5U CN204465511U (en) | 2015-04-28 | 2015-04-28 | A kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider |
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| CN201520264478.5U CN204465511U (en) | 2015-04-28 | 2015-04-28 | A kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105406860A (en) * | 2015-10-20 | 2016-03-16 | 北京中科飞鸿科技有限公司 | High precision output single-chip microcomputer phase-locked loop rapid frequency source |
| CN105827239A (en) * | 2016-03-21 | 2016-08-03 | 成都天进仪器有限公司 | Clock circuit for intelligent relay protection tester |
| CN107741523A (en) * | 2017-09-07 | 2018-02-27 | 江汉大学 | A kind of time-domain signal measurement apparatus based on PLL phaselocked loops |
| CN112234986A (en) * | 2020-09-04 | 2021-01-15 | 上海鸿晔电子科技股份有限公司 | Signal source |
| CN116418310A (en) * | 2023-04-14 | 2023-07-11 | 上海韬润半导体有限公司 | High-frequency input buffer and integrated circuit |
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2015
- 2015-04-28 CN CN201520264478.5U patent/CN204465511U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105406860A (en) * | 2015-10-20 | 2016-03-16 | 北京中科飞鸿科技有限公司 | High precision output single-chip microcomputer phase-locked loop rapid frequency source |
| CN105827239A (en) * | 2016-03-21 | 2016-08-03 | 成都天进仪器有限公司 | Clock circuit for intelligent relay protection tester |
| CN107741523A (en) * | 2017-09-07 | 2018-02-27 | 江汉大学 | A kind of time-domain signal measurement apparatus based on PLL phaselocked loops |
| CN107741523B (en) * | 2017-09-07 | 2020-01-07 | 江汉大学 | Time domain signal measuring device based on PLL |
| CN112234986A (en) * | 2020-09-04 | 2021-01-15 | 上海鸿晔电子科技股份有限公司 | Signal source |
| CN112234986B (en) * | 2020-09-04 | 2021-07-13 | 上海鸿晔电子科技股份有限公司 | Signal source |
| CN116418310A (en) * | 2023-04-14 | 2023-07-11 | 上海韬润半导体有限公司 | High-frequency input buffer and integrated circuit |
| CN116418310B (en) * | 2023-04-14 | 2024-02-09 | 上海韬润半导体有限公司 | High-frequency input buffer and integrated circuit |
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