CN101534186B - Digital smoothing circuit and method for utilizing digital smoothing circuit to extract clock from Ethernet signals - Google Patents
Digital smoothing circuit and method for utilizing digital smoothing circuit to extract clock from Ethernet signals Download PDFInfo
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- CN101534186B CN101534186B CN200810017670.9A CN200810017670A CN101534186B CN 101534186 B CN101534186 B CN 101534186B CN 200810017670 A CN200810017670 A CN 200810017670A CN 101534186 B CN101534186 B CN 101534186B
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Abstract
The invention relates to a digital smoothing circuit and a method for utilizing the digital smoothing circuit to extract clock from random Ethernet signals. The digital smoothing circuit comprises a bit adjusting circuit and a digital phase-locked loop which comprises a frequency discriminator, a phase discriminator, an adder and a frictional frequency divider. The invention adopts a method with juxtaposition of frequency discrimination and phase discrimination, simultaneously combines a digital filter with the method, adopts the frictional frequency divider to form a digital control vibrator, and restores E1 clock signals therefrom. The invention solves the technical problem that the existing digital smoothing circuit has complex structure, and has the advantages of simple structure and easy realization; an ASIC circuit designed by the method has reliable operation and jitter index thereof meets relevant ITU-T standard by experimental verification.
Description
Technical field
The present invention relates to a kind of digital smoothness circuit and utilize this digital smoothness circuit from random ethernet signal, to extract the method for clock.
Background technology
In IP-based New Generation of Communication, in order to realize multi-service transmission, at transmitting terminal, real time business (TDM business) processings of pack, make it become the packet that too net wraps, then transmit; At receiving terminal, in order to reply original TDM business, data are added up and jitter elimination, thus the timing information of acquisition code stream.The basic principle of jitter elimination is exactly the principle of digital phase-locked loop; Utilize PHASE-LOCKED LOOP PLL TECHNIQUE to realize quantification, the digital filtering and regularly comprehensive to incoming timing signal.Traditional digitlization theory here shows as simply and rounds, and circuit is often corresponding is the pulse of handling up, and is the form of counter.
In TDMoIP system, at transmitting terminal, needing the signal sending is the E1 signal of standard, in order to transmit in Ethernet system, E1 signal is split, encapsulated, make its Ethernet bag that becomes fixed size, the timing information in E1 signal originally is all lost; In the signal of receiving at receiving terminal, do not contain any timing information, the shake of data also becomes random, and this just need to will carry out special processing at receiving terminal, could reply the clock of E1 signal.Because ethernet signal is random signal, first random ethernet signal is carried out to statistical disposition, obtain the fundamental frequency of signal, then take this frequency as benchmark, carry out digital smoothness; Traditional digital smoothness circuit can be divided into two classes; One class is to be made up of the digital phase-locked loop of bit Circuit tuning and Medium-bandwidth, and another kind of is to be made up of a phase-locked loop, but the smaller bandwidth of phase-locked loop.But, all more complicated of such digital smoothness circuit structure.
Summary of the invention
The object of the invention is to provide a kind of digital smoothness circuit and method of extracting clock from ethernet signal of realizing, and it has solved the technical problem of existing digital smoothness circuit structure complexity.
Technical solution of the present invention is:
Realize a digital smoothness circuit that extracts clock from ethernet signal, comprise the digital phase-locked loop of bit Circuit tuning and Medium-bandwidth, described bit Circuit tuning is made up of multimode counter and data storage; Described multimode counter comprises the first counter 1 and the second counter 2; Its special character is that described digital phase-locked loop comprises frequency discriminator FD, phase discriminator PD, adder 3 and decimal frequency divider; Output and the phase demodulation control signal vd of described the first counter 1 and the second counter 2 are connected with the input of frequency discriminator PD respectively; The output of described phase demodulation control signal vd and decimal frequency divider is connected with the input of phase discriminator FD respectively; The output of described frequency discriminator FD and phase discriminator PD is connected with the input of adder 3 respectively; The output of described adder 3 is connected with the input of decimal frequency divider respectively.
Above-mentioned decimal frequency divider comprises controller 4, the first frequency divider 5, the second frequency divider 6 and selector MUX; The output of described adder 3 is connected with the input of controller 4, and the output of described controller 4 is connected with the control end of selector MUX; The input of described the first frequency divider 5 and the second frequency divider 6 connects respectively reference clock signal, and its output is connected with the input of selector MUX respectively.
Above-mentioned controller 4 is made up of serial adder.
Realize a method of extracting clock from ethernet signal, it comprises the following steps:
1] the first counter 1 and the second counter 2 input signal f to ethernet signal respectively
inwith output signal f
outcount;
2] count results and phase demodulation control signal vd send into respectively frequency discriminator FD, frequency discriminator FD output frequency difference f
d; Phase discriminator PD utilizes output signal and the differing of phase demodulation control signal vd of high-frequency clock to selector MUX to count, and output differs p
d;
3] adder 3 is added the result of frequency discriminator FD and phase discriminator PD and constant, produces the control signal of frequency divider;
4] control signal that frequency divider produces after processing according to adder 3 obtains frequency dividing ratio, sends into decimal frequency divider;
5] the output signal f of decimal frequency divider output Ethernet
out.
The concrete steps that above-mentioned frequency divider is sent frequency dividing ratio into decimal frequency divider are: controller 4 is according to the output signal filter of adder 3, obtain frequency dividing ratio, and frequency dividing ratio is sent into selector MUX, selector MUX is according to frequency dividing ratio, frequency to the first frequency divider 5 and the second frequency divider 6 is selected and adjusts, the output signal f of output Ethernet
out.
Tool of the present invention has the following advantages:
1, the present invention proposes a kind of digital smoothness device that can be level and smooth to E1 tributary signal, wherein comprise second order digital phase-locked loop, simple in structure, be easy to realize, be especially applicable to ASIC and realize, with the method ASIC design circuit, reliable, and the experiment proved that shake index meets relevant ITU-T standard.
2, the present invention adopts frequency discrimination, phase demodulation juxtaposition method, digital filter is incorporated wherein simultaneously, adopts decimal frequency divider to form digital controlled oscillator, therefrom recovers E1 clock signal.
3, the present invention elongates the variation of the frequency of output stream in time, is convenient to the design of digital phase-locked loop.
Accompanying drawing explanation
Fig. 1 is circuit theory schematic diagram of the present invention;
Wherein: 1-the first counter, 2-the second counter, 3-adder, 4-controller, 5-the first frequency divider, 6-the second frequency divider, FD-frequency discriminator, PD-phase discriminator, MUX-selector, f
out-output signal, f
in-input signal, vd-phase demodulation control signal, f
0-reference clock, filter-adder output signal, f
dthe frequency difference of-input signal and output signal, p
ddiffering of-input signal and output signal.
Embodiment
Digital smoothness circuit of the present invention, comprises the digital phase-locked loop of bit Circuit tuning and Medium-bandwidth, and bit Circuit tuning is made up of multimode counter and data storage; Multimode counter comprises the first counter and the second counter; Digital phase-locked loop comprises frequency discriminator, phase discriminator, adder and decimal frequency divider; The output of the first counter and the second counter and phase demodulation control signal are connected with the input of frequency discriminator respectively; The output of phase demodulation control signal and decimal frequency divider is connected with the input of phase discriminator respectively; The output of frequency discriminator and phase discriminator is connected with the input of adder respectively; The output of adder is connected with the input of decimal frequency divider respectively.Decimal frequency divider comprises controller, the first frequency divider, the second frequency divider and selector; The output of adder is connected with the input of controller, and the output of controller is connected with the control end of selector; The input of the first frequency divider and the second frequency divider connects respectively reference clock signal, and its output is connected with the input of selector MUX respectively; Controller produces the control signal to the first frequency divider and the output of the second frequency divider according to input signal, and controller is made up of serial adder.
Realize a method of extracting clock from ethernet signal, comprise the following steps: the first counter and the second counter respectively input signal to ethernet signal and output signal are counted; Count results and phase demodulation control signal are sent into respectively frequency discriminator, frequency discriminator output frequency difference; Phase discriminator utilizes output signal and the differing of phase demodulation control signal of high-frequency clock to selector to count, and output differs; Adder is added the result of frequency discriminator and phase discriminator and constant, produces the control signal of controller; The control signal that controller produces after processing according to adder obtains frequency dividing ratio, sends into selector; Selector, according to frequency dividing ratio, is selected and adjusts the frequency of the first frequency divider and the second frequency divider, the output signal of output Ethernet.
The principle of the invention:
The present invention is directed to the data structure of transmitting E1 signal by Ethernet, design a kind of all-digital phase-locked loop, adopted frequency discrimination, phase demodulation juxtaposition method, digital filter has been incorporated wherein simultaneously, adopt decimal frequency divider to form digital controlled oscillator, therefrom recover E1 clock signal.Reached designing requirement through feasibility, this circuit structure is simple, is easy to be integrated in ASIC and goes, and has stronger practicality, easy to utilize.
The present invention adopts and forms digital smoothness circuit by the digital phase-locked loop of bit Circuit tuning and Medium-bandwidth, and bit Circuit tuning is made up of multimode counter and data storage; Multimode counter, according to the state of data buffer FIFO, is determined the frequency that adds in data flow or detain pulse, then this information is deposited in to data storage, realizes and in data flow, adds button pulse, and the variation of the frequency of output stream is elongated in time.
The present invention is a direct processing formula phase-locked loop, the first counter and the second counter are counted read-write clock pulse respectively, subtracter, output frequency difference, digital phase discriminator, is a counter, count differing with high-frequency clock, the effect of adder is that the result of frequency discrimination and phase demodulation and constant are added, and produces the control signal of controller, and controller is to be made up of serial adder; The first frequency divider and the second frequency divider are M and M+1 frequency divider, and they form a frequency divider that contains decimal together with controller, selector, and the frequency dividing ratio of frequency divider is the result by frequency discrimination and phase demodulation, and the control signal producing after adder is processed is determined.
Because digital phase-locked loop forms digital Jitter Attenuation device together with bit Circuit tuning, be used for decaying and transmit by Ethernet the shake that E1 signal causes, the bit Circuit tuning here is just equivalent to a controlled low pass filter, according to designing requirement, the output of bit Circuit tuning, be being input as of phase-locked loop: first Ethernet data is added up, determine the basic rate of E1 signal, then the data higher or lower than basic rate are carried out to bit adjustment, the speed of bit adjustment is determined by adaptive algorithm.
The first counter and the second counter are identical cycle counters, just initial value is not identical, its function is equivalent to that past input signal is carried out to infinite time and adds up, they and frequency discriminator, phase discriminator, adder complete the effect of frequency discrimination, phase demodulation jointly, also contain the function of filter simultaneously, that is to say that a frequency discrimination, identified result carried out digital filtering.Phase demodulation control signal completes the value moment to frequency discrimination, identified result, in fact plays a quantized interval, and it should have definite integer ratio relation with the number of touching of phase discriminator.Adder the effect is here that the result juxtaposition of frequency discrimination, phase demodulation and a constant are added, and plays a circuit successive.In fact, signal, through after adder, has just really completed frequency discrimination, phase demodulation effect.
Claims (3)
1. a digital smoothness circuit for clock is extracted in realization from ethernet signal, comprises the digital phase-locked loop of bit Circuit tuning and Medium-bandwidth, and described bit Circuit tuning is made up of multimode counter and data storage; Described multimode counter comprises the first counter (1) and the second counter (2);
It is characterized in that: described digital phase-locked loop comprises frequency discriminator (FD), phase discriminator (PD), adder (3) and decimal frequency divider; Output signal (fout) end of the input termination ethernet signal of described the first counter (1), input signal (fin) end of the input termination ethernet signal of described the second counter (2), output and the phase demodulation control signal (vd) of described the first counter (1) and the second counter (2) are connected with the input of frequency discriminator (FD) respectively; The output of described phase demodulation control signal (vd) and decimal frequency divider is connected with the input of phase discriminator (PD) respectively; The output of described frequency discriminator (FD) and phase discriminator (PD) is connected with the input of adder (3) respectively; Described decimal frequency divider comprises controller (4), the first frequency divider (5), the second frequency divider (6) and selector (MUX); The output of described adder (3) is connected with the input of controller (4), and the output of described controller (4) is connected with the control end of selector (MUX); The input of described the first frequency divider (5) and the second frequency divider (6) meets respectively reference clock signal (f
0), its output is connected with the input of selector (MUX) respectively.
2. digital smoothness circuit according to claim 1, is characterized in that: described controller (4) is made up of serial adder.
3. a method for clock is extracted in realization from ethernet signal, it is characterized in that: it comprises the following steps:
1] the first counter (1) and the second counter (2) input signal (f to ethernet signal respectively
in) and output signal (f
out) count;
2] count results and phase demodulation control signal (vd) are sent into respectively frequency discriminator (FD), frequency discriminator (FD) output frequency difference (f
d); Phase discriminator (PD) utilizes output signal and the differing of phase demodulation control signal (vd) of high-frequency clock to selector (MUX) to count, and output differs (p
d);
3] adder (3) is added the result of frequency discriminator (FD) and phase discriminator (PD) and constant, produces the control signal of decimal frequency divider;
4] described decimal frequency divider comprises controller (4), the first frequency divider (5), the second frequency divider (6) and selector (MUX); Described controller (4) is according to the output signal of adder (3) (filter), obtain frequency dividing ratio, and frequency dividing ratio is sent into selector (MUX), selector (MUX) is according to frequency dividing ratio, frequency to the first frequency divider (5) and the second frequency divider (6) is selected and adjusts, the output signal (f of output Ethernet
out), the input of described the first frequency divider (5) and the second frequency divider (6) meets respectively reference clock signal (f
0).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP2333957B1 (en) * | 2009-12-04 | 2015-01-28 | Nxp B.V. | A clock signal generator |
| CN102104378B (en) * | 2009-12-18 | 2013-01-02 | 中国科学院微电子研究所 | Locking detection method and device for ADPLL (All Digital Phase-Locked Loop) |
| CN101860415B (en) * | 2010-05-18 | 2012-08-22 | 中国电子科技集团公司第五十四研究所 | Blind identification method for coding parameters of extended Golay code of error-tolerant code |
| CN105706383B (en) * | 2013-02-22 | 2019-03-08 | 瑞典爱立信有限公司 | The pluggable transceiver and its synchronous method of time synchronization |
| CN108923782B (en) * | 2018-07-19 | 2021-09-07 | 深圳大学 | All-digital phase-locked loop and rapid phase locking method thereof |
| CN117254805A (en) * | 2023-11-20 | 2023-12-19 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
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| CN101079630A (en) * | 2006-05-23 | 2007-11-28 | 中兴通讯股份有限公司 | A digital phase lock loop device for smooth switching of clock phase and its method |
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| CN101079630A (en) * | 2006-05-23 | 2007-11-28 | 中兴通讯股份有限公司 | A digital phase lock loop device for smooth switching of clock phase and its method |
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