CN111934674A - Error calibration device and method, phase-locked loop and chip - Google Patents

Error calibration device and method, phase-locked loop and chip Download PDF

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Publication number
CN111934674A
CN111934674A CN202010846989.3A CN202010846989A CN111934674A CN 111934674 A CN111934674 A CN 111934674A CN 202010846989 A CN202010846989 A CN 202010846989A CN 111934674 A CN111934674 A CN 111934674A
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China
Prior art keywords
clock
code
output
tdc
dco
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CN202010846989.3A
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Chinese (zh)
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高玲
王文根
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Chengdu Haiguang Microelectronics Technology Co Ltd
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Chengdu Haiguang Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

The application provides an error calibration device, method, phase-locked loop and chip, the device includes: the phase offset controller is used for inputting a feedback clock output by the DCO at the second moment and a preset reference clock into the TDC; the output calibrator is used for comparing the actual code output by the TDC with the preset check code and outputting the comparison result to the digital loop filter; the actual code is the unit delay of the phase difference/TDC between the feedback clock output by the DCO at the second moment and the preset reference clock; the check code is: the method comprises the steps that a phase offset controller offsets a feedback clock and/or a preset reference clock output by a DCO at a first moment to form a preset phase difference, and the reference clock and the feedback clock forming the preset phase difference are input into a TDC to obtain the phase offset; the check code is a preset phase difference/unit delay. Compared with the check coding, the unit delay contained by the actual coding and the check coding together can be eliminated, and therefore the clock jitter of the DCO output is relieved.

Description

Error calibration device and method, phase-locked loop and chip
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to an error calibration apparatus and method, a phase-locked loop, and a chip.
Background
In a conventional phase-locked loop, the phase-locked loop generally includes: TDC (Time to Digital converter), Digital loop filter, DSM (Delta Sigma Modulator), thermal encoder, current generator, DCO (Digitally Controlled Oscillator), and frequency divider.
The reference clock preset by the phase-locked loop is input to the TDC, the signal output by the frequency divider is used as the feedback clock and is also input to the TDC, and the TDC can determine the phase difference between the feedback clock and the reference clock. Because the TDC is an analog circuit module, the TDC can divide the unit delay of the inverter inside the TDC by the phase difference to obtain an output code, and the output code is output to a digital loop filter for filtering. And the digital loop filter outputs the filtered code to the DSM and the thermal encoder, respectively. The DSM further filters noise of a fractional part in the code after noise filtering and inputs the noise to a current generator; the thermal encoder converts the filtered integer part of the code into a thermometer code, which is also input to the current generator. The current generator controls the oscillation of the DCO based on the input parameters to adjust the clock of the DCO output. And finally, the output clock after the DCO adjustment is subjected to frequency division by the frequency divider and then is used as a feedback clock to be input into the TDC, so that closed-loop adjustment is formed until no phase difference exists between the reference clock and the feedback clock, and therefore phase locking is realized.
It is understood that, since the TDC is an analog circuit module, the unit delay of its internal inverter varies with the PVT ("P" is "Process" which refers to the Process adopted during the manufacturing of the TDC, "V" is "Voltage" which refers to the magnitude of the Voltage loaded during the operation of the TDC, "T" is "Temperature" which refers to the Temperature during the operation of the TDC). For example, when the TDC is manufactured by a slow process, the unit delay is large, which results in a small code output from the TDC; when the TDC is manufactured by a fast process, the unit delay is small, so that the code output by the TDC is large; when the working temperature of the TDC is low, the unit delay is large, so that the code output by the TDC is small; when the operating temperature of the TDC is too high, the unit delay is too small, which results in too large code output from the TDC. The variation of the unit delay may cause the coding of the TDC output to be unstable, and the unstable coding further causes the clock of the DCO output to have significant jitter after the series of processing.
Disclosure of Invention
An object of the embodiments of the present invention is to provide an error calibration apparatus and method, a phase-locked loop, and a chip, so as to prevent the result output to a digital loop filter from being unstable due to the influence of unit delay variation, and to alleviate the jitter of a clock output by a DCO.
In a first aspect, an embodiment of the present application provides an error calibration apparatus, where the apparatus includes: the phase offset controller is used for being connected with the output end of the DCO in the phase-locked loop and the input end of the TDC; an output calibrator connected to an output of the TDC and an input of a digital loop filter in the phase-locked loop; the phase offset controller is used for inputting a feedback clock output by the DCO at a second moment and a preset reference clock into the TDC; the output calibrator is used for comparing the actual code output by the TDC with a preset check code and outputting the comparison result to the digital loop filter; wherein the actual coding is a unit delay of the TDC/a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock; the check code is as follows: shifting, by the phase shift controller, a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC; and the check code is the preset phase difference/the unit delay.
In the embodiment of the application, the output calibrator is preset with the check code equal to the preset phase difference/unit delay, and after the TDC outputs the actual code equal to the actual phase difference/unit delay, the output calibrator can eliminate the unit delay included in the actual code and the check code by comparing the actual code with the check code, so that the result output to the digital loop filter is not unstable due to the influence of the unit delay change, and the jitter of the clock output by the DCO is alleviated.
With reference to the first aspect, in a first possible implementation manner, the phase shift controller is configured to pre-shift the feedback clock output by the DCO at a first time, so that the pre-shifted feedback clock is advanced by half a clock period of the preset reference clock, and input the pre-shifted feedback clock and the preset reference clock to the TDC; the feedback clock output by the DCO at the first moment is subjected to post-offset, so that the post-offset feedback clock is placed in the preset reference clock for half a clock period later, and the post-offset feedback clock and the preset reference clock are input into the TDC; the output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code is a preceding half clock cycle/the unit delay, and the second code is a succeeding half clock cycle/the unit delay.
In the embodiment of the application, on one hand, the phase difference of the overall offset is a complete clock cycle, so the phase difference can be used for conveniently calculating the check code; on the other hand, since the offset is performed every half clock cycle, the accuracy is high, and the error of the offset can be reduced.
With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner, the phase shift controller includes: a state machine and a phase shift circuit; the state machine is configured to output a feedback clock output by the DCO at a first time and the preset reference clock to the phase offset circuit, and send a first instruction to the phase offset circuit first and then send a second instruction to the phase offset circuit; the phase shift circuit is configured to, after receiving a feedback clock output by the DCO at a first time and the preset reference clock, pre-shift the feedback clock output by the DCO at the first time according to the first instruction, input the pre-shifted feedback clock and the preset reference clock to the TDC, post-shift the feedback clock output by the DCO at the first time according to the second instruction, and input the post-shifted feedback clock and the preset reference clock to the TDC; and the state machine is further used for inputting the feedback clock output by the DCO at the second moment and the preset reference clock into the TDC.
In the embodiment of the application, the offset executing time sequence is specially controlled through the state machine, so that the offset operation can be ensured to be executed in order.
With reference to the first aspect, in a third possible implementation manner, the phase offset controller is configured to pre-offset the feedback clock output by the DCO at the first time, and post-offset the preset reference clock, so that the pre-offset feedback clock is pre-offset by half a clock period of the post-offset reference clock, and input the pre-offset feedback clock and the post-offset reference clock to the TDC; the TDC is also used for post-shifting the feedback clock output by the DCO at the first moment, pre-shifting the preset reference clock, enabling the post-shifted feedback clock to be placed at the post-shifted reference clock half clock period later, and inputting the post-shifted feedback clock and the pre-shifted reference clock into the TDC;
the output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code is a preceding half clock cycle/the unit delay, and the second code is a succeeding half clock cycle/the unit delay.
In the embodiment of the application, on one hand, the phase difference of the overall offset is a complete clock cycle, so the phase difference can be used for conveniently calculating the check code; on the other hand, since the offset is performed every half clock cycle, the accuracy is high, and the error of the offset can be reduced.
With reference to the first aspect, in a fourth possible implementation manner, the phase shift controller is configured to shift the preset reference clock to a rear position, so that the feedback clock output by the DCO at the first time is advanced by half a clock period of the reference clock of the rear shift, and input the feedback clock output by the DCO and the reference clock of the rear shift into the TDC; the TDC is also used for pre-offsetting the preset reference clock, enabling the feedback clock output by the DCO at the first moment to be positioned at the reference clock of the pre-offset by half a clock period, and inputting the feedback clock output by the DCO at the first moment and the reference clock of the pre-offset into the TDC; the output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code is a preceding half clock cycle/the unit delay, and the second code is a succeeding half clock cycle/the unit delay.
In the embodiment of the application, on one hand, the phase difference of the overall offset is a complete clock cycle, so the phase difference can be used for conveniently calculating the check code; on the other hand, since the offset is performed every half clock cycle, the accuracy is high, and the error of the offset can be reduced.
With reference to any one of the first to fourth possible implementation manners of the first aspect, in a fifth possible implementation manner, the output calibrator includes: the phase offset controller comprises a memory, a subtracter, a divider and a multiplier, wherein the memory is respectively connected with the subtracter and the phase offset controller, and the subtracter is connected with the divider; the memory is further configured to be coupled to an output of the TDC, the divider is configured to be coupled to an output of the TDC, and the multiplier is configured to be coupled to an input of the digital loop filter; the memory is used for storing the first code and the second code; and a phase shift controller for outputting the first code and the second code to the subtractor based on control of the phase shift controller; the subtracter is used for subtracting the first code from the second code to obtain the check code and outputting the check code to the divider; the divider is used for dividing the check code and the actual code to obtain a quotient value and outputting the quotient value to the multiplier; and the multiplier is used for multiplying the quotient value by a preset value to obtain the result and outputting the result to the digital loop filter.
In the embodiment of the application, the check code and the actual code are calculated by setting each operational circuit of hardware, so that the efficiency is high, and the resources of software are not occupied.
In a second aspect, an embodiment of the present application provides an error calibration method, where the method includes: inputting a feedback clock and a preset reference clock output by a DCO (digital data output) in the phase-locked loop at the second moment into a TDC (time to live) in the phase-locked loop; comparing the actual code output by the TDC with a preset check code, and outputting the comparison result to a digital loop filter in the phase-locked loop; wherein the actual coding is a unit delay of the TDC/a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock; the check code is as follows: obtaining by shifting a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC; and the check code is the preset phase difference/the unit delay.
With reference to the second aspect, in a first possible implementation manner, the determining the check code includes: pre-offsetting a feedback clock output by the DCO at a first moment to enable the pre-offset feedback clock to be positioned in front of the preset reference clock by half a clock period, and inputting the pre-offset feedback clock and the preset reference clock into the TDC; and post-shifting a feedback clock output by the DCO at a first time, so that the post-shifted feedback clock is placed in the preset reference clock for a half clock period later, and inputting the post-shifted feedback clock and the preset reference clock into the TDC; and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
With reference to the second aspect, in a second possible implementation manner, the determining the check code includes: pre-offsetting a feedback clock output by the DCO at a first moment, post-offsetting the preset reference clock to enable the pre-offset feedback clock to be pre-positioned in a post-offset reference clock by half a clock period, and inputting the pre-offset feedback clock and the post-offset reference clock into the TDC; and post-offsetting the feedback clock output by the DCO at the first time, pre-offsetting the preset reference clock, enabling the post-offset feedback clock to be placed at the post-offset reference clock half clock period later, and inputting the post-offset feedback clock and the pre-offset reference clock into the TDC; and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
With reference to the second aspect, in a third possible implementation manner, the determining the check code includes: the preset reference clock is subjected to post-offset, so that a feedback clock output by the DCO at a first moment is positioned in front of the post-offset reference clock by half a clock period, and the feedback clock output by the DCO and the post-offset reference clock are input into the TDC; pre-offsetting the preset reference clock, enabling a feedback clock output by the DCO at a first moment to be positioned at a half clock period of the pre-offset reference clock, and inputting the feedback clock output by the DCO at the first moment and the pre-offset reference clock into the TDC; and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
With reference to the second aspect or any one of the first to third possible implementation manners of the second aspect, in a fourth possible implementation manner, comparing the actual code output by the TDC with a preset check code, and outputting a comparison result to a digital loop filter in the phase-locked loop, includes: dividing the check code and the actual code to obtain a quotient value; and multiplying the quotient value by a preset value to obtain the result, and outputting the result to the digital loop filter.
In a third aspect, an embodiment of the present application provides a phase-locked loop, including: outputting a calibrator, a DCO and a TDC; a digital loop filter, the output calibrator being connected to an output of the TDC and an input of the digital loop filter, an output of the DCO being connected to an input of the TDC, the digital loop filter being connected to an input of the DCO; the DCO is used for outputting a feedback clock to the TDC at a second moment; the TDC is used for determining an actual code according to the feedback clock and a preset reference clock and outputting the actual code to the output calibrator; the output calibrator is used for comparing the actual code with a preset check code and outputting a comparison result to the digital loop filter; wherein the actual coding is a unit delay of the TDC/a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock; the check code is as follows: obtaining by shifting a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC; the check code is the preset phase difference/the unit delay; and the digital loop filter is used for filtering the result and inputting the result into the DCO so as to adjust the output of the DCO.
With reference to the third aspect, in a first possible implementation manner, the phase-locked loop further includes: the phase offset controller is connected with the output end of the DCO and the input end of the TDC; the phase shift controller is configured to shift a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and input the reference clock and the feedback clock forming the preset phase difference to the TDC.
In a fourth aspect, embodiments of the present application provide a non-transitory computer-readable storage medium storing program code, which, when executed by a computer, performs an error calibration method according to the second aspect or any one of the possible implementations of the second aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a first block diagram of an error calibration apparatus according to an embodiment of the present disclosure;
fig. 2 is a second block diagram of an error calibration apparatus according to an embodiment of the present disclosure;
FIG. 3A is a first waveform diagram of clock skew in an error calibration apparatus according to an embodiment of the present disclosure;
FIG. 3B is a second waveform diagram of clock skew in an error calibration apparatus according to an embodiment of the present disclosure;
fig. 4A is a third waveform diagram of clock skew in an error calibration apparatus according to an embodiment of the present disclosure;
FIG. 4B is a fourth waveform of clock skew in an error calibration apparatus according to an embodiment of the present disclosure;
FIG. 5A is a fifth waveform diagram of clock skew in an error calibration apparatus according to an embodiment of the present disclosure;
FIG. 5B is a sixth waveform illustrating clock skew in an error calibration apparatus according to an embodiment of the present disclosure;
fig. 6 is a first block diagram of a phase-locked loop according to an embodiment of the present disclosure;
fig. 7 is a second structural block diagram of a phase-locked loop according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Referring to fig. 1, an embodiment of the present invention provides an error calibration apparatus 100, the error calibration apparatus 100 can be applied to a phase-locked loop, and the error calibration apparatus 100 can include: a phase offset controller 110, and an output calibrator 120. The phase shift controller 110 is configured to be connected to an output of the DCO and an input of the TDC in the phase-locked loop (actually, the phase shift controller 110 is not directly connected to the DCO, but is indirectly connected to the DCO through a frequency divider), and the output calibrator 120 is configured to be connected to an output of the TDC and a digital loop filter in the phase-locked loop.
In this embodiment, the principle of the error calibration apparatus 100 to achieve calibration is to input the clock with the offset of the preset phase difference to the TDC to obtain the check code output by the TDC and formed by the unit delay of the preset phase difference/inverter in the TDC. Therefore, in the subsequent application, the check code is divided by the actual code output in the TDC actual application, so that the unit delay is eliminated, the compared result is input into the digital loop filter, the instability caused by the influence of the unit delay change is avoided, and the jitter of the clock output by the DCO is relieved.
Further, to achieve the above technical effects, the error calibration apparatus 100 may determine the check code in a preparation stage before the error calibration apparatus 100 is put into practical use, where the preparation stage may be performed before the error calibration apparatus 100 leaves a factory, or may be performed each time the error calibration apparatus 100 is used in practical use, or may be performed each time the PVT of the TDC changes.
Regarding the preparation phase: the phase shift controller 110 may shift the feedback clock output by the DCO at the first time and/or a preset reference clock to form a preset phase difference, and input the reference clock and the feedback clock forming the preset phase difference to the TDC, where the feedback clock output by the DCO at the first time is actually the feedback clock output by the DCO through the frequency divider, and for convenience of understanding, the feedback clock output by the DCO through the frequency divider is hereinafter collectively described as the feedback clock output by the DCO at the first time.
The output calibrator 120 records a check code outputted from the TDC, wherein the check code is the predetermined phase difference/unit delay of the inverter in the TDC.
Further, after the preparation phase is completed, the error calibration apparatus 100 may enter the practical application phase.
Regarding the actual application phase: the phase offset controller 110 is configured to input the feedback clock output by the DCO at the second time and the preset reference clock to the TDC again;
the output calibrator 120 compares the actual code output by the TDC with the check code, and outputs the comparison result to the digital loop filter, where the actual code is the actual phase difference/unit delay between the feedback clock output by the DCO at the second time and the preset reference clock.
It can be understood that, the output calibrator 120 stores the check code equal to the preset phase difference/unit delay in the preparation stage, and after the TDC outputs the actual code equal to the actual phase difference/unit delay after being put into practical use, the output calibrator 120 can eliminate the unit delay included in the actual code and the check code by comparing the actual code with the check code, so that the result output to the digital loop filter is not unstable due to the influence of the unit delay change, and the clock jitter of the DCO output is alleviated.
It should be noted that the first time is a certain time in the preparation phase, and the second time is a certain time in the actual application phase, which can be selected according to actual requirements.
The principle of the error calibration apparatus 100 will be described in detail from the preparation stage and the actual application stage, respectively.
1. Aiming at the preparation stage:
in this embodiment, for convenience of calculation, the predetermined phase difference may be one clock cycle, and to ensure that the offset precision is high, the phase offset controller 110 may perform two offsets in a half clock cycle unit to combine to form the predetermined phase difference of one clock cycle.
As a first exemplary way of shifting by half a clock cycle, in each of the two shifts, the phase shift controller 110 may shift only the feedback clock that the DCO outputs at the first time.
Illustratively, the phase offset controller 110 is configured to pre-offset the feedback clock output by the DCO at the first time such that the pre-offset feedback clock is advanced by a half clock period of the preset reference clock, and input the pre-offset feedback clock and the preset reference clock into the TDC.
And a phase offset controller 110 for post-offsetting the feedback clock output by the DCO at the first time, such that the post-offset feedback clock is placed at the preset reference clock half a clock period later, and inputting the post-offset feedback clock and the preset reference clock into the TDC.
Thus, the leading half clock cycle and the trailing half clock cycle are added up, i.e., the shift by one clock cycle as a whole is realized.
Referring to fig. 2, as a specific way to implement the two offsets, since the two offsets are involved, the phase offset controller 110 is required to control the timing of the two offsets, and therefore, the phase offset controller 110 may include: a state machine 111, and a phase shift circuit 112 connected to the state machine 111. The state machine 111 may be used to connect to the TDC and the DCO, respectively, and the phase shift circuit 112 is used to connect to the TDC.
The state machine 111 is configured to control the phase shift circuit 112 to sequentially execute a timing shift twice by half a clock cycle through a preset control logic. For example, after the state machine 111 receives the feedback clock output by the DCO at the first time and the preset reference clock, the state machine 111 outputs the feedback clock output by the DCO at the first time and the preset reference clock to the phase shift circuit 112 according to the preset control logic, and then the state machine 111 sends a first instruction for instructing the phase shift circuit 112 to perform a first half-clock-cycle shift to the phase shift circuit 112 and sends a second instruction for instructing the phase shift circuit 112 to perform a second half-clock-cycle shift to the phase shift circuit 112 according to the preset control logic, wherein the first instruction and the second instruction are both digital signals for convenience of control.
It should be noted that the interval between the sending of the first instruction and the sending of the second instruction may be set longer to ensure that the phase shift circuit 112 sends the second instruction after the first half clock cycle of shift has been performed according to the first instruction.
Correspondingly, the phase shift circuit 112 is configured to sequentially shift the feedback clock output by the DCO at the first time by a pre-shift and a post-shift according to the first instruction and the second instruction received successively. For example, the phase shift circuit 112 receives a feedback clock outputted by the DCO at a first time and a preset reference clock inputted by the state machine 111; then, the phase shift circuit 112 receives a first instruction sent by the state machine 111, and under the trigger of the first instruction, performs pre-shift on the feedback clock output by the DCO at the first time compared with the preset reference clock, so that the pre-shifted feedback clock is placed in the preset reference clock by half a clock cycle, wherein in the process of pre-shift, the phase shift circuit 112 may continuously detect the change of the phase difference between the offsetting feedback clock and the preset reference clock, and when detecting that the phase difference changes to the pre-half clock cycle, stops shifting; after the first offset, the phase shift circuit 112 inputs the pre-offset feedback clock and the predetermined reference clock into the TDC. Then, the phase shift circuit 112 receives a second instruction sent by the state machine 111, and under the trigger of the second instruction, performs post-shift on the feedback clock output by the DCO at the first time compared with the preset reference clock, so that the post-shifted feedback clock is placed in the preset reference clock by half a clock cycle, wherein in the process of post-shift, the phase shift circuit 112 may also continuously detect the change of the phase difference between the shifting feedback clock and the preset reference clock, and when detecting that the phase difference changes to the post-shifted half clock cycle, stops shifting; after the second offset, the phase offset circuit 112 inputs the post-offset feedback clock and the predetermined reference clock into the TDC.
In this embodiment, after receiving the feedback clock of the pre-offset output by the phase offset circuit 112 and the preset reference clock, the TDC may determine the phase difference to be a half clock period ahead. And, since the feedback clock of the pre-offset is advanced by a preset reference clock by half a clock period, the TDC determines that the phase difference is positive, and the TDC determines that the first code is positive by dividing the positive phase difference by a unit delay time preset by itself, and outputs it to the output calibrator 120. Thereafter, after receiving the post-shifted feedback clock output by the phase shift circuit 112 and the preset reference clock, the TDC may determine the phase difference to be a post-half clock period. And, since the feedback clock of the post offset is placed in the preset reference clock for half a clock cycle later, the TDC determines that the phase difference is negative, and the TDC can determine a negative second code by dividing the negative phase difference by the unit delay time preset by itself and output it to the output calibrator 120.
Referring to fig. 3A and 3B, the present solution is described below by way of an example.
Assume that 1: when the loop of the phase-locked loop is in a state of being locked but not completely locked, the calibration starts, and the feedback clock output by the DCO at the first moment is almost in phase with the preset reference clock. Then, the phase shift circuit 112 does not adjust the predetermined reference clock and pre-shifts the feedback clock outputted by the DCO at the first time to a phase difference of T/2 along the direction of V1 under the trigger of the first instruction, so that the pre-shifted feedback clock is advanced by half a clock period T/2 compared with the predetermined reference clock, where T is the clock frequency period outputted by the DCO. Then, the phase shift circuit 112 does not adjust the predetermined reference clock and shifts the feedback clock outputted by the DCO at the first time to be a phase difference of T/2 along the direction of V2 under the trigger of the second instruction, so that the feedback clock shifted backward is shifted half clock cycle ahead of the predetermined reference clock by T/2.
In the present embodiment, as a second exemplary manner of performing the offset with a half clock cycle, in each offset of the two offsets, the phase offset controller 110 offsets both the feedback clock output by the DCO at the first time and the preset reference clock.
Illustratively, the phase offset controller 110 is configured to pre-offset the feedback clock output by the DCO at the first time and post-offset a preset reference clock such that the pre-offset feedback clock is pre-offset by half a clock period of the post-offset reference clock, and input the pre-offset feedback clock and the post-offset reference clock into the TDC.
And the phase offset controller 110 is further configured to post-offset the feedback clock output by the DCO at the first time, pre-offset a preset reference clock, so that the post-offset feedback clock is post-offset by half a clock period of the pre-offset reference clock, and input the post-offset feedback clock and the pre-offset reference clock into the TDC.
Thus, the addition of the leading half clock cycle and the trailing half clock cycle also achieves an overall shift of one clock cycle.
Referring to fig. 2, as a specific way to implement the two-time offset, since the two-time offset is also involved, the phase offset controller 110 is also required to control the timing of the two-time offset, and therefore, the phase offset controller 110 may also include: a state machine 111, and a phase shift circuit 112 connected to the state machine 111. The state machine 111 may be used to connect to the TDC and the DCO, respectively, and the phase shift circuit 112 is used to connect to the TDC.
The state machine 111 is also used to control the phase shift circuit 112 to perform the timing shift twice in half clock cycle by using a preset control logic. For example, after the state machine 111 receives the feedback clock output by the DCO at the first time and the preset reference clock, the state machine 111 outputs the feedback clock output by the DCO at the first time and the preset reference clock to the phase shift circuit 112 according to the preset control logic, and then the state machine 111 sends a first instruction for instructing the phase shift circuit 112 to perform a first half-clock-cycle shift to the phase shift circuit 112 and sends a second instruction for instructing the phase shift circuit 112 to perform a second half-clock-cycle shift to the phase shift circuit 112 according to the preset control logic, wherein the first instruction and the second instruction are both digital signals for convenience of control.
It should be noted that the interval between the sending of the first instruction and the sending of the second instruction may be set longer to ensure that the phase shift circuit 112 sends the second instruction after the first half clock cycle of shift has been performed according to the first instruction.
Correspondingly, the phase shift circuit 112 is configured to sequentially shift the feedback clock output by the DCO at the first time and the preset reference clock twice according to the first instruction and the second instruction received successively. For example, the phase shift circuit 112 receives a feedback clock outputted by the DCO at a first time and a preset reference clock inputted by the state machine 111; then, the phase shift circuit 112 receives the first instruction sent by the state machine 111, and under the trigger of the first instruction, performs forward shift on the feedback clock output by the DCO at the first time compared with the preset reference clock, and performs backward shift on the preset reference clock compared with the feedback clock output by the DCO at the first time, so that the forward shifted feedback clock is placed in front of the backward shifted reference clock by half a clock period. After the first offset is completed, the phase offset circuit 112 inputs the pre-offset feedback clock and the post-offset reference clock into the TDC. Then, the phase shift circuit 112 receives a second instruction sent by the state machine 111, and under the trigger of the second instruction, performs post-shift on the feedback clock output by the DCO at the first time compared with the preset reference clock, and performs pre-shift on the preset reference clock compared with the feedback clock output by the DCO at the first time, so that the post-shifted feedback clock is placed at the post-shifted reference clock by half a clock period. After the second offset is completed, the phase offset circuit 112 inputs the post-offset feedback clock and the pre-offset reference clock into the TDC.
In this embodiment, after receiving the feedback clock of the pre-offset and the reference clock of the post-offset output by the phase offset circuit 112, the TDC may determine the phase difference to be a first half clock period. Also, since the feedback clock of the pre-offset is preceded by the reference clock of the post-offset by half a clock cycle, the TDC determines that the phase difference is positive, and the TDC determines that the first code is positive by dividing the positive phase difference by a unit delay time preset by itself, and outputs the first code to the output calibrator 120. Thereafter, upon receiving the post-shifted feedback clock and the pre-shifted reference clock output from the phase shift circuit 112, the TDC can determine a phase difference of a post-half clock period. And, since the feedback clock of the post offset is placed at the half clock cycle of the reference clock of the pre offset, the TDC determines that the phase difference is negative, and the TDC can determine a negative second code by dividing the negative phase difference by a unit delay preset by itself and output it to the output calibrator 120.
Referring to fig. 4A and 4B, the present solution is also described below by way of an example.
Assume 2: when the loop of the phase-locked loop is in a state of being locked but not completely locked, the calibration starts, and the feedback clock output by the DCO at the first moment is almost in phase with the preset reference clock. Then, the phase shift circuit 112 pre-shifts the feedback clock outputted by the DCO at the first time in the direction of V1 and post-shifts the preset reference clock in the direction of V2 under the trigger of the first instruction, so that the pre-shifted feedback clock is advanced by half a clock period T/2 compared with the post-shifted reference clock, where T is the clock frequency period outputted by the DCO. Then, the phase shift circuit 112, triggered by the second command, shifts the feedback clock outputted by the DCO at the first time backward in the direction of V2 and shifts the preset reference clock forward in the direction of V1, so that the backward shifted feedback clock is shifted by a half clock period T/2 after the forward shifted reference clock.
In the present embodiment, as a third exemplary manner of performing the shift with a half clock cycle, the phase shift controller 110 may shift only the preset reference clock in each shift of the two shifts.
Illustratively, the phase offset controller 110 is configured to post-offset a preset reference clock such that the feedback clock output by the DCO at the first time is preceded by the post-offset reference clock by half a clock period, and input the feedback clock output by the DCO at the first time and the post-offset reference clock into the TDC.
And a phase offset controller 110, further configured to pre-offset a preset reference clock, so that the feedback clock output by the DCO at the first time is followed by the pre-offset reference clock by half a clock period, and input the feedback clock output by the DCO at the first time and the pre-offset reference clock into the TDC.
Thus, the addition of the leading half clock cycle and the trailing half clock cycle also achieves an overall shift of one clock cycle.
Referring to fig. 2, as a specific way to implement the two-time offset, since the two-time offset is involved, the phase offset controller 110 is also required to control the timing of the two-time offset, and therefore, the phase offset controller 110 may also include: a state machine 111, and a phase shift circuit 112 connected to the state machine 111. The state machine 111 may be used to connect to the TDC and the DCO, respectively, and the phase shift circuit 112 is used to connect to the TDC.
The state machine 111 is also used to control the phase shift circuit 112 to perform the timing shift twice in half clock cycle by using a preset control logic. For example, after the state machine 111 receives the feedback clock output by the DCO at the first time and the preset reference clock, the state machine 111 outputs the feedback clock output by the DCO at the first time and the preset reference clock to the phase shift circuit 112 according to the preset control logic, and then the state machine 111 sends a first instruction for instructing the phase shift circuit 112 to perform a first half-clock-cycle shift to the phase shift circuit 112 and sends a second instruction for instructing the phase shift circuit 112 to perform a second half-clock-cycle shift to the phase shift circuit 112 according to the preset control logic, wherein for convenience of control, the first instruction and the second instruction are both digital signals.
It should be noted that the interval between the sending of the first instruction and the sending of the second instruction may be set longer to ensure that the phase shift circuit 112 sends the second instruction after the first half clock cycle of shift has been performed according to the first instruction.
Correspondingly, the phase shift circuit 112 is configured to sequentially shift the preset reference clock to the rear position and shift the preset reference clock to the front position according to the first instruction and the second instruction received successively. For example, the phase shift circuit 112 receives a feedback clock outputted by the DCO at a first time and a preset reference clock inputted by the state machine 111; then, the phase shift circuit 112 receives the first instruction sent by the state machine 111, and performs post-shift on the preset reference clock compared with the feedback clock output by the DCO at the first time under the trigger of the first instruction, so that the feedback clock output by the DCO at the first time is advanced by half a clock period of the post-shifted reference clock. After the first offset is completed, the phase offset circuit 112 inputs the pre-offset reference clock and the feedback clock output by the DCO at the first time into the TDC. Then, the phase shift circuit 112 receives a second instruction sent by the state machine 111, and under the trigger of the second instruction, performs pre-shift on the preset reference clock compared with the feedback clock output by the DCO at the first time, so that the feedback clock output by the DCO at the first time is placed behind the pre-shifted reference clock by half a clock period. After the second offset is completed, the phase offset circuit 112 inputs the feedback clock outputted by the DCO at the first time and the pre-offset reference clock into the TDC.
In this embodiment, after the TDC receives the post-offset reference clock output by the phase offset circuit 112 and the feedback clock output by the DCO at the first time, the TDC may determine the phase difference to be a half clock period ahead. Also, since the feedback clock outputted by the DCO at the first time is preceded by the post-shifted reference clock by half a clock period, the TDC determines that the phase difference is positive, and the TDC determines that the first code is positive by dividing the positive phase difference by the unit delay time preset by itself, and outputs the first code to the output calibrator 120. Thereafter, after the TDC receives the pre-shifted reference clock output from the phase shift circuit 112 and the feedback clock output from the DCO at the first time, the TDC can determine a phase difference by a second half clock period. Also, since the feedback clock outputted by the DCO at the first time is followed by the pre-shifted reference clock by half a clock period, the TDC determines that the phase difference is negative, and the TDC determines that the second code is negative by dividing the negative phase difference by the unit delay preset by itself, and outputs the second code to the output calibrator 120.
Referring to fig. 5A and 5B, the present solution is described below by way of an example.
Assume that 3: when the loop of the phase-locked loop is in a state of being locked but not completely locked, the calibration starts, and the feedback clock output by the DCO at the first moment is almost in phase with the preset reference clock. Then, the phase shift circuit 112, triggered by the first instruction, does not adjust the feedback clock output by the DCO at the first time, and shifts the preset reference clock back to a phase difference of T/2 along the direction of V2, so that the feedback clock output by the DCO at the first time is shifted forward by half a clock cycle T/2 compared with the reference clock shifted back, where T is the clock frequency cycle output by the DCO. Then, the phase shift circuit 112 neither adjusts the feedback clock outputted by the DCO at the first time point, nor pre-shifts the preset reference clock to a phase difference of T/2 in the direction of V1 under the trigger of the second instruction by the phase shift circuit 112, so that the feedback clock outputted by the DCO at the first time point is shifted forward by a half clock period T/2 compared with the pre-shifted reference clock.
With continued reference to fig. 2, the output calibrator 120 may include: the memory 121, a subtractor 122 connected to the memory 121, a divider 123 connected to the subtractor 122, and a multiplier 123 connected to the divider 123. The memory 121 is further configured to be connected to an output of the TDC, the divider 123 is further configured to be connected to an output of the TDC, and the multiplier 123 is configured to be connected to an input of the digital loop filter.
In this embodiment, since the memory 121 is connected to the phase shift controller 110, for example, connected to the phase shift circuit 112 in the phase shift controller 110, the memory 121 can store the first code and the second code output by the phase shift circuit 112. Based on the control of the phase shift controller 110, for example, when the check code needs to be calculated, the memory 121 receives a third instruction sent by the state machine 111 in the phase shift controller 110, and outputs the first code and the second code to the subtractor 122 under the trigger of the third instruction. The subtractor 122 subtracts the second code from the first code to obtain a check code, and outputs the check code to the divider 123.
It should be noted that the divider 123 and the multiplier 123 operate in an actual application stage, and therefore, the principle of the divider 123 and the multiplier 123 is described in the actual application stage.
It should be noted that the manner of performing the offset twice in half a clock cycle in the present embodiment is only an exemplary manner of the present embodiment, and is not limited thereto. For example, in the case where the accuracy requirement is not very high, the phase shift controller 110 may directly perform the shift once to form the preset phase difference of one clock cycle. It will be appreciated that since the entire process only performs the offset once, the state machine 111 does not need to control the timing of the offset, and the output calibrator 120 may not include the subtractor 122 (the memory 121 is directly connected to the divider 123).
2. Aiming at the actual application stage:
after the check code is determined in the preparation stage, the phase shift controller 110 may directly input the feedback clock output by the DCO at the second time and the preset reference clock into the TDC without inputting the feedback clock output by the DCO and the preset reference clock into the TDC, for example, after receiving the feedback clock output by the DCO at the second time, the state machine 111 inputs the feedback clock output by the DCO at the second time and the preset reference clock into the TDC.
In this embodiment, after receiving the feedback clock output by the DCO at the second time and the preset reference clock input by the state machine 111, the TDC can determine an actual phase difference between the feedback clock output by the DCO at the second time and the preset reference clock, and divide the actual phase difference by the unit delay preset by itself, so as to determine an actual code, and output the actual code to the output calibrator 120.
Further, since the divider 123 in the output calibrator 120 is connected to the output of the TDC, the divider 123 may receive the actual code of the TDC output. Since the divider 123 already obtains the check code output by the subtractor 122 before the actual code is received, the divider 123 can divide the check code and the actual code to obtain the quotient after obtaining the actual code.
It can be understood that the quotient obtained by dividing the check code by the actual code is very different from the code output by the TDC in the standard unit delay, so that the quotient obtained by dividing the check code by the actual code cannot be directly input to the digital loop filter, and the quotient obtained by dividing the check code by the actual code needs to be enlarged by the multiplier 123 to be in the same dimension as the code output by the TDC in the standard unit delay to output the code. In other words, a preset value is preset in the multiplier 123, a quotient obtained by dividing the check code by the actual code is output to the multiplier 123 through the divider 123, and the multiplier 123 obtains a final result by multiplying the quotient by the preset value, thereby outputting the result to the digital loop filter. For example, if the standard unit delay is 2ms and the TDC determines a phase difference of 300ms, the TDC outputs a code of 150. If the check code is divided by the actual code, its value may be 27, so it is necessary to multiply by 5 on a 27 basis to have the final outputs 135 and 150 in the same dimension.
Based on the same inventive concept, the embodiment of the present application further provides an error calibration method, and a flow of the error calibration method may include:
step S100: inputting a feedback clock and a preset reference clock output by a DCO (digital data output) in the phase-locked loop at the second moment into a TDC (time to live) in the phase-locked loop;
step S200: comparing the actual code output by the TDC with a preset check code, and outputting the comparison result to a digital loop filter in the phase-locked loop;
wherein the actual coding is a unit delay of the TDC/a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock; the check code is as follows: obtaining by shifting a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC; and the check code is the preset phase difference/the unit delay.
Optionally, step S200 may further include: dividing the check code and the actual code to obtain a quotient value; and multiplying the quotient value by a preset value to obtain the result, and outputting the result to the digital loop filter.
Optionally, the step of determining the check code includes:
step S101: pre-offsetting a feedback clock output by the DCO at a first moment to enable the pre-offset feedback clock to be positioned in front of the preset reference clock by half a clock period, and inputting the pre-offset feedback clock and the preset reference clock into the TDC; and post-shifting a feedback clock output by the DCO at a first time, so that the post-shifted feedback clock is placed in the preset reference clock for a half clock period later, and inputting the post-shifted feedback clock and the preset reference clock into the TDC;
step S201: and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
Optionally, the step of determining the check code further includes:
step S301: pre-offsetting a feedback clock output by the DCO at a first moment, post-offsetting the preset reference clock to enable the pre-offset feedback clock to be pre-positioned in a post-offset reference clock by half a clock period, and inputting the pre-offset feedback clock and the post-offset reference clock into the TDC; and post-offsetting the feedback clock output by the DCO at the first time, pre-offsetting the preset reference clock, enabling the post-offset feedback clock to be placed at the post-offset reference clock half clock period later, and inputting the post-offset feedback clock and the pre-offset reference clock into the TDC;
step S401: and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
Optionally, the step of determining the check code further includes:
step S501: the preset reference clock is subjected to post-offset, so that a feedback clock output by the DCO at a first moment is positioned in front of the post-offset reference clock by half a clock period, and the feedback clock output by the DCO and the post-offset reference clock are input into the TDC; pre-offsetting the preset reference clock, enabling a feedback clock output by the DCO at a first moment to be positioned at a half clock period of the pre-offset reference clock, and inputting the feedback clock output by the DCO at the first moment and the pre-offset reference clock into the TDC;
step S601: and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
It should be noted that, as those skilled in the art can clearly understand, for convenience and brevity of description, the specific working process of the method described above may refer to the corresponding process in the foregoing device embodiment, and is not described herein again. Meanwhile, the method can be implemented by the device not only, but also by other devices.
Referring to fig. 6, based on the same inventive concept, an embodiment of the present application further provides a phase-locked loop 10, where the phase-locked loop 10 may be applied in a chip, for example, the phase-locked loop 10 may be connected to a chip core (i.e., a core processing circuit of the chip) in the chip, and the phase-locked loop 10 may include: output calibrator 120, DCO11, TDC12, digital loop filter 13.
Of course, in practical applications, the phase locked loop 10 may also include more components, such as DSM14, thermal encoder 15, current generator 16, and frequency divider 17.
The output calibrator 120 is connected to the output of the TDC12 and the input of the digital loop filter 13, the output of the digital loop filter 13 is connected to the input of the DSM14 and the input of the thermal encoder 15, the output of the DSM14 and the output of the thermal encoder 15 are connected to the input of the current generator 16, the output of the current generator 16 is connected to the control terminal of the DCO11, and the output of the DCO11 is connected to the input of the TDC12 through the frequency divider 17.
DCO11 for outputting the feedback clock to TDC12 via divider 17 at the second time.
The TDC12 is configured to determine an actual code according to the feedback clock and a preset reference clock, and output the actual code to the output calibrator 120.
An output calibrator 120 for comparing the actual code with a preset check code and outputting the result of the comparison to the digital loop filter 13; the actual coding is the unit delay of the phase difference/TDC 12 between the feedback clock output by the DCO11 at the second moment and the preset reference clock; the check code is: obtained by shifting the feedback clock outputted by the DCO11 at the first timing and/or a preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC 12; checking coding as a preset phase difference/unit delay;
a digital loop filter 13 for filtering the result and inputting it to DSM14 and to thermal encoder 15.
DSM14, for filtering the noise in the fractional part of the filtered code and inputting it to current generator 16 after filtering.
A thermal encoder 15 for converting the filtered integer part of the code into a thermometer code and inputting the thermometer code also to the current generator 16.
The current generator 16 is used for controlling the oscillation of the DCO11 based on the input parameters to adjust the clock output by the DCO11, thereby forming a closed-loop regulation.
As shown in fig. 7, in this embodiment, the phase-locked loop 10 may further include: a phase offset controller 110, the phase offset controller 110 being coupled to an input of the DCO11 and an output of the TDC 12.
And a phase shift controller 110 for shifting the feedback clock outputted from the DCO11 at the first time and/or a preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC 12.
It should be noted that, as those skilled in the art can clearly understand, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing embodiments of the apparatuses, and are not described herein again.
Some embodiments of the present application further provide a computer-readable storage medium of a computer-executable non-volatile program code, which can be a general-purpose storage medium, such as a removable magnetic disk, a hard disk, or the like, and the computer-readable storage medium has a program code stored thereon, and when the program code is executed by a computer, the method of the error calibration method of any of the above embodiments is performed.
The program code product of the error calibration method provided in the embodiment of the present application includes a computer-readable storage medium storing the program code, and instructions included in the program code may be used to execute the method in the foregoing method embodiment, and specific implementation may refer to the method embodiment, which is not described herein again.
In summary, the output calibrator presets the check code equal to the preset phase difference/unit delay, and after the TDC outputs the actual code equal to the actual phase difference/unit delay, the output calibrator compares the actual code with the check code, so as to eliminate the unit delay included in the actual code and the check code, so that the result output to the digital loop filter is not unstable due to the influence of the unit delay change, and the jitter of the clock output by the DCO is alleviated.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (14)

1. An error calibration apparatus, the apparatus comprising:
the phase offset controller is used for being connected with the output end of the DCO in the phase-locked loop and the input end of the TDC;
an output calibrator connected to an output of the TDC and an input of a digital loop filter in the phase-locked loop;
the phase offset controller is used for inputting a feedback clock output by the DCO at a second moment and a preset reference clock into the TDC;
the output calibrator is used for comparing the actual code output by the TDC with a preset check code and outputting the comparison result to the digital loop filter;
wherein the actual coding is a unit delay of the TDC/a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock; the check code is as follows: shifting, by the phase shift controller, a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC; and the check code is the preset phase difference/the unit delay.
2. The error calibration device of claim 1,
the phase offset controller is used for pre-offsetting the feedback clock output by the DCO at the first moment, so that the pre-offset feedback clock is advanced to the preset reference clock by half a clock period, and inputting the pre-offset feedback clock and the preset reference clock into the TDC; the feedback clock output by the DCO at the first moment is subjected to post-offset, so that the post-offset feedback clock is placed in the preset reference clock for half a clock period later, and the post-offset feedback clock and the preset reference clock are input into the TDC;
the output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code is a preceding half clock cycle/the unit delay, and the second code is a succeeding half clock cycle/the unit delay.
3. The error calibration device of claim 2, wherein the phase offset controller comprises: a state machine and a phase shift circuit;
the state machine is configured to output a feedback clock output by the DCO at a first time and the preset reference clock to the phase offset circuit, and send a first instruction to the phase offset circuit first and then send a second instruction to the phase offset circuit;
the phase shift circuit is configured to, after receiving a feedback clock output by the DCO at a first time and the preset reference clock, pre-shift the feedback clock output by the DCO at the first time according to the first instruction, input the pre-shifted feedback clock and the preset reference clock to the TDC, post-shift the feedback clock output by the DCO at the first time according to the second instruction, and input the post-shifted feedback clock and the preset reference clock to the TDC;
and the state machine is further used for inputting the feedback clock output by the DCO at the second moment and the preset reference clock into the TDC.
4. The error calibration device of claim 1,
the phase offset controller is used for pre-offsetting the feedback clock output by the DCO at the first moment and post-offsetting the preset reference clock, so that the pre-offset feedback clock is pre-offset in a post-offset reference clock by half a clock period, and the pre-offset feedback clock and the post-offset reference clock are input into the TDC; the TDC is also used for post-shifting the feedback clock output by the DCO at the first moment, pre-shifting the preset reference clock, enabling the post-shifted feedback clock to be placed at the post-shifted reference clock half clock period later, and inputting the post-shifted feedback clock and the pre-shifted reference clock into the TDC;
the output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code is a preceding half clock cycle/the unit delay, and the second code is a succeeding half clock cycle/the unit delay.
5. The error calibration device of claim 1,
the phase offset controller is used for post-offsetting the preset reference clock, so that the feedback clock output by the DCO at the first moment is positioned in front of the post-offset reference clock by half a clock period, and the feedback clock output by the DCO and the post-offset reference clock are input into the TDC; the TDC is also used for pre-offsetting the preset reference clock, enabling the feedback clock output by the DCO at the first moment to be positioned at the reference clock of the pre-offset by half a clock period, and inputting the feedback clock output by the DCO at the first moment and the reference clock of the pre-offset into the TDC;
the output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code is a preceding half clock cycle/the unit delay, and the second code is a succeeding half clock cycle/the unit delay.
6. The error calibration device of any one of claims 2-5, wherein the output calibrator comprises: the phase offset controller comprises a memory, a subtracter, a divider and a multiplier, wherein the memory is respectively connected with the subtracter and the phase offset controller, and the subtracter is connected with the divider; the memory is further configured to be coupled to an output of the TDC, the divider is configured to be coupled to an output of the TDC, and the multiplier is configured to be coupled to an input of the digital loop filter;
the memory is used for storing the first code and the second code; and a phase shift controller for outputting the first code and the second code to the subtractor based on control of the phase shift controller;
the subtracter is used for subtracting the first code from the second code to obtain the check code and outputting the check code to the divider;
the divider is used for dividing the check code and the actual code to obtain a quotient value and outputting the quotient value to the multiplier;
and the multiplier is used for multiplying the quotient value by a preset value to obtain the result and outputting the result to the digital loop filter.
7. A method of error calibration, the method comprising:
inputting a feedback clock and a preset reference clock output by a DCO (digital data output) in the phase-locked loop at the second moment into a TDC (time to live) in the phase-locked loop;
comparing the actual code output by the TDC with a preset check code, and outputting the comparison result to a digital loop filter in the phase-locked loop;
wherein the actual coding is a unit delay of the TDC/a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock; the check code is as follows: obtaining by shifting a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC; and the check code is the preset phase difference/the unit delay.
8. The error calibration method of claim 7, wherein the step of determining the check code comprises:
pre-offsetting a feedback clock output by the DCO at a first moment to enable the pre-offset feedback clock to be positioned in front of the preset reference clock by half a clock period, and inputting the pre-offset feedback clock and the preset reference clock into the TDC; and post-shifting a feedback clock output by the DCO at a first time, so that the post-shifted feedback clock is placed in the preset reference clock for a half clock period later, and inputting the post-shifted feedback clock and the preset reference clock into the TDC;
and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
9. The error calibration method of claim 7, wherein the step of determining the check code comprises:
pre-offsetting a feedback clock output by the DCO at a first moment, post-offsetting the preset reference clock to enable the pre-offset feedback clock to be pre-positioned in a post-offset reference clock by half a clock period, and inputting the pre-offset feedback clock and the post-offset reference clock into the TDC; and post-offsetting the feedback clock output by the DCO at the first time, pre-offsetting the preset reference clock, enabling the post-offset feedback clock to be placed at the post-offset reference clock half clock period later, and inputting the post-offset feedback clock and the pre-offset reference clock into the TDC;
and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
10. The error calibration device of claim 7, wherein the step of determining the check code comprises:
the preset reference clock is subjected to post-offset, so that a feedback clock output by the DCO at a first moment is positioned in front of the post-offset reference clock by half a clock period, and the feedback clock output by the DCO and the post-offset reference clock are input into the TDC; pre-offsetting the preset reference clock, enabling a feedback clock output by the DCO at a first moment to be positioned at a half clock period of the pre-offset reference clock, and inputting the feedback clock output by the DCO at the first moment and the pre-offset reference clock into the TDC;
and recording a first code and a second code output by the TDC, and determining the check code according to the first code and the second code, wherein the first code is a front half clock cycle/the unit delay, and the second code is a rear half clock cycle/the unit delay.
11. The error calibration method according to any one of claims 7-10, wherein comparing the actual code output from the TDC with a preset check code and outputting the comparison result to a digital loop filter in the phase-locked loop comprises:
dividing the check code and the actual code to obtain a quotient value;
and multiplying the quotient value by a preset value to obtain the result, and outputting the result to the digital loop filter.
12. A phase locked loop, comprising: the digital loop filter comprises an output calibrator, a DCO, a TDC and a digital loop filter; the output calibrator is connected with the output end of the TDC and the input end of the digital loop filter, the output end of the DCO is connected with the input end of the TDC, and the digital loop filter is connected with the input end of the DCO;
the DCO is used for outputting a feedback clock to the TDC at a second moment;
the TDC is used for determining an actual code according to the feedback clock and a preset reference clock and outputting the actual code to the output calibrator;
the output calibrator is used for comparing the actual code with a preset check code and outputting a comparison result to the digital loop filter; wherein the actual coding is a unit delay of the TDC/a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock; the check code is as follows: obtaining by shifting a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference to the TDC; the check code is the preset phase difference/the unit delay;
and the digital loop filter is used for filtering the result and inputting the result into the DCO so as to adjust the output of the DCO.
13. The phase locked loop of claim 12, further comprising: the phase offset controller is connected with the output end of the DCO and the input end of the TDC;
the phase shift controller is configured to shift a feedback clock output by the DCO at a first time and/or the preset reference clock to form a preset phase difference, and input the reference clock and the feedback clock forming the preset phase difference to the TDC.
14. A chip, comprising: a chip core, and a phase locked loop according to claim 12 or 13 connected to the chip core.
CN202010846989.3A 2020-08-20 2020-08-20 Error calibration device and method, phase-locked loop and chip Pending CN111934674A (en)

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