CN113852370A

CN113852370A - Phase jitter compensation method, module and digital phase-locked loop

Info

Publication number: CN113852370A
Application number: CN202010601752.9A
Authority: CN
Inventors: 庞瑞; 刘法恩; 曹雯
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2021-12-28
Also published as: WO2022001940A1

Abstract

The application discloses a phase jitter compensation method, a module and a digital phase-locked loop. The phase jitter compensation method comprises the following steps: acquiring a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determining duty ratio mismatch information according to the phase error signal of the current period and the phase error signal of the adjacent previous period, wherein the phase error signal comprises a digital signal formed by a difference value between an input reference signal phase and a feedback signal phase; generating current phase compensation information according to the duty ratio mismatch information; and correcting the phase error signal in the current period by adopting the current phase compensation information, and sending the corrected phase error signal to the digital phase-locked loop so as to perform phase tracking again according to the corrected phase error signal. According to the technical scheme of the embodiment of the application, the calibration precision can be improved, and the area of a circuit required by calibration is reduced.

Description

Phase jitter compensation method, module and digital phase-locked loop

Technical Field

The present application relates to the field of phase-locked loops, and in particular, to a phase jitter compensation method, module and digital phase-locked loop.

Background

At present, the 6 th generation wireless technology standard 802.11ax supports a Modulation and demodulation mode of 1024 Quadrature Amplitude Modulation (QAM), and an Error Vector Amplitude (EVM) index of-35 dB thereof puts a strict requirement on clock quality and puts a great challenge on implementation of a clock circuit.

Generally, increasing the reference frequency of the phase-locked loop brings an improvement to the in-band noise performance of the output clock, which greatly relieves the design pressure of the high-performance phase-locked loop. Because the clock frequency of the off-chip reference clock crystal is fixed, the improvement of the reference clock frequency of the phase-locked loop is usually completed by an internal frequency multiplication circuit of the chip. If the input clock source has duty ratio mismatch, the reference frequency is increased by the frequency multiplier, and the edge of the reference clock has jitter, so that the in-band noise and spurious performance are deteriorated.

In the prior art, the duty ratio calibration circuit is usually implemented in an analog manner. The analog clock duty ratio calibration circuit comprises a filter, a voltage comparator, a duty ratio adjusting circuit and the like, the circuit scale is large, digital-analog circuit cooperation is needed, and the development design difficulty and the simulation verification period are improved. Moreover, the mismatch of the analog circuit limits the accuracy of the adjustment to the matching degree of the analog circuit, which makes the calibration effect difficult to reach an ideal state, and the consistency and reliability of the calibration are also affected by the processing procedure, Voltage and Temperature (PVT) and other factors.

Disclosure of Invention

The embodiment of the application provides a phase jitter compensation method, a phase jitter compensation module and a digital phase-locked loop, so that duty ratio calibration is realized in a mode of not increasing an analog circuit, the calibration precision is improved, the area of a circuit required by calibration is reduced, and the development difficulty is reduced.

In a first aspect, an embodiment of the present application provides a phase jitter compensation method applied in a digital phase-locked loop, including:

acquiring a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determining duty ratio mismatch information according to the phase error signal of the digital phase-locked loop in the current period and the phase error signal of the adjacent previous period, wherein the phase error signal comprises a digital signal formed by a difference value between an input reference signal phase and a feedback signal phase, the input reference signal is an input reference signal of the digital phase-locked loop, and the feedback signal is a feedback signal transmitted in a feedback loop of the digital phase-locked loop when the phase is locked;

generating current phase compensation information according to the duty ratio mismatch information;

and correcting the phase error signal in the current period by adopting the current phase compensation information, and sending the corrected phase error signal to the digital phase-locked loop so as to instruct the digital phase-locked loop to perform phase tracking again according to the corrected phase error signal.

In a second aspect, an embodiment of the present invention further provides a phase jitter compensation module, configured in a digital phase-locked loop, including:

the duty ratio mismatch detection module is used for acquiring a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determining duty ratio mismatch information according to the phase error signal of the current period and the phase error signal of the adjacent previous period, wherein the phase error signal comprises a digital signal formed by a difference value between an input reference signal phase and a feedback signal phase, the input reference signal is an input reference signal of the digital phase-locked loop, and the feedback signal is a feedback signal transmitted in a feedback loop of the digital phase-locked loop during phase locking;

the error accumulation module is used for generating current phase compensation information according to the duty ratio mismatch information;

and the calibration compensation module is used for correcting the phase error signal in the current period by adopting the current phase compensation information and sending the corrected phase error signal to the digital phase-locked loop so as to instruct the digital phase-locked loop to perform phase tracking again according to the corrected phase error signal.

In a third aspect, an embodiment of the present application further provides a digital phase-locked loop, including:

a phase comparison module, a phase jitter compensation module and a phase tracking module according to any of the embodiments of the present application;

the phase comparison module is connected with the phase tracking module and is used for acquiring an input reference signal and a feedback signal sent by the phase tracking module, performing phase comparison on the input reference signal and the feedback signal to generate a phase error signal and sending the phase error signal to the phase jitter compensation module;

the phase jitter compensation module is used for correcting the phase error signal so as to send the corrected phase error signal to the phase tracking module;

the phase tracking module is used for generating a feedback signal according to the corrected phase error signal and sending the feedback signal to the phase comparison module, and the feedback signal is used for indicating the phase comparison module to continuously adjust the phase error signal until the data in the phase error signal is constant.

The embodiment of the application adopts the phase jitter compensation method in the digital phase-locked loop, and obtains the duty ratio mismatch information by obtaining the phase error signal in the digital phase-locked loop, comparing the phase errors of adjacent periods, generating the current phase compensation information according to the duty ratio mismatch information, compensating the current phase compensation information into the phase error signal of the current period, sending the corrected phase error signal to the digital phase-locked loop, instructing the digital phase-locked loop to continue phase tracking according to the corrected phase error signal, realizing the compensation of the phase jitter caused by the duty ratio mismatch in the digital phase-locked loop, solving the problems of low calibration precision, large circuit area and the like caused by the fact that the analog circuit realizes the duty ratio calibration in the prior art, and being capable of simulating the calibration precision of the circuit calibration duty ratio, the calibration precision is improved, the calibration reliability is effectively improved, the calibration consistency is ensured, and the area of a calibration circuit is reduced.

Drawings

Fig. 1 is a schematic diagram of phase jitter caused by duty cycle mismatch according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of a phase jitter compensation method according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of a phase jitter compensation method according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a phase jitter compensation module according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a phase jitter compensation module according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a phase jitter compensation module according to an embodiment of the present disclosure;

FIG. 7 is a block diagram of an odd-even period detection module according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a duty cycle mismatch detection module according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a first direction modification module according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of an attenuator and accumulator provided in an embodiment of the present application;

fig. 11 is a schematic diagram of a second direction modification module according to an embodiment of the present disclosure;

fig. 12 is a schematic diagram of a phase jitter compensation module according to an embodiment of the present disclosure;

fig. 13 is a schematic diagram of a phase jitter compensation module according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a calibration compensation module according to an embodiment of the present disclosure;

FIG. 15 is a diagram of a digital phase-locked loop according to an embodiment of the present application;

FIG. 16 is a diagram of a digital phase-locked loop according to an embodiment of the present application;

fig. 17 is a schematic diagram of a phase error signal when a phase jitter compensation module stops working according to an embodiment of the present disclosure;

fig. 18 is a schematic diagram of a phase error signal when an SDM quantization noise calibration associated module provided in an embodiment of the present application operates;

fig. 19 is a schematic diagram of a phase error signal when a phase jitter compensation module according to an embodiment of the present disclosure operates;

fig. 20 is a schematic diagram of a phase error signal when a phase jitter compensation module stops working according to an embodiment of the present disclosure;

fig. 21 is a schematic diagram of a phase error signal when a phase jitter compensation module according to an embodiment of the present disclosure operates;

fig. 22 is a schematic diagram of a phase error signal when a phase jitter compensation module stops working according to an embodiment of the present disclosure;

fig. 23 is a schematic diagram of a phase error signal when a phase jitter compensation module provided in the embodiment of the present application operates and a module associated with SDM quantization noise calibration operates.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no peculiar meaning by themselves. Thus, "module", "component" or "unit" may be used mixedly.

To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Some indexes of the current modulation and demodulation mode put more strict requirements on the clock quality. Compared with the traditional Analog Phase-locked Loop, a Digital Phase-locked Loop (DPLL) has greater freedom in design and bandwidth configuration of a Loop filter, and the integral noise of a DPLL output clock can be adjusted to an optimal level by selecting appropriate Loop parameters. In addition, the full-digital implementation mode of the phase-locked loop also provides feasibility for increasing various digital calibration technologies, and the calibration technologies can effectively improve the performance of the phase-locked loop. Finally, DPLLs have significant area and performance advantages over APLLs under advanced processes. Thus, high performance clock generators are typically implemented in a DPLL manner.

Increasing the input reference signal frequency of the phase-locked loop will bring improvements to the in-band noise performance of the output clock, which greatly relieves the design pressure of high performance phase-locked loops. Because the clock frequency of the clock crystal for inputting the reference signal outside the chip is fixed, the frequency of the reference signal input by the phase-locked loop is usually increased by a frequency doubling circuit inside the chip. However, if the duty ratio of the input reference signal source is mismatched, the input reference signal edge may be jittered while the reference frequency is increased by the frequency multiplier. For example, as shown in fig. 1, the input reference signal is a square wave signal with a duty ratio of 50%, and the duty ratio may be a proportion of time of a high level in one period. But the duty cycle is not 50% due to bu, which is different between t1 and t0 of the input reference signal, due to the duty cycle mismatch phenomenon. Correspondingly, the phases of the real frequency doubling input reference signals in the adjacent periods are different after frequency doubling (the frequency is increased to be twice as much as the original frequency), and the actual frequency doubling input reference signals are shown to have different adjacent period durations. In fact, if there is no duty mismatch in the input reference signal, i.e. t1 and t0 of the input reference signal are the same, the phases of the ideal frequency-doubled input reference signal after frequency doubling in adjacent cycles are the same, and the duration of each cycle is t 2. Compared with an ideal frequency doubling input reference signal, the rising edge of a certain period in the real frequency doubling input reference signal is delayed by delta t, or the rising edge of a certain period is advanced by delta t, and it can be understood that the duty ratio mismatch causes the delta t jitter of the frequency doubling input reference signal. Specifically, if sampling is performed with the falling edge of the feedback signal, the rising edge of the input reference signal at odd cycles is jittered by Δ t. Such jitter degrades in-band noise and spurious performance. Therefore, in the phase-locked loop, a duty ratio calibration circuit is often required at the same time when the frequency multiplication circuit appears. Correspondingly, the digital phase-locked loop carries out phase tracking based on the ideal frequency doubling input reference signal, after the final phase locking, the phases of the generated feedback signals in adjacent periods are the same, and the phase error between the phase of the feedback signal and the phase of the ideal frequency doubling input reference signal is fixed and unchanged.

The current improved method is to use an analog duty cycle detection circuit to realize the calibration of the duty cycle. Generally, an analog clock duty ratio calibration circuit comprises a filter, a voltage comparator, a duty ratio adjusting circuit and the like, the circuit scale is large, digital-analog circuit cooperation is needed, and the development design difficulty and the simulation verification period are improved. In addition, the precision of the adjustment of the analog circuit is limited by the matching degree of the analog circuit, mismatch is introduced into the analog circuit, so that the calibration effect is difficult to reach an ideal state, the consistency and reliability of calibration are also influenced by PVT, and in addition, a filter in the duty ratio detection circuit can cause that the occupied area of a whole system chip is large, so that the digital phase-locked loop circuit is not suitable for the all-digital phase-locked loop circuit.

In order to solve the problem of duty ratio mismatch in the existing phase-locked loop, the method and the device creatively provide that the phase error sent by the phase comparison module is analyzed, wherein the phase error is a digital signal output by the digital phase-locked loop, the duty ratio difference is calculated and periodically accumulated to generate the current phase compensation value, and the phase error is compensated. Therefore, the duty cycle compensation technology of the invention can maximally inhibit the non-idealities caused by the reference clock duty cycle mismatch in the phase-locked loop, namely the problems of in-band noise deterioration and reference spurious.

In an exemplary implementation manner, fig. 2 is a flowchart of a phase jitter compensation method provided in an embodiment of the present application. The phase jitter compensation method is suitable for the condition of calibrating the duty ratio on the premise of not adding an additional analog circuit. The phase jitter compensation method is applied to the digital phase-locked loop, and the method can be executed by a phase jitter compensation module, and the phase jitter compensation module is configured in the digital phase-locked loop.

As shown in fig. 2, the phase jitter compensation method includes:

s110, obtaining a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determining duty ratio mismatch information according to the phase error signal of the current period and the phase error signal of the adjacent previous period, wherein the phase error signal comprises a digital signal formed by a difference value between an input reference signal phase and a feedback signal phase, the input reference signal is an input reference signal of the digital phase-locked loop, and the feedback signal is a feedback signal transmitted in a feedback loop of the digital phase-locked loop when the phase is locked.

In the embodiment of the application, the digital phase-locked loop comprises a phase comparison module and a phase tracking module, wherein the phase comparison module is used for acquiring the phase of an input reference signal and the phase of a feedback signal, comparing the phases, generating a phase error, and sending the phase error to the phase tracking module. The phase tracking module is used for generating an output signal according to the phase error, determining a feedback signal according to the output signal, and sending the feedback signal to the phase comparison module so as to instruct the phase comparison module to continuously compare the phase error between the phase of the input reference signal and the phase of the feedback signal until the phase error between the phase of the input reference signal and the phase of the output signal is fixed and unchanged, so that the purpose of generating an output signal synchronous with the phase of the input reference signal according to the input reference signal is achieved, and the phase locking effect is achieved. The feedback signal may be the same as the output signal, or may be a signal formed by performing frequency division processing (increasing a frequency point) on the output signal.

In fact, the phase jitter compensation method in the embodiment of the present application starts after the digital phase-locked loop locks the phase error between the feedback signal and the input reference signal, at this time, the phase error between the feedback signal and the input reference signal is fixed and constant, and the phase error may be 0 or may be a constant.

The phase error signal is a digital signal formed by the difference between the phase of the input reference signal and the phase of the feedback signal in the digital phase-locked loop. The phase error signal may refer to a digital signal in which the phase error varies with time. The duty cycle mismatch information is used to represent a phase jitter error caused by the duty cycle mismatch.

In fact, under the ideal condition without phase jitter, the input reference signals of the digital phase-locked loop at different periods are the same, and the feedback signals of the digital phase-locked loop at different periods are the same. Because the phase jitter does not exist, the input reference signals of the digital phase-locked loop in different periods are different, the feedback signals of the digital phase-locked loop in different periods are also different, and correspondingly, the difference value between the input reference signal phase and the feedback signal phase of the digital phase-locked loop in different periods is different. It follows that it is possible to detect whether the duty cycle is mismatched by analyzing whether the phase error between the input reference signal phase and the feedback signal phase is the same in adjacent cycles. Therefore, the influence brought by the phase jitter can be represented by the difference between the phase of the input reference signal and the phase of the feedback signal of the digital phase-locked loop in different periods. Therefore, the difference between the phase error signal of the digital phase-locked loop in the current period and the phase error signal of the adjacent previous period can be used for representing the phase jitter error caused by duty ratio mismatch.

In a specific example, as shown in fig. 1, the phase error signal of the current cycle may refer to information about a phase error correlation between a true frequency-doubled input reference signal phase and a feedback signal phase in the current cycle. The phase error signal of the adjacent previous cycle may refer to information related to a phase error between a phase of a true frequency-doubled input reference signal and a phase of a feedback signal in the previous cycle adjacent to the current cycle. The duty cycle mismatch information is used to determine whether the duty cycles in adjacent periods are the same to determine whether the duty cycles of the input reference signal are mismatched. The duty ratio mismatch information may refer to a difference between duty ratios of adjacent periods, and may be represented by a difference between phase errors of two adjacent periods, that is, the difference between the phase errors of two adjacent periods is used to detect whether the duty ratios are mismatched.

In an exemplary embodiment, the digital phase-locked loop is a double-frequency digital phase-locked loop, the phase error signal includes a digital signal formed by a difference between a phase of a double-frequency input reference signal and a phase of a feedback signal in the double-frequency digital phase-locked loop when the phase is locked, and the double-frequency input reference signal is a signal formed by a double-frequency process on an input reference signal of the double-frequency digital phase-locked loop.

Generally, the phase jitter compensation method of the embodiment of the present application is mainly applied to a digital phase-locked loop and a frequency-doubled digital phase-locked loop. In addition, a plurality of double-frequency digital phase-locked loops can be superposed to form a 2 n-th-power (n is an integer greater than or equal to 2) double-frequency digital phase-locked loop, and correspondingly, the phase jitter compensation method can be respectively applied to each double-frequency digital phase-locked loop, so that each double-frequency digital phase-locked loop can solve the phase jitter problem caused by duty ratio mismatch, and the phase jitter problem can be solved by the whole system.

By applying the phase jitter compensation method in the double-frequency digital phase-locked loop and based on the phase error signal between the double-frequency input reference signal and the feedback signal after frequency multiplication processing, determining the phase compensation information and compensating the phase error signal, the phase jitter error caused by duty ratio mismatch in the double-frequency input reference signal in the double-frequency digital phase-locked loop can be effectively reduced.

The phase error sent by the phase comparison module in the Digital phase-locked loop is a value quantized by a Time-to-Digital Converter (TDC), so that the input reference signal and the feedback signal are both Digital signals, and accordingly, the phase error signal formed by the phase error between the input reference signal and the feedback signal changing with Time is actually a Digital signal.

It should be noted that the periods involved in the phase jitter compensation method disclosed in the embodiment of the present application are all clock periods of the feedback signal.

And S120, generating current phase compensation information according to the duty ratio mismatch information.

In fact, the phase jitter compensation method is a compensation method based on a negative feedback loop, and specifically, the phase compensation is adjusted in each period until the reduction of the phase error caused by the mismatch of the duty ratio in the loop converges to a stable value, so that the phase error signal can be tracked in real time, the matched compensation value can be determined, the phase error signal can be responded in time to correspondingly adjust the compensation value, and the stability of the compensation system is improved. The duty ratio mismatch information is used for determining a phase compensation value of the current period, and the phase compensation value is continuously adjusted according to the phase compensation condition of the historical period to generate the phase compensation value of the current period. The current phase compensation information is used to compensate the phase error signal of the current cycle. The current phase compensation information may refer to a phase compensation value of the current cycle.

It will be appreciated that there is a desired phase compensation value and that the phase error in the case of duty cycle mismatch can be compensated such that the compensated phase error is (or very close to) the phase error between the ideal input reference signal phase and the feedback signal phase. The phase error under the condition of duty ratio mismatch actually changes periodically along with time, and the corresponding expected phase compensation value also changes periodically along with time. The phase error signal, thus formed as a function of time for the phase error, and the ideal phase compensation signal, formed as a function of time for the desired phase compensation value, have amplitudes that represent the desired phase compensation value. Therefore, the phase compensation is not completed in one step, but compensation is performed in each period, so that the phase error between the phase of the real input reference signal and the phase of the feedback signal gradually approaches the phase error between the phase of the ideal input reference signal and the phase of the feedback signal, and therefore, the ideal input reference signal gradually approaches the real input reference signal, and the compensation effect of the input reference signal is finally achieved. The duty cycle mismatch information is used to adjust the phase compensation information to be continuously closer to the desired phase compensation value.

In an exemplary embodiment, the generating current phase compensation information according to the duty cycle mismatch information includes: carrying out attenuation processing on data in the duty ratio mismatch information; calculating an accumulation result of the attenuated data and the data in the accumulated phase compensation information, and determining the accumulation result as the current phase compensation information; and taking the current phase compensation information as new accumulated phase compensation information.

The attenuation process is used to reduce the size of the data, for example, by an order of magnitude or by a number of bits. Specifically, the method can be completed by right shift of the register (right shift is s bits, the numerical value of the original data is attenuated by 2^ s times) or multiplication (multiplication with lambda, 0< lambda < 1). The attenuation processing is actually used for reducing the adjustment value of the phase compensation value, so that the attenuated data is accumulated to accumulated phase compensation information, the phase compensation value can be finely adjusted, the situation that the phase compensation value is adjusted in a large range and deviates from an expected phase compensation value is avoided, the phase compensation value is accurately adjusted, and the stability of phase jitter compensation is improved.

The accumulated phase compensation information is used to accumulate the phase compensation values for each compensation to continuously approach the desired phase compensation value. The accumulated phase compensation information may be a phase compensation value accumulated at a previous time. The value in the duty mismatch information is accumulated in the data in the accumulated phase compensation information, and may be adjusted by the previous phase compensation value. The accumulated result may be a phase compensation value that is continuously adjusted since the phase jitter compensation method has been operated. The current phase compensation information may refer to a phase compensation value accumulated for the current period.

Illustratively, the initial value of the accumulated phase compensation information is 0, i.e., the accumulated phase compensation information includes a value of 0 at the time of starting the operation. The current phase compensation information is used to determine a phase value for duty cycle mismatch compensation of the current period phase error. The current phase compensation information may include a phase value to be compensated into the current period phase error. While the current phase compensation information is used as the new accumulated phase compensation information.

The embodiment of the application attenuates the information of the mismatch of the duty ratio, improves the stability of the phase jitter compensation system, and continuously carries out accurate accumulation adjustment on the phase compensation value, so that the phase compensation value approaches to an expected phase compensation value, the phase jitter caused by the mismatch of the duty ratio is finally compensated, and the stability and the accuracy of the phase jitter compensation are improved.

And S130, correcting the phase error signal in the current period by using the current phase compensation information, and sending the corrected phase error signal to the digital phase-locked loop to instruct the digital phase-locked loop to perform phase tracking again according to the corrected phase error signal.

The current phase compensation information includes a compensation value that is compensated to the phase error signal of the current cycle, illustratively, by adding or subtracting the compensation value from the phase error signal. And the corrected phase error signal is used as a phase error for eliminating the duty ratio mismatch error and is sent to the digital phase-locked loop so as to instruct the digital phase-locked loop to continue to carry out the phase tracking process according to the corrected phase error signal. Therefore, in the phase tracking process of the digital phase-locked loop, the error of duty ratio mismatch is eliminated, and the output feedback signal is ensured to be the feedback signal corresponding to the ideal input reference signal.

In an exemplary embodiment, before performing attenuation processing on the data in the duty cycle mismatch information, the method further includes:

sampling the input reference signal by adopting the falling edge of the feedback signal, and determining the parity information of the current period according to the level of the input reference signal point obtained by sampling, wherein the level of the input reference signal point in the odd period is low level, and the level of the input reference signal point in the even period is high level; correcting the sign of the data in the duty ratio mismatch information according to the parity information of the current period and the corresponding relation between the preset parity information and the sign; the attenuating the data in the duty cycle mismatch information includes: carrying out attenuation processing on the data in the corrected duty ratio mismatch information; the calculating an accumulation result of the attenuated data and the data in the accumulated phase compensation information to determine the current phase compensation information includes: calculating an accumulation result of the attenuated data and the data in the accumulated phase compensation information; and correcting the sign of the accumulation result according to the parity information of the current period and the preset corresponding relation between the parity information and the sign, and determining the corrected accumulation result as the current phase compensation information.

At this time, the digital phase-locked loop is a double-frequency digital phase-locked loop. The parity information of the current cycle is used to determine which direction adjustment is performed on the phase compensation value and which direction compensation is performed on the phase difference information of the current cycle. The parity information of the current period is used for correcting the sign of the data in the duty ratio mismatch information, actually, the value of the data in the duty ratio mismatch information is an absolute value, and the parity information of the current period is used for adding the sign to the data in the duty ratio mismatch information. And, the parity information of the current period is used to add a symbol to the accumulated data. Since the desired phase compensation value may be a positive number or a negative number, the current phase compensation value matching the desired phase compensation value is converged by adding a sign to the data in the current phase compensation information.

In the double-frequency digital phase-locked loop, the period duration of the input reference signal before frequency multiplication is twice as long as the period duration of the input reference signal after frequency multiplication. Specifically, as shown in fig. 1, t1 and t0 form one period of the input reference signal, while t1 forms a first period of the true frequency doubled input reference signal, and t0 forms a second period of the true frequency doubled input reference signal. When the duty ratio mismatch phenomenon does not exist, each period of the real frequency doubling input reference signal is the same, the first period and the second period of the real frequency doubling input reference signal are different due to the fact that the duty ratio mismatch phenomenon exists in the real frequency doubling input reference signal, and the third period and the fourth period repeat the first period and the second period. Therefore, the aforementioned first period and second period can be distinguished using an odd-numbered period and an even-numbered period. As can be seen from fig. 1, the level of the input reference signal at t1 is high, and the level at t0 is low, so that the parity of the frequency-doubled input reference signal period can be determined by the level state of the input reference signal. For example, the input reference signal may be sampled according to a period of the feedback signal, for example, the input reference signal may be sampled by using a rising edge or a falling edge of the electrical feedback signal. Among the sampled signal points, the level of the input reference signal point in the odd cycle is low level, and the level of the input reference signal point in the even cycle is high level.

In the phase compensation process, the phase compensation value may be greater than the desired phase compensation value or may be smaller than the desired phase compensation value, so that when the phase compensation value is adjusted to approach the desired phase compensation value, the adjustment needs to be increased and decreased, and the desired phase compensation value is continuously approached. It may be configured such that the phase compensation value is increased at the odd cycle and decreased at the even cycle, or the phase compensation value is increased at the even cycle and decreased at the odd cycle, and so on. The increase and the decrease can be reflected in the positive and negative of the numerical value, and the positive number is accumulated to the data in the accumulated phase compensation information, which is equivalent to increasing the numerical value of the data in the accumulated phase compensation information; accumulating negative numbers into the data in the accumulated phase compensation information is equivalent to reducing the value of the data in the accumulated phase compensation information.

In fact, the phase jitter compensation method cannot accurately obtain the expected phase compensation value, and only can obtain the phase compensation value through the known phase error signal, and continuously accumulate the phase compensation value until the expected phase compensation value is converged, and the phase compensation value can be accurately and continuously adjusted by increasing or decreasing the phase compensation value according to the odd-even number of the period, so that the phase compensation value aiming at the phase jitter caused by the mismatch of the duty ratio can be accurately converged.

According to the embodiment of the application, the parity information of the real frequency doubling input reference signal period is detected by detecting the parity of the period, and the sign is added to the data in the duty ratio mismatch information and the data in the accumulation result according to the parity information, so that the purpose of increasing adjustment and reducing adjustment phase compensation values is achieved, the expected phase compensation values are continuously approached until the expected phase compensation values are converged, the phase jitter caused by the duty ratio mismatch is finally compensated, and the stability and the accuracy of phase jitter compensation are improved.

In an exemplary implementation manner, fig. 3 is a flowchart of a phase jitter compensation method provided in an embodiment of the present application. The method comprises the following steps:

s210, obtaining a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determining duty ratio mismatch information according to the phase error signal of the current period and the phase error signal of the adjacent previous period, wherein the phase error signal comprises a digital signal formed by a difference value between an input reference signal phase and a feedback signal phase, the input reference signal is an input reference signal of the digital phase-locked loop, and the feedback signal is a feedback signal transmitted in a feedback loop of the digital phase-locked loop when the phase is locked.

And S220, generating current phase compensation information according to the duty ratio mismatch information.

And S230, compensating the preset frequency division control information by adopting the current phase compensation information to generate the corrected frequency division control information.

The Frequency division Control information may be a Frequency Control Word (FCW).

And S240, quantizing the corrected frequency division control information to obtain quantized frequency division control information, wherein the quantized frequency division control information is used for indicating the digital phase-locked loop to generate a feedback signal according to the quantized frequency division control information.

The modified frequency division control information may refer to frequency division control information compensated by the current phase compensation information, that is, a phase jitter error introduced by duty ratio mismatch is reduced in the modified frequency division control information. The quantized frequency division control information may be frequency division control information formed by quantizing the modified frequency division control information.

Specifically, in a frequency-doubled digital phase-locked loop, for example, a double-frequency digital phase-locked loop, a Delta-Sigma Modulator (SDM) is used to quantize frequency control information to generate a digital control signal, so as to instruct a frequency divider to divide the frequency of an output signal of the digital phase-locked loop to form a feedback signal. However, SDM quantization may lose part of the continuous data, which may generate quantization errors, and therefore, the quantization errors of SDM may be calculated and compensated for, thereby reducing the quantization errors in the digital phase-locked loop.

The delta-sigma modulator is used for carrying out quantization processing on the frequency division control information. Illustratively, the sigma-delta modulator is an SDM of order n, and the output quantized frequency division control information includes [ -2 [ ]^n-1+1，2^n-1]An integer within the range. The delta-sigma modulator is used for sending quantized frequency division control information to a frequency divider in the digital phase-locked loop, and the quantized frequency division control information is used for indicating the frequency divider to divide the frequency of an output signal of the digital phase-locked loop to form a feedback signal. The quantized frequency division control information comprises the current phase compensation information, and then the frequency divider divides the frequency of the output signal according to the control signal for compensating the phase jitter error introduced by the mismatch of the duty ratio, so that the frequency division can be performed by adapting to the current compensated output signal, and the frequency division precision is improved.

And S250, determining quantization compensation information according to the corrected frequency division control information and the quantized frequency division control information.

Due to the existence of quantization errors, quantization errors exist in the quantized frequency division control information. It can be seen that whether or not quantization error is introduced can be determined by analyzing difference information between the frequency division control information before and after quantization. Thus, the corrected frequency division control information and the difference between the quantized frequency division control information can determine a compensation value of the quantization error.

The quantization compensation information is used to perform duty mismatch compensation and quantization error compensation on the phase error signal. The quantization compensation information comprises two types of compensation information, wherein one type of compensation information is compensation information of phase jitter error introduced by duty ratio mismatch of an input reference signal, and the other type of compensation information is compensation information of phase error introduced by quantization operation of a delta-sigma modulator.

And S260, correcting the phase error signal of the current period by adopting the quantization compensation information.

The duty ratio mismatch error and the quantization error can be compensated in the phase error signal by using the quantization compensation information for correction.

And S270, sending the corrected phase error signal to the digital phase-locked loop to instruct the digital phase-locked loop to perform phase tracking again according to the corrected phase error signal.

The embodiment of the application adds the current phase compensation information into the input frequency division control information of the triangular integral modulator, obtains the frequency division control information of the triangular integral modulator before and after quantization, and determines the quantization compensation information of the triangular integral modulator, and simultaneously, the current phase compensation information is introduced into the quantization compensation information because the frequency division control information before and after quantization comprises the current phase compensation information, so that the phase error signal is compensated according to the quantization compensation information, errors introduced by duty ratio mismatch and quantization errors introduced by the triangular integral modulator are compensated, the phase locking precision of a digital phase locking loop is improved, and the system error of the digital phase locking loop is reduced.

In one exemplary embodiment, the frequency division control information is a frequency control word; the determining quantization compensation information according to the modified frequency division control information and the quantized frequency division control information includes: acquiring the corrected frequency control word and the quantized frequency control word, and calculating quantization error information; accumulating the accumulated quantization compensation information according to the quantization error information to generate current quantization compensation information; taking the current quantization compensation information as new accumulated quantization compensation information; acquiring compensation gain information according to the current quantization compensation information and the phase correction feedback signal; and calculating the product of the data in the compensation gain information and the data in the current quantization compensation information as quantization compensation information.

The quantization error information may refer to a difference between data before and after quantization processing by the delta-sigma modulator, and may be represented by a difference between the modified frequency control word and the quantized frequency control word.

In practice, there is a desired phase compensation value that can compensate for the quantization error of the SDM so that the compensated quantized data is (or very close to) the pre-quantized data. Similar to the compensation process of duty ratio mismatch, the calibration compensation module cannot accurately obtain the expected quantization compensation value, and can only obtain the quantization compensation value through the known quantization error information, and continuously accumulates until the expected quantization compensation value is converged. The accumulated quantized compensation information is used to accumulate quantized compensation values for respective compensations to continuously approach desired quantized compensation values. The accumulated quantization compensation information may be a previously accumulated quantization compensation value. Illustratively, the initial value of the accumulated quantized compensation information is 0, that is, when the phase jitter compensation method starts to work, the accumulated quantized compensation information includes a value of 0.

The compensation gain information is used to increase the magnitude of the current quantized compensation information data. Because the current quantization compensation information and the phase error signal have a difference of an order of magnitude, for example, the quantization compensation information is extremely smaller than the phase error signal, and the quantization compensation information has a poor compensation effect on the phase error signal, the current quantization compensation information can be gained, so that the order of magnitude of the current quantization compensation information is the same as the order of magnitude of the phase error signal, and the phase error signal can be accurately compensated.

Also, the quantization compensation process is a negative feedback loop. The phase correction feedback signal is adjacent to the phase error signal after the previous correction. According to the phase correction feedback signal and the current quantization compensation information, the compensation value of the current quantization error can be continuously adjusted according to the previous quantization error compensation condition so as to realize continuous calibration of the compensation value, and the continuously calibrated value is used as compensation gain information, so that the correctness of the compensation value can be improved.

And taking the current quantization compensation information subjected to gain as quantization compensation information, and compensating the phase error signal of the current period to realize duty ratio mismatch compensation and SDM quantization compensation on the phase error at the same time.

According to the embodiment of the application, the quantization error can be accurately calculated by calculating the quantization residual error, calculating the calibration source, calculating the compensation gain, correcting the quantization error and the like, the quantization compensation value is determined according to the quantization error, and meanwhile, the quantization compensation value is continuously subjected to accurate accumulation adjustment so that the quantization compensation value approaches to the expected quantization compensation value, the quantization error caused by SDM quantization is finally compensated, and the stability and the accuracy of quantization compensation are improved.

In an exemplary embodiment, the obtaining compensation gain information according to the current quantization compensation information and a phase correction feedback signal includes: and determining compensation gain information according to the current quantization compensation information and the phase error signal of the current period by adopting a minimum root mean square algorithm.

The Least Mean Square (LMS) algorithm is an algorithm that minimizes the Mean Square error by iterative computation as a function of the cost.

According to the embodiment of the application, the difference between the current quantization compensation information and the magnitude of the phase error signal of the current period can be accurately determined through the minimum root mean square algorithm, the gain information is determined according to the difference, and the numerical value of the current quantization compensation information is increased, so that the phase error signal can be accurately compensated.

Fig. 4 is a schematic structural diagram of a phase jitter compensation module according to an embodiment of the present disclosure. The phase jitter compensation module is suitable for the condition of calibrating the duty ratio on the premise of not adding an additional analog circuit. The phase jitter compensation module is configured in the digital phase-locked loop, and the embodiment of the present application does not limit the type of the digital phase-locked loop.

As shown in fig. 4, the phase jitter compensation module 100 provided in the embodiment of the present application includes: the calibration device comprises a duty ratio mismatch detection module 110, an error accumulation module 120 and a calibration compensation module 130, wherein the duty ratio mismatch detection module 110 is respectively connected with a phase comparison module and the error accumulation module 120 in a digital phase-locked loop, the error accumulation module 120 is connected with the calibration compensation module 130, and the calibration compensation module 130 is respectively connected with a phase tracking module and a phase comparison module in the digital phase-locked loop;

a duty mismatch detection module 110, configured to obtain a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determine duty mismatch information according to the phase error signal of the current period and the phase error signal of the adjacent previous period, where the phase error signal includes a digital signal formed by a difference between an input reference signal phase and a feedback signal phase, the input reference signal is an input reference signal of the digital phase-locked loop, and the feedback signal is a feedback signal transmitted in a feedback loop of the digital phase-locked loop during phase locking; an error accumulation module 120, configured to generate current phase compensation information according to the duty mismatch information; and the calibration compensation module 130 is configured to modify the phase error signal in the current period by using the current phase compensation information, and send the modified phase error signal to the digital phase-locked loop, so as to instruct the digital phase-locked loop to perform phase tracking again according to the modified phase error signal.

The phase jitter compensation module 100 starts to operate after the digital phase-locked loop locks the phase error between the feedback signal and the input reference signal, and at this time, the phase error between the feedback signal and the input reference signal is fixed and constant, and the phase error may be 0 or may be a constant. The compensation process of the phase jitter compensation module 100 is a negative feedback loop, and the compensation process of the phase jitter compensation module 100 continuously accumulates the compensation value, so that the accumulated compensation value gradually approaches the desired phase compensation value. The compensation process of the phase jitter compensation module 100 is configured as a negative feedback loop, so that the phase error signal can be tracked in real time, the matched compensation value can be determined, the phase error signal can be responded in time to correspondingly adjust the compensation value, and the stability of the compensation system is improved.

The phase error signal obtained by the duty cycle mismatch detection module 110 is sent by the phase comparison module. The phase error sent by the phase comparison module in the Digital phase-locked loop is a value quantized by a Time Digital Converter (TDC), so that a phase error signal formed by the phase error changing with Time is actually a Digital signal. Thus, the phase error signal processed by the phase jitter compensation module 100 is a digital signal. Accordingly, the duty mismatch detection module 110 obtains the duty mismatch information based on the phase error signal output by the time-to-digital converter in the phase comparison module of the digital phase-locked loop.

It should be noted that the periods involved in the phase jitter compensation module 100 disclosed in the embodiment of the present application are all clock periods of the feedback signal, and the clock driving signal of each module in the phase jitter compensation module 100 is the feedback signal.

The error accumulation module 120 is used to accumulate the phase compensation value step by step and determine the phase compensation value of the current cycle, so that the phase compensation value of the current cycle is continuously close to the expected phase compensation value.

The calibration compensation module 130 is used to compensate the current phase compensation information into the phase error signal, for example, to add or subtract a compensation value included in the current phase compensation information to the phase error signal. The corrected phase error signal is used as a phase error for eliminating the duty ratio mismatch error and is sent to the phase locking module so as to instruct the phase locking module to continue to perform the phase tracking process according to the corrected phase error signal. Therefore, in the phase tracking process of the digital phase-locked loop, the error of duty ratio mismatch is eliminated, and the output feedback signal is ensured to be the feedback signal corresponding to the ideal input reference signal.

The embodiment of the application configures a phase jitter compensation module in a digital phase-locked loop, obtains a phase error signal in the digital phase-locked loop through a duty ratio mismatch detection module, wherein the phase error signal is a digital signal, compares phase errors of adjacent periods to obtain duty ratio mismatch information, determines a compensation value through an error accumulation module based on the duty ratio mismatch information, continuously accumulates in accumulated phase compensation information of a plurality of periods to generate current phase compensation information, compensates the current phase compensation information into the phase error signal of the current period through a calibration compensation module, sends a corrected phase error signal to a phase tracking module in the digital phase-locked loop to generate a feedback signal matched with the corrected phase error signal, realizes compensation of phase jitter caused by duty ratio mismatch in the feedback signal, and solves the problems of low calibration precision, large circuit area and the like caused by realizing duty ratio calibration in an analog circuit in the prior art, the calibration precision of the analog circuit calibration duty ratio can be broken through, the calibration precision is improved, the calibration reliability is effectively improved, the calibration consistency is ensured, and the area of the calibration circuit is reduced.

In an exemplary embodiment, the digital phase-locked loop is a double frequency digital phase-locked loop, the phase error signal includes a difference between a phase of a double frequency input reference signal in the double frequency digital phase-locked loop and a phase of the feedback signal when the phase is locked, and the double frequency input reference signal is a signal formed by a double frequency process of an input reference signal of the double frequency digital phase-locked loop.

Generally, the phase jitter compensation module according to the embodiment of the present application is mainly applied to a digital phase-locked loop and a frequency-doubled digital phase-locked loop. In addition, a plurality of double-frequency digital phase-locked loops can be superposed to form a 2 n-th power (n is an integer greater than or equal to 2) double-frequency digital phase-locked loop, and correspondingly, the phase jitter compensation module can be respectively configured in each double-frequency digital phase-locked loop, so that each double-frequency digital phase-locked loop can solve the phase jitter problem caused by duty ratio mismatch, and the phase jitter problem can be solved by the whole system.

In an exemplary embodiment, the phase jitter compensation module further comprises: a control module; the control module is used for respectively controlling whether the duty ratio mismatch detection module, the error accumulation module and the calibration compensation module work or not.

The control module is used for controlling whether each module in the phase jitter compensation module works or not.

In fact, the phase jitter compensation module is a module that works independently from other modules in the digital phase-locked loop, and can be controlled to work and/or stop working manually or automatically. Illustratively, the phase jitter error is extremely small or does not exist, the operation of the phase jitter module can be stopped, and the power consumption of the digital phase-locked loop is reduced.

When the phase of the digital phase-locked loop is not locked, the feedback signal of the digital phase-locked loop is unstable, and the correspondingly obtained phase error is inaccurate, so that the phase compensation value determined according to the inaccurate phase error is greatly deviated from the expected phase compensation value, and the difficulty of phase compensation is increased. Therefore, whether the control is automatic or manual, the phase jitter compensation module needs to start to work after the phase locking of the digital phase-locked loop, that is, the phase jitter compensation module only starts to work after the output signal output by the digital phase-locked loop is stably synchronized with the input reference signal.

The phase jitter compensation module can be independently controlled by controlling whether the phase jitter compensation module works, whether the phase jitter compensation is started or not can be selected according to needs, the flexibility of the phase jitter compensation is improved, and the power consumption of the digital phase-locked loop is reduced.

In an exemplary implementation manner, fig. 5 is a schematic structural diagram of a phase jitter compensation module according to an embodiment of the present application. In this embodiment, the error accumulation module includes: an attenuation module and an accumulation module. Accordingly, as shown in fig. 5, the error accumulation module 120 of the present embodiment includes: the calibration compensation module comprises an attenuation module 121 and an accumulation module 122, wherein the attenuation module 121 is respectively connected with the accumulation module 122 and the duty ratio mismatch detection module 110, and the accumulation module 122 is connected with the calibration compensation module 130; the attenuation module 121 is configured to perform attenuation processing on data in the duty mismatch information; an accumulation module 122, configured to calculate an accumulation result of the attenuated data and data in the accumulated phase compensation information, and determine the result as current phase compensation information; and taking the current phase compensation information as new accumulated phase compensation information.

According to the phase compensation method and device, the attenuation module and the accumulation module are configured, accurate accumulation adjustment is continuously carried out on the phase compensation value, so that the phase compensation value approaches to an expected phase compensation value, phase jitter caused by duty ratio mismatch is finally compensated, and stability and accuracy of phase jitter compensation are improved.

In an exemplary implementation manner, fig. 6 is a schematic structural diagram of a phase jitter compensation module according to an embodiment of the present application. In this embodiment, the error accumulation module includes: an odd-even cycle detection module; the attenuation module includes a first direction modification module and an attenuator, and the accumulation module includes an accumulator and a second direction modification module. In the embodiment of the application, the digital phase-locked loop is a double-frequency digital phase-locked loop, and the input reference signal is a signal formed by performing frequency doubling processing on an external input reference signal.

Accordingly, as shown in fig. 6, the error accumulation module 120 of the present embodiment includes: the odd-even period detection module 123, the attenuation module 121 includes a first direction modification module 124 and an attenuator 125, the accumulation module 122 includes an accumulator 126 and a second direction modification module 127, wherein the odd-even period detection module 123 is respectively connected with the first direction modification module 124 and the second direction modification module 127, and the first direction modification module 124, the attenuator 125, the accumulator 126 and the second direction modification module 127 are connected in series;

the parity cycle detection module 123 is configured to sample the input reference signal by using a falling edge of the feedback signal, and determine parity information of a current cycle according to a level of an input reference signal point obtained by sampling, where a level of the input reference signal point in an odd cycle is a low level, and a level of the input reference signal point in an even cycle is a high level; a first direction correction module 124, configured to correct a symbol of data in the duty cycle mismatch information according to the parity information of the current cycle and a preset correspondence between the parity information and a positive or negative symbol; an attenuator 125, configured to perform attenuation processing on data in the corrected duty mismatch information; an accumulator 126 for calculating an accumulation result of the attenuated data and the data in the accumulated phase compensation information; and a second direction correcting module 127, configured to correct a symbol of the accumulation result according to the parity information of the current period and a preset correspondence between the parity information and a positive or negative sign, and determine the corrected accumulation result as current phase compensation information.

The parity cycle detection module 123 is configured to detect parity information of a current cycle. The parity information of the current period is used to determine which direction to adjust the phase compensation value and which direction to compensate the phase difference information of the current period.

The first direction correcting module 124 is configured to correct a symbol of the data in the duty mismatch information, where in fact, a value of the data in the duty mismatch information is an absolute value, and the first direction correcting module 124 is configured to add the symbol to the data in the duty mismatch information.

And an attenuator 125 for reducing the value of the data in the modified duty mismatch information.

An accumulator 126 for calculating the accumulated result of the attenuated data and the data in the accumulated phase compensation information.

And a second direction correcting module 127, configured to correct a symbol of the accumulation result according to the parity information of the current period and a preset correspondence between the parity information and a positive or negative sign, and determine the corrected accumulation result as current phase compensation information.

In fact, the phase jitter compensation module cannot accurately obtain the desired phase compensation value, and can only obtain the phase compensation value through the known phase error signal, and accumulate the phase compensation value continuously until the desired phase compensation value is converged, and the phase compensation value can be accurately and continuously adjusted by increasing or decreasing the phase compensation value through the first direction correction module 124 and the second direction correction module 127, so that the phase compensation value aiming at the phase jitter caused by duty ratio mismatch is accurately converged.

In a specific example, the digital pll is a double-frequency digital pll, as shown in fig. 6, the phase jitter compensation module 100 includes: a duty cycle mismatch detection module 110, an error accumulation module 120, a calibration compensation module 130, and a control module 140, wherein the error accumulation module 120 includes: an attenuation module 121, an accumulation module 122, and a parity cycle detection module 123, the attenuation module 121 including a first direction modification module 124 and an attenuator 125, the accumulation module 122 including an accumulator 126 and a second direction modification module 127.

As shown in fig. 7, the parity-cycle detecting module 123 includes a sampler based on a D-type Flip-Flop (DFF) or other types, wherein the sampling clock is a feedback signal of a digital phase-locked loop, and the input Data is an input reference signal before frequency multiplication. The sampler samples the input reference signal before frequency multiplication by using the falling edge of the feedback signal, and C1 output by the parity cycle detection module 123 is determined as the parity information of the current cycle. A sampler output value of C1 of 1 indicates that the current true doubled input reference signal is in an even cycle, and a block output value of C1 of 0 indicates that the current true doubled input reference signal is in an odd cycle.

As shown in fig. 8, the duty cycle mismatch detection module 110 includes a delay unit and a subtractor. The delay unit is used for delaying the phase error signal by a period of a feedback signal to form a signal D1, inputting the D1 and the phase error signal into the subtracter for processing to obtain a difference D2 between the phase error signal and the adjacent phase error signal in the previous period, and determining the difference as duty ratio mismatch information.

As shown in fig. 9, the first direction modification module 124 includes an inverting unit and a multiplexer. The inverting unit is used for inverting the data D2, and the multiplexer is used for selecting to output the original data or the inverted data. The first direction correcting module 124 controls whether to invert D2 according to C1 output from the parity cycle detecting module 123. When the true double frequency input reference signal is in an odd cycle, i.e. C1 is 0, then D2 is not negated, D4 equals D2; when the true double frequency input reference signal is at an even cycle, i.e., C1 is 1, then D2 is negated, and D4 equals D3, i.e., -D2.

As shown in fig. 10, wherein the attenuator 125 may be a proportional attenuator, the attenuation of D4 is obtained as D5. Specifically, the attenuation operation can be performed by multiplication, i.e., D4 is multiplied by a configured λ value greater than and less than 1 to obtain D5, e.g., D5 ═ D4 ^ λ, but right shifting through registers in digital circuits is the most effective method for attenuating data, assuming that the configured right shift is s, then D5 ═ D4/2^ s. The accumulator 126 continues to accumulate D5 as clocked by the feedback signal, and after calibration is complete, D6 will converge to a stable value.

As shown in fig. 11, the second direction correcting module 127 includes an inverting unit and a multiplexer. The inverting unit is used for inverting the data D6, and the multiplexer is used for selecting to output the original data or the inverted data. The second direction correcting module 127 controls whether to invert D6 according to C1 output from the parity cycle detecting module 123. When the true double frequency input reference signal is in an odd cycle, i.e. C1 is 0, then D6 is not negated, D8 equals D6; when the true double frequency input reference signal is at an even cycle, i.e., C1 is 1, then D8 is negated, and D8 equals D7, i.e., -D6.

According to the embodiment of the application, the odd-even period detection module is configured to detect the odd-even information of the real frequency doubling input reference signal period, and the sign is added to the data in the duty ratio mismatch information and the data in the accumulation result according to the odd-even information, so that the adjustment is increased, the phase compensation value is reduced, the expected phase compensation value is continuously approached until the expected phase compensation value is converged, the phase jitter caused by the duty ratio mismatch is finally compensated, and the stability and the accuracy of the phase jitter compensation are improved.

In an exemplary implementation manner, fig. 12 is a schematic structural diagram of a phase jitter compensation module according to an embodiment of the present application. In this embodiment, the calibration compensation module includes: the device comprises a frequency division control information compensation module, a delta-sigma modulator and a quantization error compensation module. The digital phase-locked loop is a double-frequency digital phase-locked loop, and the input reference signal is a signal formed by performing frequency doubling processing on an external input reference signal.

Accordingly, as shown in fig. 12, the calibration compensation module 130 of the present embodiment includes: a frequency division control information compensation module 131, a delta-sigma modulator 132 and a quantization error compensation module 133, wherein the frequency division control information compensation module 131 is respectively connected with the error accumulation module 120, the delta-sigma modulator 132 is respectively connected with the quantization error compensation module 133 and the phase tracking module, and the quantization error compensation module 133 is respectively connected with the phase comparison module and the phase tracking module;

a frequency division control information compensation module 131, configured to compensate the preset frequency division control information by using the current phase compensation information, and generate modified frequency division control information; the delta-sigma modulator 132 is configured to perform quantization processing on the modified frequency division control information to obtain quantized frequency division control information, where the quantized frequency division control information is used to instruct the digital phase-locked loop to generate a feedback signal according to the quantized frequency division control information by frequency division; a quantization compensation module 133, configured to determine quantization compensation information according to the modified frequency division control information and the quantized frequency division control information; and correcting the phase error signal of the current period by adopting the quantization compensation information, and sending the corrected phase error signal to a phase tracking module.

The frequency division control information compensation module 131 is configured to add current phase compensation information to the frequency division control information, introduce phase jitter compensation into the frequency division control information, and reduce a phase jitter error introduced by duty mismatch in the quantized frequency division control information output by the delta-sigma modulator 132.

The Frequency division Control information may be a Frequency Control Word (FCW). The modified frequency division control information may refer to frequency division control information compensated by the current phase compensation information, that is, a phase jitter error introduced by duty ratio mismatch is reduced in the modified frequency division control information.

The delta-sigma modulator 132 is used to perform quantization processing on the frequency division control information. Illustratively, the delta-sigma modulator 132 is an n-order SDM.

The quantization compensation module 133 is configured to calculate a quantization error of the delta-sigma modulator 132, superimpose the current phase compensation information, generate quantization compensation information, and compensate the phase error signal of the current period by using the quantization compensation information.

The current phase compensation information is added to the input of the delta-sigma modulator 132, so that the current phase compensation information also exists in the quantized frequency division control information output by the delta-sigma modulator 132. Meanwhile, current phase compensation information exists in the frequency division control information before and after quantization, so that the determined quantization error has the current phase compensation information according to the frequency division control information before and after quantization, and the quantization compensation information determined aiming at the quantization error also comprises the current phase compensation information.

In an exemplary embodiment, as shown in fig. 13, the quantization compensation module 133 includes: the device comprises a quantization residual calculation module 134, a calibration source calculation module 135, a compensation gain calculation module 136 and a quantization correction module 137, wherein the quantization residual calculation module 134 is respectively connected with a frequency division control information compensation module 131 and a triangular integral modulator 132, the quantization correction module 137 is connected with a phase tracking module, the quantization residual calculation module 134, the calibration source calculation module 135, the compensation gain calculation module 136 and the quantization correction module 137 are connected in series, the calibration source calculation module 135 is connected with the quantization correction module 137, and frequency division control information is a frequency control word;

a quantization residual calculation module 134, configured to obtain the modified frequency control word and the quantized frequency control word, and calculate quantization error information of the delta-sigma modulator 132; a calibration source calculation module 135, configured to accumulate the accumulated quantization compensation information according to the quantization error information, generate current quantization compensation information, and use the current quantization compensation information as new accumulated quantization compensation information; a compensation gain calculation module 136, configured to obtain compensation gain information according to the current quantization compensation information and the phase correction feedback signal; and the quantization correction module 137 is configured to calculate a product of data in the compensation gain information and data in the current quantization compensation information, use the product as quantization compensation information, correct a phase error by using the quantization compensation information, generate a corrected phase error signal, and send the corrected phase error signal to the phase tracking module.

The quantization compensation module 133 includes a negative feedback loop, and the phase error signal after the correction output by the quantization compensation module 133 is fed back to the compensation gain calculation module 136 as a new phase correction feedback signal to calculate the compensation gain information.

According to the embodiment of the application, the quantization error can be accurately calculated by configuring the quantization residual calculation module, the calibration source calculation module, the compensation gain calculation module and the quantization correction module, the quantization compensation value is determined according to the quantization error, and meanwhile, the quantization compensation value is continuously subjected to accurate accumulation adjustment, so that the quantization compensation value approaches to an expected quantization compensation value, the quantization error caused by SDM quantization is finally compensated, and the stability and the accuracy of quantization compensation are improved.

In an exemplary embodiment, as shown in fig. 14, the compensation gain calculation module 136 includes: a minimum root mean square calculation module 138; and a minimum root mean square calculation module 138, configured to determine compensation gain information according to the current quantization compensation information and the phase error signal of the current period by using a minimum root mean square algorithm.

In a specific example, as shown in fig. 14, the digital pll is a double-frequency digital pll, and the calibration compensation module 130 includes: a frequency division control information compensation module 131, a delta-sigma modulator 132, and a quantization error compensation module 133; a quantization compensation module 133, comprising: a quantization residual calculation module 134, a calibration source calculation module 135, a compensation gain calculation module 136, and a quantization modification module 137; a compensation gain calculation module 136 comprising: a minimum root mean square calculation module 138.

The frequency division control information compensation module 131 includes an adder for adding the frequency control word to the current phase compensation information D8 to obtain D9, and for reusing D9 as the frequency control word of the digital phase-locked loop.

The delta sigma modulator 132 quantizes D9 to D10 by clocking the feedback signal.

The quantized residual calculation block 134 comprises a subtractor for calculating the difference between D9 and D10 to obtain D11, where D11 is actually the quantized residual of the delta-sigma modulator 132.

The calibration source calculation module 135 includes an accumulator, and accumulates the quantized residual D11 for a plurality of cycles to obtain the calibration source D12.

The quantization modification module 137 includes a multiplier and a subtractor, wherein the multiplier is used for calculating the product of the calibration source D12 and the calibration gain D16 as the calibration value D13. The subtracter is used for acquiring a calibration value D13 output by the multiplier, and subtracting the calibration value D13 from the phase error of the current period to determine a corrected phase error. Since the phase error of the current period is consistent with the jitter amplitude and jitter direction of the calibration value D13, the resulting corrected phase error will be a relatively stable data sequence.

The offset gain calculation module 136 includes a rms calculation module 138 that includes multipliers, accumulators, and attenuators. The multipliers, accumulators and attenuators implement the calculations based on the LMS method. The multiplier is used for multiplying the calibration source D12 and the phase error to obtain a gain error D14. The accumulator is used for accumulating the gain errors D14 of a plurality of periods to obtain D15. The attenuator is used to reduce the value of D15 by multiplication or right shift operation, and the attenuator obtains a more stable calibration gain value D16 by proper attenuation of D15.

It should be noted that the control module in the foregoing phase jitter compensation module may also control whether each module in the calibration compensation module operates. If at least one of the quantization residual calculation module 134, the calibration source calculation module 135, the compensation gain calculation module 136, the quantization correction module 137, etc. does not work, the current phase error signal directly corrects the phase error signal of the current period, so as to realize compensation of only the phase jitter error introduced by duty mismatch. Thereby, the mutual independence of duty ratio mismatch compensation and SDM quantization error compensation can be realized.

The embodiment of the present application provides a digital phase-locked loop, fig. 15 is a schematic structural diagram of the digital phase-locked loop provided by the present application, and the digital phase-locked loop 200 provided by the present application includes: a phase comparison module 210, a phase jitter compensation module 100 according to any of the embodiments of the present application, and a phase tracking module 220;

the phase comparing module 210 and the phase tracking module 220, wherein the phase comparing module 210 is configured to obtain an input reference signal and a feedback signal sent by the phase tracking module 220, perform phase comparison on the input reference signal and the feedback signal, generate a phase error signal, and send the phase error signal to the phase jitter compensating module 100; the phase jitter compensation module 100 is configured to modify the phase error signal, so as to send the modified phase error signal to the phase tracking module 220; the phase tracking module 220 is configured to generate a feedback signal according to the modified phase error signal, and send the feedback signal to the phase comparison module 210, where the feedback signal is used to instruct the phase comparison module 210 to continuously adjust the phase error signal until data in the phase error signal is constant.

The feedback signal may be the same as or different from the output signal.

When the phase jitter compensation module 100 is not in operation, the compensation value of the phase jitter compensation module 100 is 0, and the phase error signal output by the phase comparison module 210 is the same as the phase error signal after correction output by the phase jitter compensation module 100. At this time, the phase comparison module 210 and the phase tracking module 220 cooperate together to synchronize the phase of the output signal and the input reference signal, i.e. to lock the phase, and further, to achieve frequency synchronization. The input reference signal is an input signal sent to the digital phase-locked loop by an external device.

After the phase of the digital phase-locked loop is locked, the phase jitter compensation module 100 starts to work to compensate for the phase jitter error introduced by the duty cycle mismatch in the output signal and the feedback signal in the digital phase-locked loop.

Currently, a typical duty cycle calibration circuit directly adjusts the rising or falling edge of a reference clock outside a loop, and adjusts the clock duty cycle to an ideal state before sending the clock duty cycle to a phase-locked loop. Since the duty cycle of the clock is directly processed, an unreasonable design will degrade the performance of the reference clock, resulting in additive jitter. The phase dithering module in the embodiment of the application is configured in the digital phase-locked loop and compensates non-ideality generated by duty ratio mismatch.

In an exemplary embodiment, as shown in fig. 16, the phase comparison module 210 includes: the frequency multiplier 211, the phase detector 212 and the time-to-digital converter 213, wherein the frequency multiplier 211 is connected with the phase detector 212, the phase detector 212 is connected with the time-to-digital converter 213, and the phase detector 212 is connected with the phase tracking module 220; the frequency multiplier 211 is configured to perform frequency doubling on the input reference signal and send the frequency doubled reference signal to the phase detector 212; the phase discriminator 212 is configured to obtain a frequency-doubled reference signal and a feedback signal sent by the phase tracking module 220, perform phase comparison, obtain an analog signal of a current period, and send the analog signal to the time-to-digital converter 213; the time-to-digital converter 213 is configured to perform analog-to-digital conversion on the analog signal and send the generated phase error signal to the phase jitter compensation module.

In an exemplary embodiment, as shown in fig. 16, the phase tracking module 220 includes: a filter 221, an oscillator 222, and a frequency divider 223; the filter 221 is connected to the oscillator 222 and the phase jitter compensation module 100, respectively, and the filter 221 is configured to filter the corrected phase error signal and send the filtered phase error signal to the oscillator 222; the oscillator 222 is connected to the frequency divider 223, and the oscillator 222 is configured to generate an output signal according to the filtered phase error signal and send the output signal to the frequency divider 223; the frequency divider 223 is connected to the phase comparison module, and the frequency divider 223 is configured to perform frequency division processing on the output signal according to the quantized frequency division control information, generate a feedback signal, and send the feedback signal to the phase comparison module 210, where the quantized frequency division control information includes data obtained by performing quantization processing on the modified frequency division control information by using a delta-sigma modulator, and the modified frequency division control information is obtained by modifying preset frequency division control information by using current phase compensation information.

The delta-sigma modulator is disposed in the phase jitter compensation module 100. The time-to-digital converter 213 is used to convert the analog signal into a digital signal.

In a specific example, the digital phase-locked loop is enabled by frequency doubling, and the simulation sets the duty ratio mismatch value of the input reference signal to 1%, the clock frequency of the reference source input reference signal to 61.44MHz, the integer division ratio to 19, and the fractional division ratio to 0.1.

Fig. 17 shows the output jitter of the Phase Error signal (PHE, Phase Error) output by the Phase jitter compensation module and the Phase Error signal (PHE _ pre) output by the Phase comparison module when the Phase jitter compensation module stops operating. Since the calibration value D13 is 0, PHE _ pre coincides with the PHE waveform. Large fluctuations on PHE will be converted by the numerically controlled oscillator into in-band noise and spurs at the reference frequency.

Fig. 18 shows the jitter of PHE _ pre and PHE output after the module associated with SDM quantization noise calibration in the phase jitter compensation module has been operated. At this time, jitter introduced by SDM quantization is effectively suppressed. The PHE still has jitter due to reference duty cycle mismatch.

Fig. 19 shows the output jitter of PHE _ pre and PHE after the phase jitter compensation module starts to operate. Since the calibration value D13 tracks PHE _ pre from time to time, the jitter of PHE _ pre will be sufficiently suppressed and the PHE waveform is very stable. The jitter of PHE _ pre includes not only the jitter introduced by duty cycle mismatch but also the jitter caused by SDM quantization residual.

For another example, the digital phase-locked loop is enabled to be opened by frequency doubling, the duty ratio mismatch value of the input reference signal is set to be 1% in simulation, the clock frequency of the reference source input reference signal is 61.44MHz, the integer frequency division ratio is 19, and the fractional frequency division ratio is 0.

FIG. 20 shows the output jitter of PHE _ pre and PHE when the phase jitter compensation module stops working. Since the calibration value D13 is 0, PHE coincides with PHE _ pre waveform. Large fluctuations on PHE will be converted by the numerically controlled oscillator into in-band noise and spurs at the reference frequency.

Fig. 21 shows the output jitter of PHE _ pre and PHE after the phase jitter compensation module starts to operate. Since the calibration value D13 tracks PHE _ pre from time to time, the jitter of PHE _ pre will be sufficiently suppressed and the PHE waveform is very stable.

For another example, the digital phase-locked loop is enabled to be opened by frequency doubling, the duty ratio mismatch value of the input reference signal is set to be 0% in simulation, the clock frequency of the reference source input reference signal is 61.44MHz, the integer frequency division ratio is 19, and the fractional frequency division ratio is 0.1.

FIG. 22 shows the output jitter of PHE _ pre and PHE when the phase jitter compensation module stops working. Since the reference duty cycle mismatch is 0, the jitter of PHE is mainly introduced by SDM quantization residual at this time.

Fig. 23 shows the output jitter of PHE _ pre and PHE after the module associated with SDM quantization noise calibration in the phase jitter compensation module is operated and the phase jitter compensation module starts to operate. Since the calibration value D13 tracks PHE _ pre from time to time, the jitter of PHE _ pre will be sufficiently suppressed and the PHE waveform is very stable.

The embodiment of the invention can improve the calibration precision by configuring the phase jitter compensation module in the digital phase-locked loop, wherein the input and the output of the phase jitter compensation module are both digital signals, the duty ratio mismatch is calibrated in a full digital mode, the chip occupation area of the digital phase-locked loop can be reduced, meanwhile, the phase jitter compensation module tracks a phase error signal to carry out the duty ratio mismatch calibration, and the processing of the rising edge or the falling edge of an input reference signal is not required to be considered, so that the introduction of additive jitter is avoided, in addition, the duty ratio mismatch calibration in the phase jitter module and the quantization noise calibration of a triangular integral modulator of a frequency divider can work cooperatively, the phase jitter output by a digital phase discriminator is inhibited, the phase locking precision of the digital phase-locked loop is improved, and the system stability of the digital phase-locked loop is improved.

It should be noted that, in the above embodiments applied to the phase jitter compensation module and the digital phase-locked loop, the included units and modules are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be realized; in addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the application.

The above description is only exemplary embodiments of the present application, and is not intended to limit the scope of the present application.

In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.

Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages.

Any logic flow block diagrams in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read Only Memory (ROM), Random Access Memory (RAM), optical storage devices and systems (digital versatile disks, DVDs, or CD discs), etc. The computer readable medium may include a non-transitory storage medium. The data processor may be of any type suitable to the local technical environment, such as but not limited to general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), programmable logic devices (FGPAs), and processors based on a multi-core processor architecture.

The foregoing has provided by way of exemplary and non-limiting examples a detailed description of exemplary embodiments of the present application. Various modifications and adaptations to the foregoing embodiments may become apparent to those skilled in the relevant arts in view of the drawings and the following claims without departing from the scope of the invention. Accordingly, the proper scope of the application is to be determined according to the claims.

Claims

1. A phase jitter compensation method applied to a digital phase-locked loop includes:

2. The method according to claim 1, wherein the modifying the phase error signal in the current period using the current phase compensation information comprises:

compensating preset frequency division control information by adopting the current phase compensation information to generate corrected frequency division control information;

quantizing the corrected frequency division control information to obtain quantized frequency division control information, wherein the quantized frequency division control information is used for indicating the digital phase-locked loop to generate a feedback signal according to the quantized frequency division control information;

determining quantization compensation information according to the corrected frequency division control information and the quantized frequency division control information;

and correcting the phase error signal of the current period by adopting the quantization compensation information.

3. The phase jitter compensation method of claim 1, wherein the generating current phase compensation information according to the duty cycle mismatch information comprises:

carrying out attenuation processing on data in the duty ratio mismatch information;

calculating an accumulation result of the attenuated data and the data in the accumulated phase compensation information, and determining the accumulation result as the current phase compensation information;

and taking the current phase compensation information as new accumulated phase compensation information.

4. The phase jitter compensation method of claim 3, further comprising, before performing attenuation processing on the data in the duty cycle mismatch information:

sampling the input reference signal by adopting the falling edge of the feedback signal, and determining the parity information of the current period according to the level of the input reference signal point obtained by sampling, wherein the level of the input reference signal point in the odd period is low level, and the level of the input reference signal point in the even period is high level;

correcting the sign of the data in the duty ratio mismatch information according to the parity information of the current period and the corresponding relation between the preset parity information and the sign;

the attenuating the data in the duty cycle mismatch information includes:

carrying out attenuation processing on the data in the corrected duty ratio mismatch information;

the calculating an accumulation result of the attenuated data and the data in the accumulated phase compensation information to determine the current phase compensation information includes:

calculating an accumulation result of the attenuated data and the data in the accumulated phase compensation information;

and correcting the sign of the accumulation result according to the parity information of the current period and the preset corresponding relation between the parity information and the sign, and determining the corrected accumulation result as the current phase compensation information.

5. The phase jitter compensation method of claim 2, wherein the frequency division control information is a frequency control word;

the determining quantization compensation information according to the modified frequency division control information and the quantized frequency division control information includes:

acquiring the corrected frequency control word and the quantized frequency control word, and calculating quantization error information;

accumulating the accumulated quantization compensation information according to the quantization error information to generate current quantization compensation information;

taking the current quantization compensation information as new accumulated quantization compensation information;

acquiring compensation gain information according to the current quantization compensation information and the phase correction feedback signal;

and calculating the product of the data in the compensation gain information and the data in the current quantization compensation information as quantization compensation information.

6. The phase jitter compensation method of claim 5, wherein the obtaining compensation gain information according to the current quantization compensation information and the phase correction feedback signal comprises:

and determining compensation gain information according to the current quantization compensation information and the phase error signal of the current period by adopting a minimum root mean square algorithm.

7. The phase jitter compensation method of claim 1, wherein the digital phase-locked loop is a double-frequency digital phase-locked loop, the phase error signal comprises a digital signal formed by a difference between a phase of a double-frequency input reference signal and a phase of a feedback signal in the double-frequency digital phase-locked loop during phase locking, and the double-frequency input reference signal is a signal formed by a double-frequency processing of an input reference signal of the double-frequency digital phase-locked loop.

8. A phase jitter compensation module disposed in a digital phase locked loop, comprising:

9. The phase jitter compensation module of claim 8, wherein the calibration compensation module comprises: the system comprises a frequency division control information compensation module, a delta-sigma modulator and a quantization error compensation module, wherein the frequency division control information compensation module is respectively connected with the error accumulation module, the delta-sigma modulator and the quantization error compensation module, and the quantization error compensation module is connected with the phase tracking module;

the frequency division control information compensation module is used for compensating the preset frequency division control information by adopting the current phase compensation information to generate the corrected frequency division control information;

the delta-sigma modulator is configured to perform quantization processing on the corrected frequency division control information to obtain quantized frequency division control information, where the quantized frequency division control information is used to instruct the digital phase-locked loop to generate a feedback signal according to the quantized frequency division control information;

and the quantization compensation module is used for determining quantization compensation information according to the corrected frequency division control information and the quantized frequency division control information, and correcting the phase error signal of the current period by adopting the quantization compensation information.

10. The phase jitter compensation module of claim 8, further comprising: a control module;

the control module is used for respectively controlling whether the duty ratio mismatch detection module, the error accumulation module and the calibration compensation module work or not.

11. A digital phase locked loop, comprising: a phase comparison module, a phase jitter compensation module according to any of claims 8-10 and a phase tracking module;

12. The digital phase locked loop of claim 11, wherein the phase comparison module comprises: the frequency multiplier is connected with the phase discriminator, the phase discriminator is connected with the digital converter, and the phase discriminator is connected with the phase tracking module;

the frequency multiplier is used for carrying out frequency doubling processing on the input reference signal and sending the frequency doubled reference signal to the phase discriminator;

the phase discriminator is used for acquiring a frequency-doubled reference signal and a feedback signal sent by the phase tracking module, performing phase comparison, acquiring an analog signal of the current period, and sending the analog signal to the time-to-digital converter;

the time-to-digital converter is used for performing analog-to-digital conversion on the analog signal and sending the generated phase error signal to the phase jitter compensation module.

13. The digital phase locked loop of claim 12, wherein the phase tracking module comprises: a filter, an oscillator, and a frequency divider;

the filter is respectively connected with the oscillator and the phase jitter compensation module, and is used for filtering the corrected phase error signal and sending the phase error signal to the oscillator;

the oscillator is connected with the frequency divider and used for generating an output signal according to the filtered phase error signal and sending the output signal to the frequency divider;

the frequency divider is connected with the phase comparison module and used for performing frequency division processing on the output signal according to quantized frequency division control information to generate a feedback signal and sending the feedback signal to the phase comparison module, wherein the quantized frequency division control information comprises data obtained by performing quantization processing on the corrected frequency division control information by a delta-sigma modulator, and the corrected frequency division control information is obtained by correcting preset frequency division control information by adopting current phase compensation information.