CN115694476A

CN115694476A - All-digital phase-locked loop and correction method thereof

Info

Publication number: CN115694476A
Application number: CN202110869536.7A
Authority: CN
Inventors: 杨育哲
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2023-02-03

Abstract

The disclosure relates to an all-digital phase-locked loop and a calibration method thereof. An all-digital phase-locked loop (ADPLL) comprising: a Digitally Controlled Oscillator (DCO) for generating a clock signal according to a frequency control signal; a time-to-digital converter (TDC) coupled to the dco for generating a digital output signal according to a phase difference between the clock signal and a reference signal; and a normalization circuit, coupled to the time-to-digital converter, for converting the digital output signal into a clock phase value according to a gain parameter; wherein the normalization circuit selects one of the stored candidate gain parameters as the gain parameter corresponding to the digital output signal.

Description

Full digital phase-locked loop and correction method thereof

Technical Field

The present invention relates to an all-digital phase-locked loop, and more particularly, to an all-digital phase-locked loop and a calibration method thereof, such as a gain calibration method for a time-to-digital converter in the all-digital phase-locked loop.

Background

In the adpll operation, a time-to-digital converter is used to act as a phase detector to convert the phase difference between the reference signal and the output signal of the dco into a digital code, so that subsequent processing can be performed in the digital domain. However, the time-to-digital converter has some characteristics of an analog circuit, such as its resolution may vary due to process-voltage-temperature (PVT) variations and other factors. Since the resolution of the time-to-digital converter affects the settings of certain parameters in the adpll, an error in estimating the resolution of the time-to-digital converter affects the overall performance of the adpll.

Therefore, a novel architecture and related calibration method are needed to properly obtain the correct or optimal values of the parameters associated with the time-to-digital converter (e.g., the gain of the time-to-digital converter) under various process variations and temperatures.

Disclosure of Invention

An objective of the present invention is to provide an all-digital phase-locked loop (ADPLL) and a calibration method thereof, which can set parameters related to a time-to-digital converter without side effects or with less side effects, so that the time-to-digital converter has better linearity.

One embodiment of the present invention discloses an all-digital phase-locked loop (ADPLL), comprising: a Digitally Controlled Oscillator (DCO) for generating a clock signal according to a frequency control signal; a time-to-digital converter (TDC) coupled to the dco for generating a digital output signal according to a phase difference between the clock signal and a reference signal; and a normalization circuit, coupled to the time-to-digital converter, for converting the digital output signal into a clock phase value according to a gain parameter; wherein the normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit corresponding to the digital output signal as the gain parameter.

One embodiment of the present invention discloses a calibration method for an all-digital phase-locked loop (ADPLL), comprising: generating a clock signal according to a frequency control signal by using a Digital Controlled Oscillator (DCO) in the all-digital phase-locked loop; generating a digital output signal by using a time-to-digital converter (TDC) in the ADPLL according to a phase difference between the clock signal and a reference signal; converting the digital output signal into a clock phase value according to a gain parameter by using a normalization circuit in the all-digital phase-locked loop; and selecting one of the stored candidate gain parameters as the gain parameter by using the normalization circuit corresponding to the digital output signal.

The all-digital phase-locked loop and the correction method thereof provided by the embodiment of the invention can select the corresponding gain parameter according to the digital output signal and can increase the linearity of the time-to-digital converter. In addition, the calibration method of the present invention is not limited by the resolution of the time-to-digital converter, and does not add extra cost greatly. Accordingly, the present invention can solve the problems of the related art without side effects or with less side effects.

Drawings

FIG. 1 is a diagram illustrating an embodiment of estimating the resolution of a time-to-digital converter according to the present invention.

Fig. 2 is a circuit architecture of a time-to-digital converter according to an embodiment of the invention.

Fig. 3 illustrates some of the signals involved in the circuit architecture shown in fig. 2.

FIG. 4 is a diagram illustrating the normalization operation of the time-to-digital converter according to an embodiment of the present invention.

Fig. 5 is a simplified schematic diagram of an adpll according to an embodiment of the invention.

Fig. 6 is a diagram of certain signals after locking under ideal conditions, in accordance with one embodiment of the present invention.

Fig. 7 is a graph of certain signals at a time-to-digital converter gain with a-20% error, in accordance with one embodiment of the present invention.

Fig. 8 shows some signals when the time-to-digital converter gain has a +20% error, according to an embodiment of the invention.

Figure 9 is an example of the least mean square circuit shown in figure 5 according to one embodiment of the invention.

Fig. 10 is a flowchart of a calibration method for an adpll according to an embodiment of the invention.

Fig. 11 is a simplified schematic diagram of an adpll according to another embodiment of the invention.

Fig. 12 is a schematic diagram of a storage device according to an embodiment of the invention.

Detailed Description

While various embodiments of the invention will be described below, it should be noted that elements of the various embodiments may be implemented in hardware (e.g., a device or circuit) or firmware (e.g., at least one program written on a microprocessor). Furthermore, the terms "first," "second," and the like in the following description are used only to define different elements, parameters, data, signals, or steps. And not to limit the order in which they are presented.

In an all-digital phase-locked loop (ADPLL) operation, a period of a clock signal CKV output by a Digitally Controlled Oscillator (DCO) is assumed to be T _V And a time-to-digital converter (TDC) depends on a phase difference between the clock signal CKV and the reference signal FREF (e.g., a time difference Δ t between a rising edge of the clock signal CKV and a rising edge of the reference signal FREF) _r ) Generating a digital output signal N _r The all-digital phase-locked loop needs to output a digital output signal N _r Normalizing to output a digital output signal N _r Conversion to a value between 0 and 1

(e.g., representing the phase difference between the clock signal CKV and the reference signal FREF as

Multiple T _V ) So as to be beneficial to subsequent operation. However, the result of the normalization is affected by the resolution Δ t of the time-to-digital converter _res (e.g., the time difference corresponding to the least significant bit of the digital output signal of the time-to-digital converter, or the unit delay of the time-to-digital converter)

While the resolution at of the time-to-digital converter _res The normalization operation also needs to be calibrated to the variation of resolution because it varies with the process-voltage-temperature (PVT) variation of the semiconductor.

FIG. 1 is a diagram of estimating the resolution Δ t of a time-to-digital converter according to one embodiment of the invention _res Schematic representation of (a). As shown in FIG. 1, the time-to-digital converter can detect the time difference Δ t between the rising edge of the clock signal CKV and the reference signal FREF _r And additionally detecting a time difference Δ t between a falling edge of the clock signal CKV and the reference signal FREF _f . As shown in fig. 1, Δ t _r And Δ t _f The difference between them is the half period T of the clock signal CKV _V A/2, and the time-to-digital converter (or its subsequent processing circuit) can be based on Δ t _r And Δ t _f The resolution Deltat of the time-to-digital converter is roughly calculated by the respective digital output signals _res 。

Fig. 2 is a circuit architecture of the time-to-digital converter 20 according to an embodiment of the invention, and fig. 3 is some signals involved in the circuit architecture shown in fig. 2. It should be noted that the circuit architecture shown in fig. 2 is only an example of the time-to-digital converter 20, and is not a limitation of the present invention. As shown in fig. 2, the time-to-digital converter 20 may include a plurality of inverters connected in series to form an inverter chain. Since each of these inverters causes a signal delay, the respective output signals D of these inverters<0>、D<1>、D<2>、…、D<L-1>And D<L>Each having a respective delay time with respect to the clock signal CKV input to the first inverter, as shown by D in fig. 3<0>、D<1>、D<2>、D<3>、D<4>、D<5>、D<6>And D<7>The delay introduced by one of the inverters is shown as the resolution Δ t of the time-to-digital converter 20 _res . In the present embodiment, the signal D is output<0>、D<1>、D<2>、…、D<L-1>And D<L>Are all inputted to the triggerAn input terminal (denoted as "D") of the flip-flop, and is output from an output terminal (denoted as "Q") of the flip-flop when triggered by a rising edge of the reference signal FREF, such as Q in fig. 3<0:L>As shown. In the present embodiment, the output signal Q<0:L>From 0 to 1 (e.g. Q)<1>Is 0 and Q<2>1) represents the falling edge of the clock signal CKV, and the output signal Q<0:L>From 1 to 0 (e.g. Q)<5>Is 1 and Q<6>0) represents the rising edge of the clock signal CKV. The time-to-digital converter 20 may then detect the output signal Q using a pseudo-thermometer code edge detector 22 (e.g., a detector for detecting transitions from 0 to 1 and transitions from 1 to 0 in a digital sequence) therein<0:L>And outputs a digital output signal N in binary format _r And N _f To respectively represent the time difference Δ t between the rising edge of the clock signal CKV and the reference signal FREF _r And the time difference Deltat between the falling edge of the clock signal CKV and the reference signal FREF _f (e.g., Δ t) _r ≈N _r ×Δt _res And Δ t _f ≈N _f ×Δt _res ) E.g. N _r =6 and N _f And (2). It should be noted that the circuit architecture of the time-to-digital converter 20 shown in fig. 2 is for illustrative purposes only and is not meant to limit the present invention. For example, the number of bits of the output signal of the time-to-digital converter 20 can vary according to system requirements, and L can be any positive integer.

Fig. 4 illustrates the normalization operation for the time-to-digital converter 20 according to an embodiment of the present invention. As shown in FIG. 4, the time-to-digital converter 20 can convert the digital output signal N obtained by the above operation into a digital output signal _r And N _f To the normalization circuit 30. First, the normalization circuit 30 can utilize the first calculation unit 31 (labeled "period average" for easy understanding) to perform the calculation shown in fig. 1 to obtain the average value of the period of the clock signal CKV

And the resolution deltat of the time-to-digital converter 20 _res Then using a second calculation sheetElement 32 (labeled as

To facilitate understanding) will

Is output in 12-bit binary form (e.g. signal PERINV), and then the digital output signal N is output by the multiplier 33 _r Multiplied by the signal PERINV to produce W _F Bit (e.g. W) _F = 15) and finally passes through a third calculating unit 34 (labeled as "2 ^ W ^ b ^ c) _F - (x) ') the multiplication result is converted into an unsigned 2's complement and output as a signal epsilon, where W is _F The binary signal epsilon of the bit can be expressed in the form of discrete data (e.g. k-th data) as follows:

it should be noted that, when the duty cycle of the clock signal CKV is not 50%, the average value of the period of the clock signal CKV is obtained

And the resolution deltat of the time-to-digital converter 20 _res May need to be implemented using relatively complex hardware. Furthermore, the above estimation method is also limited by the resolution Δ t of the time-to-digital converter 20 _res Therefore, there is an estimation error that degrades the performance of the adpll (e.g., output jitter/spurs (spurs) are too large).

For simplicity, the following figures are illustrated in decimal form. Fig. 5 is a simplified schematic diagram of the adpll 50 according to an embodiment of the invention, wherein the adpll 50 can include a time-to-digital converter 500, a numerically controlled oscillator 510 (shown as a sine wave in a circle for ease of understanding), a normalization circuit 520, an accumulator 530 (labeled "sigma" for ease of understanding), a Low Pass Filter (LPF), and a Low Pass Filter (LPF)) 540 (shown as a square with a low-pass response waveform for ease of understanding) and an adder 550 (shown as a circle with a plus sign for ease of understanding). In this embodiment, the parameter FCW _ F may be set to a ratio between the target frequency of the clock signal CKV and the frequency of the reference signal FREF, and the accumulator 530 may continuously accumulate the parameter FCW _ F to output the accumulated result as the reference phase. The time-to-digital converter is coupled to the numerically controlled oscillator and is used for generating a digital output signal N according to a phase difference between the clock signal CKV and the reference signal FREF _r [k](e.g. N) _r The value at the kth period of the reference signal FREF). A normalization circuit can be coupled to the time-to-digital converter and can be used for adjusting the gain parameter K _TDC Converting the digital output signal into a clock phase value

(e.g. in

Value at the kth period of the reference signal FREF), wherein the clock phase value is set to the value

Can be regarded as a digital output signal N _r [k]And (5) carrying out a normalized result. The adder 550 subtracts the reference phase and the real-time phase (e.g., the accumulated result of the real-time ratio between the real-time frequency of the clock signal CKV and the frequency of the reference signal FREF) to obtain the phase difference value

(e.g. in

The value at the kth period of the reference signal FREF) for the low pass filter 540 to generate the frequency control signal according to the phase difference value to control the dco 510 to generate the clock signal CKV according to the frequency control signal, so that the real-time frequency of the clock signal CKV gradually converges to the target frequency.

It is noted that the digital output signal N generated by the time-to-digital converter 500 _r [k]And normalized clock phase value

Only the fractional part of the instantaneous phase is represented, while the integer part of the instantaneous phase can be implemented by a counter. Since the operation of using the counter to generate the integer part of the instantaneous phase is well known in the art and does not affect the implementation of the calibration for the time-to-digital converter 500 and the normalization circuit 520 in the present invention, the counter is not shown in the drawings for simplicity and the details thereof are not described herein. Similarly, the reference phase value output by accumulator 530 shown in FIG. 5

(e.g. in

The value at the kth period of the reference signal FREF) is also used to represent only the fractional part of the reference phase for simplicity.

In the embodiment shown in FIG. 5, the normalization circuit 520 may comprise a multiplier 521 for converting the digital output signal N _r [k]Multiplying by a gain parameter K _TDC To generate clock phase values

And a gain parameter K _TDC The correct value of (c) can be calculated by the following equation:

wherein t is _res May represent the resolution of the time-to-digital converter 500 (e.g., Δ t, discussed above) _res ) And T is _DCO May represent the period of the clock signal CKV output by the numerically controlled oscillator 510 (e.g., T as described above) _V Or

). Due to the resolution t of the time-to-digital converter 500 _res Is quite sensitive to PVT variation (e.g. t at 25 deg.C) _res T is 13 picoseconds (ps for short) at 25 DEG C _res 10 ps) so that the gain parameter K varies between different temperatures _TDC There will be a gain error (gain error) and the gain parameter K _TDC Can lead to the occurrence of unwanted frequency components such as fractional spurs.

For example, assume that the frequency of the reference signal FREF is 40MHz, the ratio FCW between the target frequency of the clock signal CKV and the frequency of the reference signal FREF is 125.25, and the expected resolution (resolution) t _res 10ps and a target frequency f of the clock signal CKV _DCO At 5010MHz, then K _TDC About 0.05.

FIGS. 6-8 show clock phases at frequencies based on the clock signal CKV and the reference signal FREF

Reference phase

And a phase difference

Numerical values in different cases. As shown in fig. 6, in each period of the reference signal FREF, the digital output signal N _r In the order of 5, 10, 15 and 0, reference phase

0.25, 0.5, 0.75 and 0 in that order. At a gain parameter K _TDC In the absence of gain error (e.g. true resolution t) _res Corresponding gain parameter (i.e. t) _res /T _DCO ) And for the gain parameter K _TDC All of which are 0.05), the clock phase

0.25, 0.5, 0.75 and 0 in this order, thereby obtaining a phase difference

Are all maintained at 0. When the gain parameter K is preset _TDC With an error of-20% (e.g., 0.04), which results in a clock phase

A phase difference of 0.2, 0.4, 0.6 and 0 in this order

There is still a positive phase difference (e.g., 0.05, 0.1, 0.15, and 0) in the locked state, as shown in FIG. 7. When the gain parameter K is preset _TDC With an error of +20% (e.g., 0.06), which results in a clock phase

The order of 0.3, 0.6, 0.8 and 0 to make the phase difference

There is still a negative phase difference (e.g., -0.05, -0.1, -0.15, and 0) in the locked state, as shown in fig. 8.

As can be seen from the above example, the gain parameter K _TDC And the digital output signal N _r [k]And a phase difference

Has relevance. For example, the larger the value of N _r [k]Will result in a larger phase difference

Also for example, the gain parameter K _TDC Positive gain error of (2) results in a negative phase difference

While the gain parameter K _TDC When the gain error is negative, a positive phase difference is caused

Therefore, embodiments of the present invention provide a calibration method and a corresponding architecture for outputting a digital output signal N _r [k]And/or phase difference

For correcting the gain parameter K _TDC 。

As shown in fig. 5, in addition to the multiplier 521, the normalization circuit 520 may further include a multiplier 522 and a Least Mean Square (LMS) circuit 523 (denoted as LMS for simplicity), wherein the LMS circuit 523 is coupled between the

multipliers

521 and 522. In the embodiment, the normalization circuit 520 can be based on the clock phase value

And a reference phase value

The value of the phase difference between

Adjusting a gain parameter K _TDC . Specifically, when the phase difference value is larger

Is positive (as shown in FIG. 7), the gain parameter K is shown _TDC With negative error (e.g. gain parameter K) _TDC Less than t _res /T _DCO ) Therefore, the normalization circuit 520 can increase the gain parameter K _TDC (ii) a And when the phase difference value

Is negative (as shown in FIG. 8), and represents the gain parameter K _TDC With positive error (e.g. gain parameter K) _TDC Greater than t _res /T _DCO ) The normalization circuit 520 can reduce the gain parameter K _TDC 。

In the present embodiment, normalizationThe circuit 520 may be based on the phase difference value

And a digital output signal N _r Adjusting a gain parameter K _TDC . For example, the normalization circuit 520 can be based on the phase difference value

And the digital output signal N _r Product of (2)

Adjusting a gain parameter K _TDC . As shown in FIG. 5, the normalization circuit 520 may calculate the phase difference value using a multiplier

And the digital output signal N _r Product of (2)

For the least mean square circuit 523 to base

Adjusting gain parameter K according to the calculation result _TDC 。

Figure 9 is an example of the least mean square circuit 523 shown in figure 5 in accordance with one embodiment of the present invention. As shown in fig. 9, the least mean square circuit 523 may include a multiplier 524 and an accumulator 525 (labeled "Σ" for ease of understanding). In this embodiment, the least mean square circuit 523 can be used to determine the phase difference value

And the digital output signal N _r Product of (2)

And during the current period (e.g., the k-1 th of the reference signal FREF)Period) used by the current gain parameter K _TDC [k-1]Generating a next gain parameter K for a next (next) period, e.g. the kth period of the reference signal FREF _TDC [k]. For example, the multiplier 522 may be 19-bit

And a 6-bit digital output signal N _r [k]Multiplying to produce a 25-bit product

Multiplier 524 may multiply the above-mentioned products

Further multiplied by a predetermined value mu and the result of the multiplication may be accumulated by accumulator 525 to gain parameter K _TDC [k-1]To obtain a 16-bit gain parameter K _TDC [k]Where the predetermined value μmay be any suitable constant, and the correlation operation may be expressed as discrete data as follows:

it should be noted that the above operation and the structure shown in FIG. 9 are only the least mean square circuit 523 for the gain parameter K _TDC An example of the adjustment is made and not a limitation of the invention. All can be based on the phase difference value

And/or digital output signal N _r [k]A gain parameter K _TDC Gradually adjust/converge to t _res /T _DCO The embodiments of the present invention are all within the scope of the present invention.

Fig. 10 is a flowchart illustrating a calibration method for the adpll according to an embodiment of the invention, wherein the calibration method can be applied to the adpll 50 shown in fig. 5. It should be noted that one or more steps may be added, modified or deleted in the flowchart shown in fig. 10 as long as the overall result is not obstructed, and the steps do not necessarily have to be executed completely in the order shown in fig. 10.

In step 1010, the adpll 50 generates a clock signal CKV according to the frequency control signal by using the dco 510.

In step 1020, the adpll 50 generates a digital output signal N according to the phase difference between the clock signal CKV and the reference signal FREF by the time-to-digital converter 500 _r [k]。

In step 1030, the adpll 50 utilizes the normalization circuit 520 to adjust the gain parameter K _TDC Will digital output signal N _r [k]Conversion to clock phase value

In step 1040, the adpll 50 utilizes the normalization circuit 50 to derive a clock phase value

And a reference phase value

The value of the phase difference between

Adjusting a gain parameter K _TDC 。

To sum up, the embodiments of the present invention provide an all-digital phase-locked loop and a calibration method thereof, which can be based on the phase difference value

And the signal N output by the time-to-digital converter _r Judging the gain parameter K _TDC And a mechanism for feedback correction is established such that the gain parameter K is _TDC Can gradually converge to the correct value. In addition, the present inventionThe proposed calibration mechanism is not limited by the resolution of the time-to-digital converter, and especially the accuracy of the calibration can be determined by the bit number design of the computing units (such as the

multipliers

521 and 522 and the least mean square circuit 523) inside the normalization circuit 520. Therefore, the invention can be used for measuring the parameters related to the time-to-digital converter (such as the gain K of the time-to-digital converter) under the condition of no side effect or less side effect _TDC ) Converge to the correct or optimal value.

In the foregoing embodiment, the normalization circuit 520 in FIG. 5 corrects the gain parameter K in real time _TDC . However, due to the gain parameter K _TDC Will be subjected to the last gain parameter K _TDC And the current phase difference

May have the effect that the digital output signal N may be made _r Even with the same value, a gain parameter K with a large difference may be generated _TDC This, in turn, affects the linearity of the time-to-digital converter 500.

Therefore, the present invention further provides an all-digital phase-locked loop and a calibration method thereof, wherein one of a plurality of stored candidate gain parameters is selected as the gain parameter corresponding to the digital output signal Nr. In one embodiment, the candidate gain parameter is generated by the normalization circuit 520 according to previous phase difference values and previous digital output signals. For example, by phase difference value

And a digital output signal N _r [n-2]Generating candidate gain parameters K _TDC [n-2]By the phase difference value

And a digital output signal N _r [n-1]Generating a candidate gain parameter K _TDC [n-1]And by the value of the phase difference

And a digital output signal N _r [n]Generating a candidate gain parameter K _TDC [n]. Candidate gain parameter K _TDC [n-2]、K _TDC [n-1]And K _TDC [n]Is temporarily stored in the normalization circuit 520. When the value of the digital output signal Nr is again N _r [n]Then, a candidate gain parameter K is selected from the stored plurality of candidate gain parameters _TDC [n]Output to the multiplier 521, rather than generating the gain parameter K in real time as in the embodiment of FIG. 5 _TDC 。

Fig. 11 is a simplified schematic diagram of an adpll according to another embodiment of the invention. In the embodiment of fig. 11, in addition to the components shown in fig. 5, the normalization circuit 1100 further includes a multiplexer 1101, a storage device 1103, a demultiplexer 1105, and a first delay circuit 1107. The multiplexer 1101 is controlled by the digital output signal Nr [ k ]. The demultiplexer 1105 is controlled by the delayed digital output signal Nr [ kd ] and coupled to the output of the least mean square circuit 523. The storage device 1103 is coupled to a plurality of inputs of the multiplexer 1101 and a plurality of outputs of the demultiplexer 1105 for storing the candidate gain parameters. In one embodiment, the storage device 1103 includes a plurality of registers for storing candidate gain parameters. The first delay circuit 1107 is coupled to the multiplexer 1101 and the demultiplexer 1105 and is configured to receive the digital output signal Nr [ k ] to generate a delayed digital output signal Nr [ kd ].

In the embodiment of FIG. 11, the multiplexer 1101 first outputs the digital output signal Nr [ k ]]Selecting corresponding candidate gain parameters as gain parameters K _TDC . The least mean square circuit 523 then outputs a signal Nr kd based on the delayed digital output signal]And phase difference

Generating a corresponding digital output signal Nr [ kd ]]With respect to the candidate gain parameter, the normalization circuit 1100 may normalize the output signal Nr [ kd ] according to the corresponding digital output signal]Updates the corresponding digital output signal Nr [ k ] stored in the storage device 1103]The candidate gain parameter of (2). In one embodiment, the candidate gain parameters are not updated, but rather are based on the digital output signal Nr k]After the corresponding candidate gain parameters are generated,the same candidate gain parameters are used all the time without changing.

Fig. 12 is a schematic diagram of a storage device 1103 according to an embodiment of the present invention, which further stores candidate gain parameters in the storage device 1103. As shown in FIG. 12, the storage device 1103 includes a plurality of registers Re1 \8230, ren, a plurality of adders 1201 u 1 \8230, 1201 u n and a plurality of second delay circuits 1203 u 1 \82301203u. Register Re1 8230n for storing candidate gain parameters K _TDC1 …K _TDCn . The adders 1201_1 \8230and1201 _nare respectively coupled to one of the registers Re1 \8230andren and to the demultiplexer 1105. The second delay circuit 1203_1 _8230, 1203 _nare respectively coupled to one of the registers Re1 _8230, ren and one of the adders 1201_1 _8230, 1201 _n. In the embodiment of FIG. 12, the candidate gain parameter K originally temporarily stored in the register Re1 \8230n _TDC1 …K _TDCn Will be delayed by the second delay circuit 1203 u 1 8230n, 1203 u n, and according to the delayed digital output signal Nr kd]And the generated gain parameters are added to generate new candidate gain parameters and updated into the register Re1.

For example, if the time-to-digital converter 1100 in FIG. 11 generates the digital output signal Nr [1 ]]Then the multiplexer 1101 shown in FIG. 11 outputs the digital output signal Nr [1 ]]Controls to output the candidate gain parameter K stored in the register Re1 _TDC1 As a gain parameter K _TDC . Digital output signal Nr [1 ]]Will be delayed by the first delay circuit 1107 of FIG. 11 to generate a delayed digital output signal Nr [1d ]](not shown). The least mean square circuit 523 outputs a signal Nr [1d ] according to the delayed digital output signal]And phase difference

Generating a delay gain parameter K _TDC1d Adder 1201 u 1 will then delay gain parameter K _TDC1d And a candidate gain parameter K _TDC1 Added and updated to the register Re1.

It should be noted that the embodiments shown in fig. 11 and 12 are only examples, and any circuit architecture capable of achieving the same functions should be considered within the scope of the present invention. The calibration method of the adpll obtained by the embodiments of fig. 11 and fig. 12 comprises the following steps: generating a clock signal by using a digital control oscillator in the all-digital phase-locked loop according to a frequency control signal; generating a digital output signal by a time-to-digital converter in the all-digital phase-locked loop according to the phase difference between the clock signal and a reference signal; converting the digital output signal into a clock phase value by using a normalization circuit in the all-digital phase-locked loop according to a gain parameter; and selecting one of the stored candidate gain parameters as the gain parameter by using the normalization circuit corresponding to the digital output signal. Other detailed steps can be easily derived from the above embodiments, and thus are not described herein again.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should be covered by the present invention.

Description of the symbols

CKV clock signal

FREF reference signal

Δt _r 、Δt _f Time difference

T _V Period of time

20: time-to-digital converter

D <0>, D <1>, D <2>, D <3>, D <4>, D <5>, D <6>, D <7> to D < L-1>, D < L > and output signals

Q <0>, Q <1>, Q <2> to Q < L-1>, Q < L > and output signals

N _r 、N _f Digital output signal

30 normalization circuit

31 first calculation unit

32 second calculation unit

33 multiplier

34 third calculation unit

PERINV, ε signals

50 all-digital phase-locked loop

500 time-to-digital converter

510 digitally controlled oscillator

520. 1100 normalization circuit

521. 522 multiplier

523 least mean square circuit

524 multiplier

525 accumulator

530 accumulator

540 Low pass Filter

550. 1201\ u 1 \8230, 1201 _nadder

FCW _ F parameter

Clock phase value

Reference phase value

Numerical value of phase difference

N _r [k]Digital output signal

K _TDC Gain parameter

1010. 1020, 1030, 1040 step

1101. Multiplexer

1103. Storage device

1105. Demultiplexer

1107. First delay circuit

1203 u 1 \ 8230and 1203 u n second delay circuit

Re1 \ 8230and Ren register.

Claims

1. An all-digital phase-locked loop, comprising:

a digital control oscillator for generating a clock signal according to the frequency control signal;

a time-to-digital converter, coupled to the numerically controlled oscillator, for generating a digital output signal according to a phase difference between the clock signal and a reference signal; and

a normalization circuit, coupled to the time-to-digital converter, for converting the digital output signal into a clock phase value according to a gain parameter;

wherein the normalization circuit selects one of the stored candidate gain parameters as the gain parameter corresponding to the digital output signal.

2. The adpll of claim 1, wherein the candidate gain parameters are generated by the normalization circuit based on a plurality of previous values of the phase difference and a plurality of previous values of the digital output signal.

3. The adpll of claim 2, wherein the normalization circuits generate the candidate gain parameters based on products of one of the phase difference values and one of the digital output signals, respectively.

4. The adpll of claim 3, wherein the normalization circuit comprises a least mean square circuit for generating a next gain parameter for a next cycle based on a product of the phase difference value and the digital output signal and a current gain parameter used in the current cycle.

5. The adpll of claim 3, wherein the normalization circuit further comprises:

a multiplexer controlled by the digital output signal to output one of the candidate gain parameters as the gain parameter;

a demultiplexer controlled by the delayed digital output signal and receiving a delay gain parameter generated according to the delayed digital output signal, the delay gain parameter being used to update the corresponding candidate gain parameter;

a storage device coupled to the input terminals of the multiplexer and the output terminals of the demultiplexer for storing the candidate gain parameters;

the first delay circuit is coupled to the multiplexer and the demultiplexer for receiving the digital output signal to generate the delayed digital output signal.

6. The adpll of claim 5, wherein the normalization circuit further comprises:

a plurality of registers for storing the candidate gain parameters;

a plurality of adders respectively coupled to one of the registers and to the demultiplexer; and

and a plurality of second delay circuits respectively coupled to one of the registers and one of the adders.

7. A calibration method for an all-digital phase-locked loop, comprising:

generating a clock signal by using a digital control oscillator in the all-digital phase-locked loop according to a frequency control signal;

generating a digital output signal by a time-to-digital converter in the all-digital phase-locked loop according to the phase difference between the clock signal and a reference signal;

converting the digital output signal into a clock phase value by using a normalization circuit in the all-digital phase-locked loop according to a gain parameter; and

the normalization circuit is used to select one of a plurality of candidate gain parameters stored in correspondence with the digital output signal as the gain parameter.

8. The method of claim 7, wherein the candidate gain parameters are generated by the normalization circuit according to a plurality of previous phase difference values and a plurality of previous digital output signals.

9. The calibration method of claim 7, wherein the step of converting the digital output signal into the clock phase value according to the gain parameter by the normalization circuit in the adpll comprises:

the digital output signal is multiplied by the gain parameter by the normalization circuit to generate the clock phase value.

10. The calibration method of claim 9, wherein the step of selecting one of a plurality of candidate gain parameters stored in correspondence with the digital output signal by the normalization circuit as the gain parameter comprises:

delaying the digital output signal to produce a delayed digital output signal;

controlling a multiplexer by the digital output signal;

controlling the demultiplexer with the delayed digital output signal; and

the multiplexer controls one of the candidate gain parameters in the storage device to be output, and the demultiplexer controls the storage device to receive the delay gain parameter generated according to the delay digital output signal, wherein the delay gain parameter is used for updating the corresponding candidate gain parameter.