CN113162613B - Linear phase error comparator applied to phase-locked loop of image sensor - Google Patents

Linear phase error comparator applied to phase-locked loop of image sensor Download PDF

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Publication number
CN113162613B
CN113162613B CN202110581803.0A CN202110581803A CN113162613B CN 113162613 B CN113162613 B CN 113162613B CN 202110581803 A CN202110581803 A CN 202110581803A CN 113162613 B CN113162613 B CN 113162613B
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pmos transistor
gate
output
clock signal
transistor
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CN113162613A (en
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常玉春
周滔
申人升
冯国林
王志硕
刘岩
娄珊珊
钟国强
曲杨
程禹
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Dalian University of Technology
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Dalian University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The invention relates to the technical field of analog integrated circuits, and provides a linear phase error comparator applied to a phase-locked loop of an image sensor, which comprises the following components: a ramp generator and a control signal generation circuit; the control signal generating circuit is used for sampling and comparing an input reference clock signal and an output clock signal to generate a control signal containing phase difference information and used for controlling charge and discharge of the slope generator; the ramp generator includes: a reference current source, a voltage follower, a first capacitor, a reference voltage source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The invention can realize linear and continuous phase error comparison, reduce quantization noise of the phase error comparator and realize a low-noise phase-locked loop.

Description

Linear phase error comparator applied to phase-locked loop of image sensor
Technical Field
The present invention relates to the field of analog integrated circuits, and more particularly, to a linear phase error comparator applied to a phase-locked loop of an image sensor.
Background
In recent years, CMOS image sensors have been widely used in people's lives due to their high integration and low cost. A Phase Locked Loop (PLL) is an important component of a CMOS image sensor, and provides a basic clock signal to modules such as an analog-to-digital converter, an interface circuit, etc. of the CMOS image sensor, which has a critical influence on the performance of the CMOS image sensor.
CMOS image sensors can be classified into analog Charge Pump Phase Locked Loop (CPPLL) and All Digital Phase Locked Loop (ADPLL) according to the type of phase locked loop. The analog charge pump phase-locked loop has the characteristics of good phase noise performance, higher design complexity and power consumption than the all-digital phase-locked loop, low design complexity, easiness in process migration, low power consumption and the like. All-digital phase-locked loops gradually become the mainstream trend of phase-locked loop circuit design, but the in-band noise performance of all-digital phase-locked loops is inferior to that of analog charge pump phase-locked loops due to the influence of quantization noise of fractional phase error comparators.
The time-to-digital converter (TDC, time Digital Converter) is an important component of an all-digital phase-locked loop, acting as a fractional phase error comparator. The performance of the fractional phase error comparator directly affects the accuracy and power consumption of the all-digital phase locked loop. Two important performance parameters of the phase error comparator are resolution and power consumption. The resolution of the phase error comparator directly affects the level of quantization noise. If the time resolution of a unit of the phase error comparator is too low, this will result in the quantization noise of the phase error comparator reaching a high level, further affecting the in-band phase noise of the output of the phase locked loop. The resolution of the phase error comparator has a crucial influence on the phase noise of the phase locked loop.
The architecture adopted by the current phase error comparator is based on the structure of an inverter and a trigger. The resolution of the phase error comparator is mainly determined by the delay of the unit inverter, which is greatly affected by process variation, temperature variation and voltage variation, and an additional compensation circuit is needed to compensate the delay of the unit inverter. In addition, in the digital-analog hybrid integrated circuit, the digital circuit and the analog circuit have different general working voltages, and cannot share the same set of power ground, so that the power consumption is high.
Disclosure of Invention
The invention mainly solves the technical problem that quantization noise in the traditional fractional phase error is difficult to eliminate, and provides a linear phase error comparator applied to an image sensor phase-locked loop, which can be used in a large-scale image sensor all-digital phase-locked loop and has the characteristics of low noise and low power consumption. The invention can realize linear and continuous phase error comparison, reduce quantization noise of the phase error comparator and realize a low-noise phase-locked loop. Meanwhile, the invention can reduce the power supply voltage of the whole circuit and realize a phase-locked loop with low power consumption and low noise.
The invention provides a linear phase error comparator applied to a phase-locked loop of an image sensor, which comprises the following components: a ramp generator and a control signal generation circuit;
the control signal generating circuit is used for sampling and comparing an input reference clock signal CLKA and an output clock signal CLKB to generate a control signal containing phase difference information and used for controlling charge and discharge of the slope generator;
the ramp generator includes: a reference current source i_ref, a voltage follower Buffer, a first capacitor cap, a reference voltage source v_ref, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a first NMOS transistor MN1, and a second NMOS transistor MN2;
the source electrode of the first PMOS transistor MP1 is connected with a power supply, and the drain electrode and the grid electrode of the first PMOS transistor MP1 are connected with a reference current source I_ref; the reference current source I_ref is connected with ground;
the source stages of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to a power supply, and the gates of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to the gate of the first PMOS transistor MP 1; the drain of the second PMOS transistor MP2 is connected to the source of the fifth PMOS transistor MP5, the drain of the third PMOS transistor MP3 is connected to the source of the sixth PMOS transistor MP6, and the drain of the fourth PMOS transistor MP4 is connected to the source of the seventh PMOS transistor MP 7;
the gate of the fifth PMOS transistor MP5 is connected to the first control signal EN1, the gate of the sixth PMOS transistor MP6 is connected to the second control signal EN2, and the gate of the seventh PMOS transistor MP7 is connected to the third control signal EN3; the drains of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the drains of the eighth PMOS transistor MP8 and the first NMOS transistor MN 1;
the sources of the eighth PMOS transistor MP8 and the first NMOS transistor MN1 are connected to the drain of the ninth PMOS transistor MP9, the drain of the second NMOS transistor MN2, and the upper plate of the first capacitor cap; the eighth PMOS transistor MP8 and the first NMOS transistor MN1 form a first transmission gate TG1; the drain of the ninth PMOS transistor MP9 and the second NMOS transistor MN2 form a second transmission gate TG2;
the sources of the ninth PMOS transistor MP9 and the second NMOS transistor MN2 are connected with the positive electrode of a reference voltage source V_ref;
a gate of the eighth PMOS transistor MP8 is connected to the first output signal CLKAb of the control signal generating circuit, and a gate of the first NMOS transistor MN1 is connected to the input reference clock signal CLKA;
a gate of the ninth PMOS transistor MP9 is connected to the second output signal clk2 of the control signal generating circuit, and a gate of the second NMOS transistor MN2 is connected to the third output signal clk2b; the third output signal clk2b is an inverted signal of the second output signal clk 2;
the upper polar plate of the first capacitor cap is connected with the positive input end of the voltage follower Buffer; the output end of the voltage follower Buffer is connected with the negative input end;
the lower polar plate of the first capacitor cap is connected with the positive electrode of a reference voltage source V_ref, and the negative electrode of the reference voltage source V_ref is grounded.
Preferably, the control signal generation circuit includes: a two-input AND gate, a two-input OR gate, a D trigger, a first switch S1, a second switch S2, a first inverter and a second inverter;
a first input end of the OR gate is connected with an input reference clock signal CLKA, a second input end of the OR gate is connected with an output clock signal CLKB, and an output end of the OR gate is connected with a first switch S1; the first switch S1 is connected with a first inverter; the first inverter inputs a second output signal clk2 and outputs a third output signal clk2b;
the first input end of the AND gate is connected with an input reference clock signal CLKA, the second input end of the AND gate is connected with an output clock signal CLKB, and the output end of the AND gate is connected with a second switch S2; the second switch S2 is connected with the first inverter;
the input end of the D trigger is connected with the output clock signal CLKB, the clock signal of the D trigger is connected with the input reference clock signal CLKA, the output Q end of the D trigger is connected with the second switch clock signal clk1, and the output of the D triggerThe terminal is connected with a first switch clock signal clk1 b;
an input terminal of the second inverter is connected to the input reference clock signal CLKA, and an output terminal of the second inverter outputs the first output signal CLKAb.
Preferably, the method further comprises: a switched capacitor array voltage doubling circuit;
the switched capacitor array voltage doubling circuit comprises: a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, and a second capacitor;
the input ends of the third transmission gate and the fourth transmission gate are connected with a power supply;
the output end of the third transmission gate is connected with the input end of the sixth transmission gate and the upper polar plate of the second capacitor;
the output ends of the fourth transmission gate and the fifth transmission gate are connected with the lower polar plate of the second capacitor;
the input end of the fifth transmission gate is connected with the ground;
the output end of the sixth transmission gate outputs a multiplied voltage signal.
Preferably, the width-to-length ratio parameters of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are the same;
the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 have the same width-to-length ratio parameters.
The linear phase error comparator applied to the phase-locked loop of the image sensor can be applied in different scenes by controlling the slope of the slope voltage through the control word; the clock signal containing the phase difference information is used for controlling the transmission gate to reset and charge the capacitor, so that the continuous and high-linearity phase error comparator design can be realized, and the characteristics of high linearity and low noise are realized. The control signal generating circuit obtains the phase difference information of the input reference clock and the output clock through the AND gate, the NOT gate and the switch, and has the characteristics of simple structure and low power consumption. In the switched capacitor array voltage doubling circuit, the power supply voltage is multiplied through the switched capacitor array and then the phase comparator is powered, so that the low-power-consumption phase-locked loop can be realized by reducing the power supply voltage. The invention can realize continuous and linear phase comparison, reduce noise level and power consumption while utilizing the advantages of the digital phase-locked loop, realize the phase-locked loop with low noise and low power consumption, well cooperate with a slope analog-to-digital converter in an image sensor, realize the image sensor with low power consumption, improve the precision of the phase-locked loop in a CMOS image sensor, reduce the noise of the PLL, and simultaneously reduce the power consumption, further improve the performance of the CMOS image sensor, and eliminate the influence of quantization noise brought by a traditional fractional phase error comparator based on an inverter; the design of the CMOS image sensor with large-scale low noise and low power consumption is facilitated.
Drawings
FIG. 1 is a schematic circuit diagram of a linear phase error comparator applied to an image sensor phase locked loop according to the present invention;
FIG. 2 is a schematic circuit diagram of a control signal generation circuit provided by the present invention;
FIG. 3 is a schematic circuit diagram of a switched capacitor array voltage doubling circuit provided by the invention;
FIG. 4 is a timing chart of the control signal generating circuit according to the present invention;
fig. 5 is a timing chart of the operation of the linear phase error comparator applied to the phase-locked loop of the image sensor according to the present invention.
Detailed Description
In order to make the technical problems solved by the invention, the technical scheme adopted and the technical effects achieved clearer, the invention is further described in detail below with reference to the accompanying drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the matters related to the present invention are shown in the accompanying drawings.
As shown in fig. 1, a linear phase error comparator applied to a phase-locked loop of an image sensor according to an embodiment of the present invention includes: the switching capacitor comprises a slope generator, a control signal generating circuit and a switching capacitor array voltage doubling circuit.
The ramp generator can generate ramp signals to realize phase comparison, and comprises: a reference current source i_ref, a voltage follower Buffer, a first capacitor cap, a reference voltage source v_ref, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a first NMOS transistor MN1, and a second NMOS transistor MN2; the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 have the same width-to-length ratio parameters; the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 have the same aspect ratio parameters.
The source electrode of the first PMOS transistor MP1 is connected with a power supply, and the drain electrode and the grid electrode of the first PMOS transistor MP1 are connected with a reference current source I_ref; the reference current source I_ref is connected with ground;
the source stages of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to a power supply, and the gates of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to the gate of the first PMOS transistor MP 1; the drain of the second PMOS transistor MP2 is connected to the source of the fifth PMOS transistor MP5, the drain of the third PMOS transistor MP3 is connected to the source of the sixth PMOS transistor MP6, and the drain of the fourth PMOS transistor MP4 is connected to the source of the seventh PMOS transistor MP 7;
the gate of the fifth PMOS transistor MP5 is connected to the first control signal EN1, the gate of the sixth PMOS transistor MP6 is connected to the second control signal EN2, and the gate of the seventh PMOS transistor MP7 is connected to the third control signal EN3; the drains of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the drains of the eighth PMOS transistor MP8 and the first NMOS transistor MN 1; the first control signal EN1, the second control information EN2, and the third control information EN3 are control signals of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7, respectively, and when the first control signal EN1, the second control information EN2, and the third control information EN3 are at a low level, the corresponding transistors are turned on, and a current is output to the drain terminals of the eighth PMOS transistor MP8 and the first NMOS transistor MN 1. When the first control signal EN1, the second control information EN2, and the third control information EN3 are set to high level, the transistor is in an off state, and no current passes. By controlling the first control signal EN1, the second control information EN2 and the third control information EN3, the magnitude of the current flowing through the first transmission gate TG1 can be adjusted, thereby realizing the adjustment of the sensitivity of the comparator and compensating the circuit when the temperature, the process and the voltage change. The input reference clock signal CLKA and the first output signal CLKAb are signals controlling the first transmission gate TG1, and the second output signal clk2 and the third output signal clk2b are signals controlling the second transmission gate TG2. The first, second and third output signals CLKAb, clk2b are generated by a control signal circuit.
The sources of the eighth PMOS transistor MP8 and the first NMOS transistor MN1 are connected to the drain of the ninth PMOS transistor MP9, the drain of the second NMOS transistor MN2, and the upper plate of the first capacitor cap; wherein the eighth PMOS transistor MP8 and the first NMOS transistor MN1 form a first transmission gate TG1; the drain of the ninth PMOS transistor MP9 and the second NMOS transistor MN2 form a second transmission gate TG2.
The sources of the ninth PMOS transistor MP9 and the second NMOS transistor MN2 are connected with the positive electrode of a reference voltage source V_ref;
a gate of the eighth PMOS transistor MP8 is connected to the first output signal CLKAb of the control signal generating circuit, and a gate of the first NMOS transistor MN1 is connected to the input reference clock signal CLKA;
a gate of the ninth PMOS transistor MP9 is connected to the second output signal clk2 of the control signal generating circuit, and a gate of the second NMOS transistor MN2 is connected to the third output signal clk2b; the third output signal clk2b is an inverted signal of the second output signal clk 2;
the upper polar plate of the first capacitor cap is connected with the positive input end of the voltage follower Buffer; the output end of the voltage follower Buffer is connected with the negative input end;
the lower polar plate of the first capacitor cap is connected with the positive electrode of a reference voltage source V_ref, and the negative electrode of the reference voltage source V_ref is grounded.
The control signal generating circuit is used for sampling and comparing an input reference clock signal CLKA and an output clock signal CLKB to generate a control signal containing phase difference information and used for controlling charge and discharge of the ramp generator. As shown in fig. 2, the control signal generating circuit includes: a two-input AND gate, a two-input OR gate, a D trigger, a first switch S1, a second switch S2, a first inverter and a second inverter;
a first input end of the OR gate is connected with an input reference clock signal CLKA, a second input end of the OR gate is connected with an output clock signal CLKB, and an output end of the OR gate is connected with a first switch S1; the first switch S1 is connected with a first inverter; the first inverter inputs a second output signal clk2 and outputs a third output signal clk2b;
the first input end of the AND gate is connected with an input reference clock signal CLKA, the second input end of the AND gate is connected with an output clock signal CLKB, and the output end of the AND gate is connected with a second switch S2; the second switch S2 is connected with the first inverter;
the input end of the D trigger is connected withAn output clock signal CLKB, a clock signal of the D trigger is connected with an input reference clock signal CLKA, an output Q end of the D trigger is connected with a second switch clock signal clk1, and an output of the D triggerThe terminal is connected with a first switch clock signal clk1 b;
an input terminal of the second inverter is connected to the input reference clock signal CLKA, and an output terminal of the second inverter outputs the first output signal CLKAb.
As shown in fig. 3, the switched capacitor array voltage doubling circuit realizes power supply voltage multiplication by fast switching of a capacitor charging and discharging loop, and includes: a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, and a second capacitor; the input ends of the third transmission gate and the fourth transmission gate are connected with a power supply (VDD); the output end of the third transmission gate is connected with the input end of the sixth transmission gate and the upper polar plate of the second capacitor; the output ends of the fourth transmission gate and the fifth transmission gate are connected with the lower polar plate of the second capacitor; the input end of the fifth transmission gate is connected with the ground; the output terminal of the sixth transmission gate outputs a multiplied voltage signal (vdd_double).
The invention can realize voltage multiplication through the switched capacitor array voltage doubling circuit, thereby supplying power to the linear phase comparator by using the power supply voltage of the oscillator. Therefore, the power supply voltage is reduced, and the design of the low-power-consumption phase-locked loop is realized.
The working principle of the linear phase error comparator applied to the phase-locked loop of the image sensor provided by the embodiment of the invention is as follows:
the drain electrode of the first PMOS transistor MP1 is connected to the reference current source i_ref, so that the current flowing through the first PMOS transistor MP1 is equal to the current value of the reference current source i_ref, and the gate electrode of the first PMOS transistor MP1 is connected to the gate electrodes of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4, so as to form a current mirror structure, so that the current of the first PMOS transistor MP1 is copied to the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4. The drains of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are respectively connected to the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7, so that the magnitudes of the currents flowing through the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are respectively equal to the magnitudes of the currents flowing through the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4.
The fifth PMOS transistor MP5 is controlled by the first control signal EN1, the sixth PMOS transistor MP6 is controlled by the second control signal EN2, the seventh PMOS transistor MP7 is controlled by the third control signal EN3, when one of the control signals is turned on, the current value flowing through the eighth PMOS transistor MP8 and the first NMOS transistor MN1 is the magnitude of one time reference current, when any two control signals are turned on, the current value flowing through the eighth PMOS transistor MP8 and the first NMOS transistor MN1 is the magnitude of two times reference current, and when all three control signals are turned on, the current value flowing through the eighth PMOS transistor MP8 and the first NMOS transistor MN1 is the magnitude of three times reference current. By changing the number of the control signals which are turned on, current values with different magnitudes can be realized. The sensitivity of the phase comparator can be adjusted to meet different requirements. At the same time, the influence of power supply voltage variation, process variation and temperature variation on the current can be compensated.
When the control signal is turned on, the linear phase error comparator provided by the invention has two working states, as shown in fig. 4. The case when the input reference clock signal CLKA phase leads the output clock signal CLKB phase and the case when the input reference clock signal CLKA phase lags the output clock signal CLKB phase, respectively.
When the phase of the input reference clock signal CLKA is advanced relative to the phase of the output clock signal CLKB, the rising edge of the input reference clock signal CLKA precedes the rising edge of the output clock signal CLKB, the first transmission gate TG1 is turned on, and a current flows to start charging the first capacitor cap. The voltage of the polar plate on the first capacitor cap is slowly increased to form an upward slope signal. When the falling edge of the input reference clock signal CLKA comes, the first transmission gate TG1 is turned off, and the plate voltage on the first capacitor cap remains unchanged and does not increase. Until the falling edge of the second output signal clk2 arrives, the second transmission gate TG2 is turned on, and the plate voltage on the first capacitor cap is reset to the voltage value of the reference voltage source v_ref. During the period, the voltage follower buffer outputs a ramp signal to be fed back to the oscillator, so that phase compensation is realized.
When the input reference clock signal CLKA is phase-delayed from the output clock signal CLKB, the rising edge of the input reference clock signal CLKA is later than the rising edge of the output clock signal CLKB, and when the rising edge of the input reference clock signal CLKA comes, the first transmission gate TG1 is turned on and a current flows to start charging the first capacitor cap. The voltage of the polar plate on the first capacitor cap is slowly increased to form an upward slope signal. When the falling edge of the second output signal clk2 arrives, the second transmission gate TG2 is turned on, and the plate voltage on the first capacitor cap is reset to the voltage value of the reference voltage source v_ref. During the period, the voltage follower buffer outputs a ramp signal to be fed back to the oscillator, so that phase compensation is realized.
The two operating states of the above linear phase error comparator differ in that the second output signal clk2 is generated by the control signal generating circuit for controlling the ninth PMOS transistor MP9.
Based on the above description, the control signal generating circuit also has two operation states, respectively, when the input reference clock signal CLKA phase is advanced from the output clock signal CLKB phase, and when the input reference clock signal CLKA phase is retarded from the output clock CLKB phase.
As shown in fig. 5, when the input reference clock signal CLKA is phase-advanced relative to the output clock signal CLKB, the rising edge of the input reference clock signal CLKA precedes the rising edge of the output clock signal CLKB. The input reference clock signal CLKA is used as the clock signal of the D flip-flop, the output clock signal CLKB is used as the input signal of the D flip-flop, the input reference clock signal CLKA performs rising edge sampling on the output clock signal CLKB, and the output clock signal CLKB is at a low level at this time, so the D flip-flop outputs the second switching clock signal clk1 at a low level and the first switching clock signal clk1b at a high level. Therefore, the first switch clock signal clk1b turns on the switch S1, signals of the input reference clock signal CLKA and the output clock signal CLKB after passing through one or gate are output through the first switch S1 to form a second output signal clk2, and the second output signal clk2 passes through the first inverter to form a third output signal clk2b signal. The second output signal clk2 and the third output signal clk2b are output to the ramp generator as control signals.
When the input reference clock signal CLKA is phase-delayed from the output clock signal CLKB, the rising edge of the input reference clock signal CLKA is later than the rising edge of the output clock signal CLKB. The input reference clock signal CLKA is used as the clock signal of the D flip-flop, the output clock signal CLKB is used as the input signal of the D flip-flop, the input reference clock signal CLKA performs rising edge sampling on the output clock signal CLKB, and the D flip-flop outputs the second switching clock signal clk1 with high level and the first switching clock signal clk1b with low level because the output clock signal CLKB is at high level. Therefore, the second switch clock signal clk1 turns on the switch S2, signals of the input reference clock signal CLKA and the output clock signal CLKB after passing through an and gate are outputted through the second switch S2 to form a second output signal clk2, and the second output signal clk2 passes through the first inverter to form a third output signal clk2b. The second output signal clk2 and the third output signal clk2b are output to the ramp generator as control signals.
In two different working states of the control signal generating circuit, the pulse widths of the generated second output signal clk2 and third output signal clk2b have obvious differences, when the phase of the input reference clock signal CLKA is advanced in comparison with the phase of the output clock signal CLKB, the pulse width is larger than half of the clock period of the input reference clock signal CLKA, so that the amplitude of the ramp signal is large, the pulse width is long, and the phase compensation can be realized more quickly. When operating with the input reference clock signal CLKA phase-delayed from the output clock signal CLKB, the output control signal pulse width is less than half the clock period of the input reference clock signal CLKA, enabling fast edge alignment of the two clock signals.
In addition, the oscillator operating voltage in the phase locked loop circuit is lower than that of the linear phase error comparator, thus in order to reduce power consumption. The invention is provided with the switched capacitor array voltage doubling circuit, and the working voltage is provided for the linear phase error comparator after the power supply voltage of the oscillator is doubled, so that the low power consumption requirement of the image sensor can be met.
The specific working mode of the switched capacitor array voltage doubling circuit is divided into two stages: in the first stage, the third and fifth transfer gates are turned on to charge the second capacitor and the upper plate is charged to VDD. The first and fifth transfer gates are then turned off, and the fourth and sixth transfer gates are turned on. Because the voltage at two ends of the second capacitor can not be suddenly changed, the voltage of the lower polar plate of the second capacitor is VDD, and the voltage of the upper polar plate is forced to be raised by two times as high as VDD_double, thereby realizing output voltage multiplication. The output voltage multiplication can be realized by controlling the quick on and off of the four transmission gates through clock signals. Meanwhile, the voltage-to-temperature (PVT) compensation circuit can be used as a compensation switch in voltage, temperature and process variation, and when the voltage, temperature and process variation occur, the voltage-to-temperature (PVT) multiplication circuit is started to increase the voltage, so that the compensation of PVT (process technology) variation is realized.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments is modified or some or all of the technical features are replaced equivalently, so that the essence of the corresponding technical scheme does not deviate from the scope of the technical scheme of the embodiments of the present invention.

Claims (4)

1. A linear phase error comparator for use in an image sensor phase locked loop, comprising: a ramp generator and a control signal generation circuit;
the control signal generating circuit is used for sampling and comparing an input reference clock signal CLKA and an output clock signal CLKB to generate a control signal containing phase difference information and used for controlling charge and discharge of the slope generator;
the ramp generator includes: a reference current source i_ref, a voltage follower Buffer, a first capacitor cap, a reference voltage source v_ref, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a first NMOS transistor MN1, and a second NMOS transistor MN2;
the source electrode of the first PMOS transistor MP1 is connected with a power supply, and the drain electrode and the grid electrode of the first PMOS transistor MP1 are connected with a reference current source I_ref; the reference current source I_ref is connected with ground;
the source stages of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to a power supply, and the gates of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to the gate of the first PMOS transistor MP 1; the drain of the second PMOS transistor MP2 is connected to the source of the fifth PMOS transistor MP5, the drain of the third PMOS transistor MP3 is connected to the source of the sixth PMOS transistor MP6, and the drain of the fourth PMOS transistor MP4 is connected to the source of the seventh PMOS transistor MP 7;
the gate of the fifth PMOS transistor MP5 is connected to the first control signal EN1, the gate of the sixth PMOS transistor MP6 is connected to the second control signal EN2, and the gate of the seventh PMOS transistor MP7 is connected to the third control signal EN3; the drains of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the drains of the eighth PMOS transistor MP8 and the first NMOS transistor MN 1;
the sources of the eighth PMOS transistor MP8 and the first NMOS transistor MN1 are connected to the drain of the ninth PMOS transistor MP9, the drain of the second NMOS transistor MN2, and the upper plate of the first capacitor cap; the eighth PMOS transistor MP8 and the first NMOS transistor MN1 form a first transmission gate TG1; the drain of the ninth PMOS transistor MP9 and the second NMOS transistor MN2 form a second transmission gate TG2;
the sources of the ninth PMOS transistor MP9 and the second NMOS transistor MN2 are connected with the positive electrode of a reference voltage source V_ref;
a gate of the eighth PMOS transistor MP8 is connected to the first output signal CLKAb of the control signal generating circuit, and a gate of the first NMOS transistor MN1 is connected to the input reference clock signal CLKA;
a gate of the ninth PMOS transistor MP9 is connected to the second output signal clk2 of the control signal generating circuit, and a gate of the second NMOS transistor MN2 is connected to the third output signal clk2b; the third output signal clk2b is an inverted signal of the second output signal clk 2;
the upper polar plate of the first capacitor cap is connected with the positive input end of the voltage follower Buffer; the output end of the voltage follower Buffer is connected with the negative input end;
the lower polar plate of the first capacitor cap is connected with the positive electrode of a reference voltage source V_ref, and the negative electrode of the reference voltage source V_ref is grounded.
2. The linear phase error comparator applied to an image sensor phase locked loop of claim 1, wherein the control signal generation circuit comprises: a two-input AND gate, a two-input OR gate, a D trigger, a first switch S1, a second switch S2, a first inverter and a second inverter;
a first input end of the OR gate is connected with an input reference clock signal CLKA, a second input end of the OR gate is connected with an output clock signal CLKB, and an output end of the OR gate is connected with a first switch S1; the first switch S1 is connected with a first inverter; the first inverter inputs a second output signal clk2 and outputs a third output signal clk2b;
the first input end of the AND gate is connected with an input reference clock signal CLKA, the second input end of the AND gate is connected with an output clock signal CLKB, and the output end of the AND gate is connected with a second switch S2; the second switch S2 is connected with the first inverter;
the input end of the D trigger is connected with the output clock signal CLKB, the clock signal of the D trigger is connected with the input reference clock signal CLKA, the output Q end of the D trigger is connected with the second switch clock signal clk1, and the output of the D triggerThe terminal is connected with a first switch clock signal clk1 b;
an input terminal of the second inverter is connected to the input reference clock signal CLKA, and an output terminal of the second inverter outputs the first output signal CLKAb.
3. The linear phase error comparator applied to an image sensor phase locked loop of claim 1 or 2, further comprising: a switched capacitor array voltage doubling circuit;
the switched capacitor array voltage doubling circuit comprises: a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, and a second capacitor;
the input ends of the third transmission gate and the fourth transmission gate are connected with a power supply;
the output end of the third transmission gate is connected with the input end of the sixth transmission gate and the upper polar plate of the second capacitor;
the output ends of the fourth transmission gate and the fifth transmission gate are connected with the lower polar plate of the second capacitor;
the input end of the fifth transmission gate is connected with the ground;
the output end of the sixth transmission gate outputs a multiplied voltage signal.
4. The linear phase error comparator applied to the phase locked loop of the image sensor as claimed in claim 3, wherein the aspect ratio parameters of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are the same;
the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 have the same width-to-length ratio parameters.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950957B1 (en) * 2000-09-11 2005-09-27 Adc Telecommunications, Inc. Phase comparator for a phase locked loop
CN1717868A (en) * 2003-03-04 2006-01-04 日本电信电话株式会社 Phase comparison circuit and CDR circuit

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JP2007067709A (en) * 2005-08-30 2007-03-15 Nec Electronics Corp Comparator circuit and semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950957B1 (en) * 2000-09-11 2005-09-27 Adc Telecommunications, Inc. Phase comparator for a phase locked loop
CN1717868A (en) * 2003-03-04 2006-01-04 日本电信电话株式会社 Phase comparison circuit and CDR circuit

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